Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146926698	1			T1	394842		T2	956858		T3	6142
instr_valid_dis	111922854	1			T1	89172		T2	494456		T3	6142
instr_en	25723557	1			T1	298000		T2	253920		T22	111014

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11970847	1			T2	92808		T22	55358		T16	11722
sram_ifetch_valid_disable	112658778	1			T1	261894		T2	610978		T3	6142
sram_ifetch_enable	22297073	1			T1	132948		T2	253072		T22	44574

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146926698	1			T1	394842		T2	956858		T3	6142
hw_debug_en_valid_off	113567064	1			T1	244130		T2	655758		T3	6142
hw_debug_en_on	22504015	1			T1	62746		T2	257026		T22	145524

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	112658778	1			T1	261894		T2	610978		T3	6142
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99058460	1			T1	42294		T2	430672		T3	6142
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10050076	1			T1	211930		T2	113914		T22	77622
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4125569	1			T2	29024		T64	28566		T138	37610
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1658190	1			T64	28566		T138	20000		T139	80312
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1568889	1			T2	10688		T139	74190		T135	28474
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4992488	1			T2	63784		T22	55358		T28	25738
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1616630	1			T2	43784		T22	25542		T28	25738
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2408378	1			T22	19310		T138	20038		T139	93254
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8807975	1			T1	7670		T2	96036		T22	70834
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3897220	1			T2	5984		T22	17624		T15	14818
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3680296	1			T2	64142		T22	6396		T7	47324

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10808478	1			T1	86070		T2	129318		T22	14082
lc_exec_en	8703552	1			T1	55076		T2	97206		T22	19332
valid_exec_dis	107308816	1			T1	213136		T2	494460		T3	6142
invalid_exec_dis	34267920	1			T1	132948		T2	345880		T22	99932