Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43997785	1			T1	71745		T2	285914		T3	3071
triple_byte_access	2446970	1			T1	1456		T2	5749		T5	4005
halfword_access	3668601	1			T1	2137		T2	8499		T5	5920
byte_access	4905374	1			T1	2909		T2	11334		T5	7986
zero_access	1234846	1			T1	723		T2	2795		T5	2032

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28067991

1

T1

39627

T2

157266

T3

1024

auto[1]

28185585

1

T1

39343

T2

157025

T3

2047

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21945155	1			T1	35904		T2	143204		T3	1024
auto[0]	triple_byte_access	1220346	1			T1	730		T2	2860		T5	2032
auto[0]	halfword_access	1830203	1			T1	1132		T2	4181		T5	3034
auto[0]	byte_access	2450336	1			T1	1492		T2	5627		T5	4044
auto[0]	zero_access	621951	1			T1	369		T2	1394		T5	1014
auto[1]	word_access	22052630	1			T1	35841		T2	142710		T3	2047
auto[1]	triple_byte_access	1226624	1			T1	726		T2	2889		T5	1973
auto[1]	halfword_access	1838398	1			T1	1005		T2	4318		T5	2886
auto[1]	byte_access	2455038	1			T1	1417		T2	5707		T5	3942
auto[1]	zero_access	612895	1			T1	354		T2	1401		T5	1018