| T796 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2043764422 |
|
|
Jun 11 01:14:17 PM PDT 24 |
Jun 11 01:15:17 PM PDT 24 |
96804141 ps |
| T797 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1110958837 |
|
|
Jun 11 01:20:30 PM PDT 24 |
Jun 11 01:20:42 PM PDT 24 |
619540284 ps |
| T798 |
/workspace/coverage/default/41.sram_ctrl_executable.1048097034 |
|
|
Jun 11 01:19:57 PM PDT 24 |
Jun 11 01:21:06 PM PDT 24 |
5351298540 ps |
| T799 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.479978000 |
|
|
Jun 11 01:10:54 PM PDT 24 |
Jun 11 01:11:05 PM PDT 24 |
1187731900 ps |
| T800 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.2127276830 |
|
|
Jun 11 01:11:36 PM PDT 24 |
Jun 11 01:11:43 PM PDT 24 |
335602975 ps |
| T801 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1074692874 |
|
|
Jun 11 01:13:30 PM PDT 24 |
Jun 11 01:24:17 PM PDT 24 |
9086399267 ps |
| T802 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2762633945 |
|
|
Jun 11 01:21:32 PM PDT 24 |
Jun 11 01:21:37 PM PDT 24 |
1338797989 ps |
| T803 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.481181218 |
|
|
Jun 11 01:15:15 PM PDT 24 |
Jun 11 01:15:19 PM PDT 24 |
242996966 ps |
| T804 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.573028975 |
|
|
Jun 11 01:10:31 PM PDT 24 |
Jun 11 01:22:39 PM PDT 24 |
5175143045 ps |
| T805 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3073613618 |
|
|
Jun 11 01:21:17 PM PDT 24 |
Jun 11 01:24:51 PM PDT 24 |
8496163146 ps |
| T806 |
/workspace/coverage/default/35.sram_ctrl_smoke.1312934417 |
|
|
Jun 11 01:18:13 PM PDT 24 |
Jun 11 01:18:28 PM PDT 24 |
875505196 ps |
| T807 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.4040815954 |
|
|
Jun 11 01:13:19 PM PDT 24 |
Jun 11 01:19:55 PM PDT 24 |
3812635857 ps |
| T808 |
/workspace/coverage/default/40.sram_ctrl_alert_test.3236201371 |
|
|
Jun 11 01:19:46 PM PDT 24 |
Jun 11 01:19:48 PM PDT 24 |
15393839 ps |
| T809 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3420287731 |
|
|
Jun 11 01:12:07 PM PDT 24 |
Jun 11 01:33:21 PM PDT 24 |
173825687668 ps |
| T810 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1902698314 |
|
|
Jun 11 01:11:14 PM PDT 24 |
Jun 11 01:11:17 PM PDT 24 |
34262437 ps |
| T811 |
/workspace/coverage/default/27.sram_ctrl_partial_access.11269060 |
|
|
Jun 11 01:16:06 PM PDT 24 |
Jun 11 01:16:29 PM PDT 24 |
5318950466 ps |
| T812 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2179581908 |
|
|
Jun 11 01:14:12 PM PDT 24 |
Jun 11 01:17:22 PM PDT 24 |
1909479176 ps |
| T813 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2699959959 |
|
|
Jun 11 01:15:17 PM PDT 24 |
Jun 11 01:15:32 PM PDT 24 |
1445907410 ps |
| T814 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.2192664730 |
|
|
Jun 11 01:14:19 PM PDT 24 |
Jun 11 01:24:52 PM PDT 24 |
30323262239 ps |
| T815 |
/workspace/coverage/default/44.sram_ctrl_stress_all.4282300221 |
|
|
Jun 11 01:20:40 PM PDT 24 |
Jun 11 01:46:26 PM PDT 24 |
12688507084 ps |
| T816 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2094440661 |
|
|
Jun 11 01:21:17 PM PDT 24 |
Jun 11 02:31:58 PM PDT 24 |
40050543817 ps |
| T817 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1154917708 |
|
|
Jun 11 01:16:58 PM PDT 24 |
Jun 11 01:25:31 PM PDT 24 |
5188293128 ps |
| T85 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3952136680 |
|
|
Jun 11 01:10:55 PM PDT 24 |
Jun 11 01:11:03 PM PDT 24 |
653914898 ps |
| T818 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1994100917 |
|
|
Jun 11 01:19:58 PM PDT 24 |
Jun 11 01:20:37 PM PDT 24 |
342485321 ps |
| T819 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.2496217055 |
|
|
Jun 11 01:15:20 PM PDT 24 |
Jun 11 01:15:26 PM PDT 24 |
64566222 ps |
| T820 |
/workspace/coverage/default/19.sram_ctrl_executable.1386621580 |
|
|
Jun 11 01:14:19 PM PDT 24 |
Jun 11 01:38:43 PM PDT 24 |
38412459065 ps |
| T821 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.4127586465 |
|
|
Jun 11 01:12:29 PM PDT 24 |
Jun 11 01:12:33 PM PDT 24 |
106452882 ps |
| T822 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.4279848786 |
|
|
Jun 11 01:17:34 PM PDT 24 |
Jun 11 01:17:43 PM PDT 24 |
741595455 ps |
| T109 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1961513598 |
|
|
Jun 11 01:18:13 PM PDT 24 |
Jun 11 01:19:24 PM PDT 24 |
1213817425 ps |
| T823 |
/workspace/coverage/default/42.sram_ctrl_bijection.1769368300 |
|
|
Jun 11 01:20:11 PM PDT 24 |
Jun 11 01:20:41 PM PDT 24 |
448478078 ps |
| T824 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.4052618598 |
|
|
Jun 11 01:17:32 PM PDT 24 |
Jun 11 01:17:38 PM PDT 24 |
114137681 ps |
| T825 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1069373283 |
|
|
Jun 11 01:20:42 PM PDT 24 |
Jun 11 01:20:43 PM PDT 24 |
48452249 ps |
| T826 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.120935949 |
|
|
Jun 11 01:15:56 PM PDT 24 |
Jun 11 01:16:09 PM PDT 24 |
1620900321 ps |
| T827 |
/workspace/coverage/default/2.sram_ctrl_smoke.3600905690 |
|
|
Jun 11 01:10:32 PM PDT 24 |
Jun 11 01:10:42 PM PDT 24 |
552251717 ps |
| T828 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1758335650 |
|
|
Jun 11 01:10:53 PM PDT 24 |
Jun 11 01:28:19 PM PDT 24 |
44575095494 ps |
| T829 |
/workspace/coverage/default/4.sram_ctrl_regwen.1142335732 |
|
|
Jun 11 01:10:54 PM PDT 24 |
Jun 11 01:22:32 PM PDT 24 |
43617526981 ps |
| T830 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1853272146 |
|
|
Jun 11 01:20:09 PM PDT 24 |
Jun 11 01:20:13 PM PDT 24 |
107303737 ps |
| T831 |
/workspace/coverage/default/32.sram_ctrl_smoke.3939575072 |
|
|
Jun 11 01:17:32 PM PDT 24 |
Jun 11 01:17:49 PM PDT 24 |
145276209 ps |
| T832 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.108842088 |
|
|
Jun 11 01:13:40 PM PDT 24 |
Jun 11 01:13:42 PM PDT 24 |
152683742 ps |
| T833 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.238849301 |
|
|
Jun 11 01:17:21 PM PDT 24 |
Jun 11 01:19:45 PM PDT 24 |
6220040798 ps |
| T834 |
/workspace/coverage/default/21.sram_ctrl_alert_test.34911226 |
|
|
Jun 11 01:14:52 PM PDT 24 |
Jun 11 01:14:53 PM PDT 24 |
31951181 ps |
| T835 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.196408830 |
|
|
Jun 11 01:20:30 PM PDT 24 |
Jun 11 01:25:27 PM PDT 24 |
40660100067 ps |
| T836 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.3264007163 |
|
|
Jun 11 01:13:48 PM PDT 24 |
Jun 11 01:18:09 PM PDT 24 |
7827972748 ps |
| T837 |
/workspace/coverage/default/7.sram_ctrl_executable.85095225 |
|
|
Jun 11 01:11:13 PM PDT 24 |
Jun 11 01:23:15 PM PDT 24 |
4862615003 ps |
| T838 |
/workspace/coverage/default/21.sram_ctrl_executable.1860530665 |
|
|
Jun 11 01:14:50 PM PDT 24 |
Jun 11 01:20:42 PM PDT 24 |
49206635580 ps |
| T839 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3052551137 |
|
|
Jun 11 01:21:04 PM PDT 24 |
Jun 11 01:28:11 PM PDT 24 |
22249706776 ps |
| T840 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.568747222 |
|
|
Jun 11 01:11:26 PM PDT 24 |
Jun 11 01:36:42 PM PDT 24 |
8401660764 ps |
| T841 |
/workspace/coverage/default/24.sram_ctrl_executable.2403432498 |
|
|
Jun 11 01:15:33 PM PDT 24 |
Jun 11 01:32:18 PM PDT 24 |
16589490502 ps |
| T842 |
/workspace/coverage/default/15.sram_ctrl_regwen.1657669272 |
|
|
Jun 11 01:13:06 PM PDT 24 |
Jun 11 01:29:48 PM PDT 24 |
17273477835 ps |
| T843 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.3812959366 |
|
|
Jun 11 01:14:22 PM PDT 24 |
Jun 11 01:14:33 PM PDT 24 |
1831953174 ps |
| T844 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.980254637 |
|
|
Jun 11 01:14:28 PM PDT 24 |
Jun 11 01:15:29 PM PDT 24 |
115445003 ps |
| T845 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2332022398 |
|
|
Jun 11 01:10:21 PM PDT 24 |
Jun 11 01:16:31 PM PDT 24 |
1683899708 ps |
| T846 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1951916777 |
|
|
Jun 11 01:13:09 PM PDT 24 |
Jun 11 01:19:04 PM PDT 24 |
3614409530 ps |
| T847 |
/workspace/coverage/default/20.sram_ctrl_stress_all.3663967628 |
|
|
Jun 11 01:14:39 PM PDT 24 |
Jun 11 02:21:16 PM PDT 24 |
136551685202 ps |
| T848 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3920980088 |
|
|
Jun 11 01:13:29 PM PDT 24 |
Jun 11 01:13:30 PM PDT 24 |
16173908 ps |
| T849 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1679258177 |
|
|
Jun 11 01:20:42 PM PDT 24 |
Jun 11 01:20:49 PM PDT 24 |
158471120 ps |
| T850 |
/workspace/coverage/default/23.sram_ctrl_smoke.2849961030 |
|
|
Jun 11 01:15:16 PM PDT 24 |
Jun 11 01:15:18 PM PDT 24 |
133797374 ps |
| T851 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.20305264 |
|
|
Jun 11 01:20:20 PM PDT 24 |
Jun 11 02:07:12 PM PDT 24 |
21998370318 ps |
| T852 |
/workspace/coverage/default/44.sram_ctrl_bijection.230719205 |
|
|
Jun 11 01:20:29 PM PDT 24 |
Jun 11 01:21:39 PM PDT 24 |
11546131509 ps |
| T853 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3619933202 |
|
|
Jun 11 01:17:32 PM PDT 24 |
Jun 11 01:17:36 PM PDT 24 |
343974550 ps |
| T854 |
/workspace/coverage/default/15.sram_ctrl_stress_all.3702580807 |
|
|
Jun 11 01:13:19 PM PDT 24 |
Jun 11 01:56:56 PM PDT 24 |
60823754637 ps |
| T855 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2247035855 |
|
|
Jun 11 01:13:18 PM PDT 24 |
Jun 11 01:13:22 PM PDT 24 |
98302706 ps |
| T856 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2808982849 |
|
|
Jun 11 01:11:57 PM PDT 24 |
Jun 11 01:12:03 PM PDT 24 |
145751038 ps |
| T857 |
/workspace/coverage/default/23.sram_ctrl_stress_all.3731768918 |
|
|
Jun 11 01:15:24 PM PDT 24 |
Jun 11 01:48:17 PM PDT 24 |
139448298488 ps |
| T858 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3708063797 |
|
|
Jun 11 01:16:17 PM PDT 24 |
Jun 11 01:17:33 PM PDT 24 |
114468756 ps |
| T859 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3471629043 |
|
|
Jun 11 01:11:04 PM PDT 24 |
Jun 11 01:11:06 PM PDT 24 |
146092825 ps |
| T860 |
/workspace/coverage/default/43.sram_ctrl_regwen.4097135962 |
|
|
Jun 11 01:20:21 PM PDT 24 |
Jun 11 01:33:40 PM PDT 24 |
8466447163 ps |
| T861 |
/workspace/coverage/default/40.sram_ctrl_partial_access.3589057830 |
|
|
Jun 11 01:19:47 PM PDT 24 |
Jun 11 01:20:14 PM PDT 24 |
1101338966 ps |
| T862 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.3272791724 |
|
|
Jun 11 01:20:30 PM PDT 24 |
Jun 11 01:21:40 PM PDT 24 |
114009791 ps |
| T863 |
/workspace/coverage/default/15.sram_ctrl_alert_test.4129948957 |
|
|
Jun 11 01:13:17 PM PDT 24 |
Jun 11 01:13:19 PM PDT 24 |
39247532 ps |
| T864 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3530128003 |
|
|
Jun 11 01:18:55 PM PDT 24 |
Jun 11 01:19:23 PM PDT 24 |
100787475 ps |
| T865 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3292579666 |
|
|
Jun 11 01:16:46 PM PDT 24 |
Jun 11 01:18:25 PM PDT 24 |
1031159009 ps |
| T866 |
/workspace/coverage/default/22.sram_ctrl_regwen.1642581807 |
|
|
Jun 11 01:15:04 PM PDT 24 |
Jun 11 01:37:29 PM PDT 24 |
8128962194 ps |
| T867 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.2273177632 |
|
|
Jun 11 01:17:34 PM PDT 24 |
Jun 11 01:17:59 PM PDT 24 |
339525575 ps |
| T868 |
/workspace/coverage/default/14.sram_ctrl_partial_access.2853365299 |
|
|
Jun 11 01:12:55 PM PDT 24 |
Jun 11 01:13:02 PM PDT 24 |
301232411 ps |
| T869 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.970165079 |
|
|
Jun 11 01:15:20 PM PDT 24 |
Jun 11 01:15:44 PM PDT 24 |
366574881 ps |
| T870 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2246345387 |
|
|
Jun 11 01:20:31 PM PDT 24 |
Jun 11 01:20:36 PM PDT 24 |
241745225 ps |
| T871 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2268224967 |
|
|
Jun 11 01:14:30 PM PDT 24 |
Jun 11 01:14:34 PM PDT 24 |
301037486 ps |
| T872 |
/workspace/coverage/default/15.sram_ctrl_smoke.1075657646 |
|
|
Jun 11 01:13:11 PM PDT 24 |
Jun 11 01:15:34 PM PDT 24 |
654488127 ps |
| T873 |
/workspace/coverage/default/49.sram_ctrl_smoke.2184493339 |
|
|
Jun 11 01:21:46 PM PDT 24 |
Jun 11 01:22:22 PM PDT 24 |
411631885 ps |
| T874 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2873737712 |
|
|
Jun 11 01:10:54 PM PDT 24 |
Jun 11 01:17:05 PM PDT 24 |
16222025682 ps |
| T875 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.400670642 |
|
|
Jun 11 01:10:43 PM PDT 24 |
Jun 11 01:20:15 PM PDT 24 |
1872250060 ps |
| T876 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2427849356 |
|
|
Jun 11 01:11:13 PM PDT 24 |
Jun 11 01:11:20 PM PDT 24 |
393195951 ps |
| T877 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.1606527055 |
|
|
Jun 11 01:18:24 PM PDT 24 |
Jun 11 01:18:26 PM PDT 24 |
28321255 ps |
| T878 |
/workspace/coverage/default/33.sram_ctrl_executable.1641747520 |
|
|
Jun 11 01:17:53 PM PDT 24 |
Jun 11 01:38:35 PM PDT 24 |
2976578338 ps |
| T879 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1981821397 |
|
|
Jun 11 01:21:29 PM PDT 24 |
Jun 11 03:36:26 PM PDT 24 |
76435785296 ps |
| T880 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.2563352891 |
|
|
Jun 11 01:20:40 PM PDT 24 |
Jun 11 01:20:49 PM PDT 24 |
141518078 ps |
| T881 |
/workspace/coverage/default/43.sram_ctrl_alert_test.397448548 |
|
|
Jun 11 01:20:32 PM PDT 24 |
Jun 11 01:20:33 PM PDT 24 |
19585338 ps |
| T882 |
/workspace/coverage/default/35.sram_ctrl_bijection.2351973210 |
|
|
Jun 11 01:18:15 PM PDT 24 |
Jun 11 01:18:55 PM PDT 24 |
2683041851 ps |
| T883 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1856976028 |
|
|
Jun 11 01:21:43 PM PDT 24 |
Jun 11 01:22:00 PM PDT 24 |
97160592 ps |
| T884 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2278725790 |
|
|
Jun 11 01:20:41 PM PDT 24 |
Jun 11 01:23:54 PM PDT 24 |
5560730663 ps |
| T885 |
/workspace/coverage/default/16.sram_ctrl_executable.3641322922 |
|
|
Jun 11 01:13:28 PM PDT 24 |
Jun 11 01:29:16 PM PDT 24 |
12161961598 ps |
| T886 |
/workspace/coverage/default/5.sram_ctrl_alert_test.3252638446 |
|
|
Jun 11 01:11:05 PM PDT 24 |
Jun 11 01:11:07 PM PDT 24 |
65863765 ps |
| T887 |
/workspace/coverage/default/7.sram_ctrl_alert_test.1368031477 |
|
|
Jun 11 01:11:26 PM PDT 24 |
Jun 11 01:11:27 PM PDT 24 |
16565613 ps |
| T888 |
/workspace/coverage/default/46.sram_ctrl_executable.574851219 |
|
|
Jun 11 01:21:16 PM PDT 24 |
Jun 11 01:33:25 PM PDT 24 |
9562743664 ps |
| T889 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3964599390 |
|
|
Jun 11 01:13:49 PM PDT 24 |
Jun 11 01:13:51 PM PDT 24 |
24391327 ps |
| T890 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1131602485 |
|
|
Jun 11 01:15:03 PM PDT 24 |
Jun 11 01:19:47 PM PDT 24 |
1022942226 ps |
| T891 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.696350919 |
|
|
Jun 11 01:17:54 PM PDT 24 |
Jun 11 01:18:05 PM PDT 24 |
683606297 ps |
| T892 |
/workspace/coverage/default/21.sram_ctrl_smoke.3666303815 |
|
|
Jun 11 01:14:38 PM PDT 24 |
Jun 11 01:15:19 PM PDT 24 |
613473110 ps |
| T893 |
/workspace/coverage/default/24.sram_ctrl_bijection.2552544617 |
|
|
Jun 11 01:15:24 PM PDT 24 |
Jun 11 01:15:56 PM PDT 24 |
3412665037 ps |
| T894 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1633472615 |
|
|
Jun 11 01:16:06 PM PDT 24 |
Jun 11 01:18:31 PM PDT 24 |
611614741 ps |
| T895 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1561463923 |
|
|
Jun 11 01:17:25 PM PDT 24 |
Jun 11 01:17:28 PM PDT 24 |
1052757514 ps |
| T896 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2312255053 |
|
|
Jun 11 01:18:34 PM PDT 24 |
Jun 11 01:42:35 PM PDT 24 |
49622537975 ps |
| T897 |
/workspace/coverage/default/25.sram_ctrl_regwen.2592709071 |
|
|
Jun 11 01:15:56 PM PDT 24 |
Jun 11 01:28:00 PM PDT 24 |
6004581720 ps |
| T898 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.4292017955 |
|
|
Jun 11 01:14:11 PM PDT 24 |
Jun 11 01:14:15 PM PDT 24 |
48680268 ps |
| T899 |
/workspace/coverage/default/46.sram_ctrl_partial_access.2015918425 |
|
|
Jun 11 01:21:04 PM PDT 24 |
Jun 11 01:23:10 PM PDT 24 |
3226846714 ps |
| T900 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.118543177 |
|
|
Jun 11 01:14:49 PM PDT 24 |
Jun 11 01:15:00 PM PDT 24 |
235746541 ps |
| T901 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3315992796 |
|
|
Jun 11 01:14:19 PM PDT 24 |
Jun 11 01:21:19 PM PDT 24 |
3133994465 ps |
| T902 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3361324313 |
|
|
Jun 11 01:18:53 PM PDT 24 |
Jun 11 01:18:57 PM PDT 24 |
200407885 ps |
| T903 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.352402162 |
|
|
Jun 11 01:15:57 PM PDT 24 |
Jun 11 01:16:05 PM PDT 24 |
195763117 ps |
| T904 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1872904998 |
|
|
Jun 11 01:20:08 PM PDT 24 |
Jun 11 01:20:17 PM PDT 24 |
2222238924 ps |
| T905 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3392419364 |
|
|
Jun 11 01:13:59 PM PDT 24 |
Jun 11 01:14:06 PM PDT 24 |
594403232 ps |
| T906 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.1106305509 |
|
|
Jun 11 01:16:28 PM PDT 24 |
Jun 11 01:16:30 PM PDT 24 |
149592662 ps |
| T907 |
/workspace/coverage/default/22.sram_ctrl_stress_all.584930567 |
|
|
Jun 11 01:15:17 PM PDT 24 |
Jun 11 01:25:58 PM PDT 24 |
5097869966 ps |
| T908 |
/workspace/coverage/default/11.sram_ctrl_executable.1109877806 |
|
|
Jun 11 01:12:07 PM PDT 24 |
Jun 11 01:16:44 PM PDT 24 |
9470871966 ps |
| T909 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2560803661 |
|
|
Jun 11 01:10:55 PM PDT 24 |
Jun 11 01:13:15 PM PDT 24 |
323204705 ps |
| T910 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1511354742 |
|
|
Jun 11 01:13:08 PM PDT 24 |
Jun 11 01:13:11 PM PDT 24 |
2177435606 ps |
| T911 |
/workspace/coverage/default/22.sram_ctrl_partial_access.3986082227 |
|
|
Jun 11 01:15:04 PM PDT 24 |
Jun 11 01:15:17 PM PDT 24 |
1355247034 ps |
| T912 |
/workspace/coverage/default/14.sram_ctrl_stress_all.194495785 |
|
|
Jun 11 01:13:07 PM PDT 24 |
Jun 11 01:44:45 PM PDT 24 |
34632956391 ps |
| T913 |
/workspace/coverage/default/20.sram_ctrl_smoke.3125895342 |
|
|
Jun 11 01:14:19 PM PDT 24 |
Jun 11 01:14:39 PM PDT 24 |
3483722835 ps |
| T110 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2585253147 |
|
|
Jun 11 01:18:23 PM PDT 24 |
Jun 11 01:21:09 PM PDT 24 |
9924791874 ps |
| T914 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1278510868 |
|
|
Jun 11 01:15:24 PM PDT 24 |
Jun 11 01:32:51 PM PDT 24 |
59471583040 ps |
| T915 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.1873835487 |
|
|
Jun 11 01:19:26 PM PDT 24 |
Jun 11 01:19:28 PM PDT 24 |
48665904 ps |
| T916 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.2934177528 |
|
|
Jun 11 01:18:12 PM PDT 24 |
Jun 11 01:18:27 PM PDT 24 |
621714828 ps |
| T917 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3638372829 |
|
|
Jun 11 01:21:31 PM PDT 24 |
Jun 11 01:22:30 PM PDT 24 |
143901844 ps |
| T918 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3262881590 |
|
|
Jun 11 01:10:56 PM PDT 24 |
Jun 11 01:15:59 PM PDT 24 |
11481172663 ps |
| T919 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3685129592 |
|
|
Jun 11 01:10:19 PM PDT 24 |
Jun 11 01:10:22 PM PDT 24 |
25815285 ps |
| T920 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3928756228 |
|
|
Jun 11 01:10:29 PM PDT 24 |
Jun 11 01:36:54 PM PDT 24 |
12019012445 ps |
| T921 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2530617634 |
|
|
Jun 11 01:11:46 PM PDT 24 |
Jun 11 01:11:54 PM PDT 24 |
1602030374 ps |
| T922 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.480998946 |
|
|
Jun 11 01:11:45 PM PDT 24 |
Jun 11 01:11:53 PM PDT 24 |
2585569018 ps |
| T923 |
/workspace/coverage/default/21.sram_ctrl_partial_access.4228498663 |
|
|
Jun 11 01:14:49 PM PDT 24 |
Jun 11 01:16:49 PM PDT 24 |
1278901324 ps |
| T924 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.3109564106 |
|
|
Jun 11 01:15:24 PM PDT 24 |
Jun 11 01:15:30 PM PDT 24 |
285603554 ps |
| T925 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1138649659 |
|
|
Jun 11 01:18:14 PM PDT 24 |
Jun 11 01:22:21 PM PDT 24 |
5107342622 ps |
| T926 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.447030910 |
|
|
Jun 11 01:19:11 PM PDT 24 |
Jun 11 01:19:21 PM PDT 24 |
2387280830 ps |
| T927 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1228657050 |
|
|
Jun 11 01:16:45 PM PDT 24 |
Jun 11 01:21:41 PM PDT 24 |
3030907876 ps |
| T52 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1530862943 |
|
|
Jun 11 01:07:19 PM PDT 24 |
Jun 11 01:07:21 PM PDT 24 |
605120632 ps |
| T49 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.952669335 |
|
|
Jun 11 01:06:36 PM PDT 24 |
Jun 11 01:06:39 PM PDT 24 |
689763433 ps |
| T53 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.703068611 |
|
|
Jun 11 01:06:39 PM PDT 24 |
Jun 11 01:06:40 PM PDT 24 |
34680274 ps |
| T928 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2942283367 |
|
|
Jun 11 01:07:25 PM PDT 24 |
Jun 11 01:07:28 PM PDT 24 |
124862061 ps |
| T929 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2215504897 |
|
|
Jun 11 01:07:24 PM PDT 24 |
Jun 11 01:07:28 PM PDT 24 |
73440352 ps |
| T65 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2615024372 |
|
|
Jun 11 01:06:50 PM PDT 24 |
Jun 11 01:06:51 PM PDT 24 |
15991656 ps |
| T134 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2261731433 |
|
|
Jun 11 01:06:41 PM PDT 24 |
Jun 11 01:06:44 PM PDT 24 |
235666248 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2303231276 |
|
|
Jun 11 01:06:37 PM PDT 24 |
Jun 11 01:06:41 PM PDT 24 |
544919216 ps |
| T930 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2786456767 |
|
|
Jun 11 01:06:47 PM PDT 24 |
Jun 11 01:06:52 PM PDT 24 |
147120786 ps |
| T931 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.95606083 |
|
|
Jun 11 01:07:18 PM PDT 24 |
Jun 11 01:07:21 PM PDT 24 |
173249063 ps |
| T50 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1227478388 |
|
|
Jun 11 01:06:48 PM PDT 24 |
Jun 11 01:06:50 PM PDT 24 |
137954039 ps |
| T67 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3490201912 |
|
|
Jun 11 01:07:40 PM PDT 24 |
Jun 11 01:07:41 PM PDT 24 |
77980779 ps |
| T68 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3925200621 |
|
|
Jun 11 01:07:28 PM PDT 24 |
Jun 11 01:07:32 PM PDT 24 |
403678179 ps |
| T932 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.779003449 |
|
|
Jun 11 01:07:33 PM PDT 24 |
Jun 11 01:07:38 PM PDT 24 |
232795078 ps |
| T933 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1547557691 |
|
|
Jun 11 01:06:48 PM PDT 24 |
Jun 11 01:06:50 PM PDT 24 |
154287143 ps |
| T69 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2972235719 |
|
|
Jun 11 01:07:38 PM PDT 24 |
Jun 11 01:07:39 PM PDT 24 |
18930933 ps |
| T93 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4103474303 |
|
|
Jun 11 01:07:55 PM PDT 24 |
Jun 11 01:07:57 PM PDT 24 |
54847455 ps |
| T70 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3614756816 |
|
|
Jun 11 01:07:35 PM PDT 24 |
Jun 11 01:07:37 PM PDT 24 |
405371769 ps |
| T51 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4273635821 |
|
|
Jun 11 01:07:46 PM PDT 24 |
Jun 11 01:07:49 PM PDT 24 |
181915462 ps |
| T71 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4022066791 |
|
|
Jun 11 01:06:37 PM PDT 24 |
Jun 11 01:06:39 PM PDT 24 |
40586835 ps |
| T94 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.56591778 |
|
|
Jun 11 01:07:28 PM PDT 24 |
Jun 11 01:07:30 PM PDT 24 |
20837445 ps |
| T95 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2483495646 |
|
|
Jun 11 01:07:07 PM PDT 24 |
Jun 11 01:07:08 PM PDT 24 |
20586940 ps |
| T126 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3150464785 |
|
|
Jun 11 01:07:24 PM PDT 24 |
Jun 11 01:07:27 PM PDT 24 |
189416361 ps |
| T934 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.870684609 |
|
|
Jun 11 01:07:27 PM PDT 24 |
Jun 11 01:07:30 PM PDT 24 |
80349752 ps |
| T935 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2651215178 |
|
|
Jun 11 01:07:17 PM PDT 24 |
Jun 11 01:07:18 PM PDT 24 |
21787654 ps |
| T936 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1868013748 |
|
|
Jun 11 01:06:40 PM PDT 24 |
Jun 11 01:06:43 PM PDT 24 |
875715318 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.126512945 |
|
|
Jun 11 01:06:58 PM PDT 24 |
Jun 11 01:06:59 PM PDT 24 |
22400588 ps |
| T73 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.402568905 |
|
|
Jun 11 01:07:17 PM PDT 24 |
Jun 11 01:07:21 PM PDT 24 |
550598628 ps |
| T937 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1641910139 |
|
|
Jun 11 01:06:26 PM PDT 24 |
Jun 11 01:06:30 PM PDT 24 |
186558369 ps |
| T938 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2564920465 |
|
|
Jun 11 01:06:56 PM PDT 24 |
Jun 11 01:07:00 PM PDT 24 |
156320242 ps |
| T74 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3873643157 |
|
|
Jun 11 01:07:07 PM PDT 24 |
Jun 11 01:07:11 PM PDT 24 |
440898888 ps |
| T939 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3287981541 |
|
|
Jun 11 01:07:06 PM PDT 24 |
Jun 11 01:07:11 PM PDT 24 |
256459590 ps |
| T940 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3010053111 |
|
|
Jun 11 01:07:45 PM PDT 24 |
Jun 11 01:07:47 PM PDT 24 |
32275360 ps |
| T75 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3916204499 |
|
|
Jun 11 01:06:15 PM PDT 24 |
Jun 11 01:06:20 PM PDT 24 |
1601061125 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1199781384 |
|
|
Jun 11 01:07:06 PM PDT 24 |
Jun 11 01:07:11 PM PDT 24 |
146668205 ps |
| T76 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2548921410 |
|
|
Jun 11 01:07:09 PM PDT 24 |
Jun 11 01:07:12 PM PDT 24 |
244663354 ps |
| T942 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.847081740 |
|
|
Jun 11 01:07:46 PM PDT 24 |
Jun 11 01:07:48 PM PDT 24 |
15673853 ps |
| T121 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2717891614 |
|
|
Jun 11 01:07:28 PM PDT 24 |
Jun 11 01:07:31 PM PDT 24 |
175105839 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3998872342 |
|
|
Jun 11 01:06:39 PM PDT 24 |
Jun 11 01:06:42 PM PDT 24 |
168289117 ps |
| T944 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3793649627 |
|
|
Jun 11 01:07:57 PM PDT 24 |
Jun 11 01:08:02 PM PDT 24 |
217433737 ps |
| T945 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3801135209 |
|
|
Jun 11 01:07:17 PM PDT 24 |
Jun 11 01:07:19 PM PDT 24 |
46593758 ps |
| T946 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2627373549 |
|
|
Jun 11 01:07:55 PM PDT 24 |
Jun 11 01:07:57 PM PDT 24 |
30902149 ps |
| T130 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3274682097 |
|
|
Jun 11 01:06:40 PM PDT 24 |
Jun 11 01:06:43 PM PDT 24 |
120369084 ps |
| T947 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1251106241 |
|
|
Jun 11 01:06:37 PM PDT 24 |
Jun 11 01:06:38 PM PDT 24 |
12535999 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1985461221 |
|
|
Jun 11 01:07:45 PM PDT 24 |
Jun 11 01:07:47 PM PDT 24 |
24517135 ps |
| T949 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2398102746 |
|
|
Jun 11 01:07:46 PM PDT 24 |
Jun 11 01:07:48 PM PDT 24 |
22261911 ps |
| T77 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1522617645 |
|
|
Jun 11 01:07:26 PM PDT 24 |
Jun 11 01:07:30 PM PDT 24 |
381057894 ps |
| T950 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2503409615 |
|
|
Jun 11 01:06:36 PM PDT 24 |
Jun 11 01:06:41 PM PDT 24 |
206203476 ps |
| T951 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2793087639 |
|
|
Jun 11 01:06:58 PM PDT 24 |
Jun 11 01:06:59 PM PDT 24 |
72941116 ps |
| T952 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.427424386 |
|
|
Jun 11 01:07:57 PM PDT 24 |
Jun 11 01:07:58 PM PDT 24 |
110433364 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.221926812 |
|
|
Jun 11 01:07:54 PM PDT 24 |
Jun 11 01:07:59 PM PDT 24 |
50323487 ps |
| T954 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.215310740 |
|
|
Jun 11 01:07:27 PM PDT 24 |
Jun 11 01:07:30 PM PDT 24 |
110328347 ps |
| T955 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1440534509 |
|
|
Jun 11 01:07:25 PM PDT 24 |
Jun 11 01:07:27 PM PDT 24 |
35481531 ps |
| T956 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.393295780 |
|
|
Jun 11 01:07:46 PM PDT 24 |
Jun 11 01:07:51 PM PDT 24 |
37179839 ps |
| T131 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1965230286 |
|
|
Jun 11 01:07:18 PM PDT 24 |
Jun 11 01:07:20 PM PDT 24 |
366637312 ps |
| T957 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1785666406 |
|
|
Jun 11 01:06:56 PM PDT 24 |
Jun 11 01:06:58 PM PDT 24 |
94611186 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1916646189 |
|
|
Jun 11 01:06:48 PM PDT 24 |
Jun 11 01:06:50 PM PDT 24 |
222300242 ps |
| T959 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1068246689 |
|
|
Jun 11 01:07:26 PM PDT 24 |
Jun 11 01:07:29 PM PDT 24 |
30837967 ps |
| T960 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4168107228 |
|
|
Jun 11 01:07:26 PM PDT 24 |
Jun 11 01:07:29 PM PDT 24 |
24210730 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1914944577 |
|
|
Jun 11 01:06:38 PM PDT 24 |
Jun 11 01:06:42 PM PDT 24 |
58088391 ps |
| T122 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.596008591 |
|
|
Jun 11 01:07:24 PM PDT 24 |
Jun 11 01:07:27 PM PDT 24 |
108292782 ps |
| T132 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1425672002 |
|
|
Jun 11 01:07:19 PM PDT 24 |
Jun 11 01:07:21 PM PDT 24 |
96939728 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2866448230 |
|
|
Jun 11 01:06:37 PM PDT 24 |
Jun 11 01:06:39 PM PDT 24 |
15564245 ps |
| T133 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.866454976 |
|
|
Jun 11 01:07:06 PM PDT 24 |
Jun 11 01:07:09 PM PDT 24 |
1078558789 ps |
| T963 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2277935414 |
|
|
Jun 11 01:06:39 PM PDT 24 |
Jun 11 01:06:42 PM PDT 24 |
178154568 ps |
| T86 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.965296297 |
|
|
Jun 11 01:07:45 PM PDT 24 |
Jun 11 01:07:50 PM PDT 24 |
769416117 ps |
| T87 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1230541747 |
|
|
Jun 11 01:06:47 PM PDT 24 |
Jun 11 01:06:51 PM PDT 24 |
643645569 ps |
| T88 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3556927414 |
|
|
Jun 11 01:06:14 PM PDT 24 |
Jun 11 01:06:16 PM PDT 24 |
22528404 ps |
| T964 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3001122972 |
|
|
Jun 11 01:06:57 PM PDT 24 |
Jun 11 01:06:59 PM PDT 24 |
23402175 ps |
| T123 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3626324325 |
|
|
Jun 11 01:07:25 PM PDT 24 |
Jun 11 01:07:28 PM PDT 24 |
188064157 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.38652767 |
|
|
Jun 11 01:06:37 PM PDT 24 |
Jun 11 01:06:40 PM PDT 24 |
352254642 ps |
| T124 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1107103092 |
|
|
Jun 11 01:07:58 PM PDT 24 |
Jun 11 01:08:01 PM PDT 24 |
311109187 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1818740544 |
|
|
Jun 11 01:07:17 PM PDT 24 |
Jun 11 01:07:19 PM PDT 24 |
20642593 ps |
| T967 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.828553195 |
|
|
Jun 11 01:07:18 PM PDT 24 |
Jun 11 01:07:23 PM PDT 24 |
362396558 ps |
| T89 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1632372209 |
|
|
Jun 11 01:07:07 PM PDT 24 |
Jun 11 01:07:08 PM PDT 24 |
52674713 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2431125948 |
|
|
Jun 11 01:06:26 PM PDT 24 |
Jun 11 01:06:27 PM PDT 24 |
19264734 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1503119098 |
|
|
Jun 11 01:07:47 PM PDT 24 |
Jun 11 01:07:49 PM PDT 24 |
35356059 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3386193901 |
|
|
Jun 11 01:06:39 PM PDT 24 |
Jun 11 01:06:41 PM PDT 24 |
117126340 ps |
| T971 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.479369772 |
|
|
Jun 11 01:07:27 PM PDT 24 |
Jun 11 01:07:29 PM PDT 24 |
43790502 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2609473118 |
|
|
Jun 11 01:07:58 PM PDT 24 |
Jun 11 01:08:00 PM PDT 24 |
14165178 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4000454267 |
|
|
Jun 11 01:06:38 PM PDT 24 |
Jun 11 01:06:41 PM PDT 24 |
1383289916 ps |
| T973 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3269242034 |
|
|
Jun 11 01:07:24 PM PDT 24 |
Jun 11 01:07:27 PM PDT 24 |
177364222 ps |
| T974 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.708849646 |
|
|
Jun 11 01:07:26 PM PDT 24 |
Jun 11 01:07:29 PM PDT 24 |
122355792 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.737765838 |
|
|
Jun 11 01:07:54 PM PDT 24 |
Jun 11 01:07:58 PM PDT 24 |
310113789 ps |
| T91 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3664641848 |
|
|
Jun 11 01:06:47 PM PDT 24 |
Jun 11 01:06:50 PM PDT 24 |
304397990 ps |
| T976 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1619687493 |
|
|
Jun 11 01:07:07 PM PDT 24 |
Jun 11 01:07:10 PM PDT 24 |
799493911 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3435261995 |
|
|
Jun 11 01:06:15 PM PDT 24 |
Jun 11 01:06:20 PM PDT 24 |
437806737 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.268769842 |
|
|
Jun 11 01:07:16 PM PDT 24 |
Jun 11 01:07:18 PM PDT 24 |
36625126 ps |
| T979 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1531968207 |
|
|
Jun 11 01:07:28 PM PDT 24 |
Jun 11 01:07:31 PM PDT 24 |
18994646 ps |
| T980 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3804498899 |
|
|
Jun 11 01:07:25 PM PDT 24 |
Jun 11 01:07:27 PM PDT 24 |
11640393 ps |
| T981 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1727306615 |
|
|
Jun 11 01:07:26 PM PDT 24 |
Jun 11 01:07:28 PM PDT 24 |
19074526 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2233860737 |
|
|
Jun 11 01:06:28 PM PDT 24 |
Jun 11 01:06:29 PM PDT 24 |
34116550 ps |
| T92 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.403849815 |
|
|
Jun 11 01:07:54 PM PDT 24 |
Jun 11 01:07:56 PM PDT 24 |
234278503 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1261262167 |
|
|
Jun 11 01:06:48 PM PDT 24 |
Jun 11 01:06:49 PM PDT 24 |
26674140 ps |
| T984 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1027626577 |
|
|
Jun 11 01:07:25 PM PDT 24 |
Jun 11 01:07:31 PM PDT 24 |
85602269 ps |
| T127 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2384490249 |
|
|
Jun 11 01:07:57 PM PDT 24 |
Jun 11 01:08:02 PM PDT 24 |
405918346 ps |
| T985 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.963558 |
|
|
Jun 11 01:07:40 PM PDT 24 |
Jun 11 01:07:44 PM PDT 24 |
1574504723 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3988037147 |
|
|
Jun 11 01:06:56 PM PDT 24 |
Jun 11 01:06:59 PM PDT 24 |
530954534 ps |
| T987 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3964978720 |
|
|
Jun 11 01:07:28 PM PDT 24 |
Jun 11 01:07:33 PM PDT 24 |
2045271756 ps |
| T988 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3233947309 |
|
|
Jun 11 01:06:56 PM PDT 24 |
Jun 11 01:06:58 PM PDT 24 |
106107608 ps |
| T989 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3790018516 |
|
|
Jun 11 01:07:46 PM PDT 24 |
Jun 11 01:07:48 PM PDT 24 |
60399163 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.692500295 |
|
|
Jun 11 01:07:46 PM PDT 24 |
Jun 11 01:07:49 PM PDT 24 |
847663068 ps |
| T991 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2048509411 |
|
|
Jun 11 01:07:34 PM PDT 24 |
Jun 11 01:07:36 PM PDT 24 |
117593246 ps |
| T992 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3787113267 |
|
|
Jun 11 01:07:47 PM PDT 24 |
Jun 11 01:07:51 PM PDT 24 |
277604017 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4275012029 |
|
|
Jun 11 01:06:40 PM PDT 24 |
Jun 11 01:06:42 PM PDT 24 |
74039441 ps |
| T994 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1493755154 |
|
|
Jun 11 01:06:57 PM PDT 24 |
Jun 11 01:06:59 PM PDT 24 |
137811696 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1374400622 |
|
|
Jun 11 01:06:50 PM PDT 24 |
Jun 11 01:06:51 PM PDT 24 |
88501111 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3718996479 |
|
|
Jun 11 01:06:48 PM PDT 24 |
Jun 11 01:06:49 PM PDT 24 |
11220359 ps |
| T997 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1007406592 |
|
|
Jun 11 01:07:56 PM PDT 24 |
Jun 11 01:07:58 PM PDT 24 |
16388775 ps |
| T998 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3413600750 |
|
|
Jun 11 01:07:58 PM PDT 24 |
Jun 11 01:08:04 PM PDT 24 |
753303554 ps |
| T999 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1182053132 |
|
|
Jun 11 01:07:07 PM PDT 24 |
Jun 11 01:07:09 PM PDT 24 |
154272486 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.618443966 |
|
|
Jun 11 01:06:45 PM PDT 24 |
Jun 11 01:06:47 PM PDT 24 |
57107363 ps |
| T125 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.117163669 |
|
|
Jun 11 01:07:40 PM PDT 24 |
Jun 11 01:07:42 PM PDT 24 |
328149575 ps |
| T128 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2899330722 |
|
|
Jun 11 01:06:56 PM PDT 24 |
Jun 11 01:07:00 PM PDT 24 |
683245076 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1192979056 |
|
|
Jun 11 01:06:56 PM PDT 24 |
Jun 11 01:06:58 PM PDT 24 |
369126742 ps |