Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13953983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59402608

1

T1

150196

T2

3214

T3

140

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36568332	1			T1	82398		T2	1789		T3	349
values[0x0]	16995329	1			T1	39933		T2	804		T3	132
values[0x1]	19792930	1			T1	42861		T2	919		T3	255

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6953912	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66402679

1

T1

157686

T2

3354

T3

433

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	271787	1			T1	627		T2	14		T8	3
valid_sources[0x01]	286823	1			T1	651		T2	12		T8	6
valid_sources[0x02]	288271	1			T1	624		T2	20		T8	3
valid_sources[0x03]	367975	1			T1	726		T2	13		T8	6
valid_sources[0x04]	273099	1			T1	556		T2	14		T8	2
valid_sources[0x05]	262100	1			T1	640		T2	14		T8	2
valid_sources[0x06]	340220	1			T1	811		T2	19		T5	91
valid_sources[0x07]	287285	1			T1	630		T2	16		T8	4
valid_sources[0x08]	294715	1			T1	809		T2	19		T8	6
valid_sources[0x09]	283471	1			T1	633		T2	16		T8	7
valid_sources[0x0a]	267959	1			T1	659		T2	22		T8	3
valid_sources[0x0b]	263258	1			T1	615		T2	14		T5	101
valid_sources[0x0c]	330548	1			T1	599		T2	13		T3	736
valid_sources[0x0d]	291931	1			T1	637		T2	13		T8	4
valid_sources[0x0e]	286751	1			T1	650		T2	14		T8	4
valid_sources[0x0f]	315639	1			T1	643		T2	8		T8	4
valid_sources[0x10]	270517	1			T1	757		T2	12		T5	64
valid_sources[0x11]	259386	1			T1	676		T2	14		T8	3
valid_sources[0x12]	329954	1			T1	585		T2	15		T8	6
valid_sources[0x13]	279495	1			T1	621		T2	11		T8	6
valid_sources[0x14]	253472	1			T1	644		T2	17		T8	3
valid_sources[0x15]	279694	1			T1	679		T2	12		T8	1
valid_sources[0x16]	304153	1			T1	565		T2	13		T8	3
valid_sources[0x17]	291432	1			T1	549		T2	9		T8	6
valid_sources[0x18]	366578	1			T1	638		T2	18		T8	2
valid_sources[0x19]	266963	1			T1	609		T2	16		T8	5
valid_sources[0x1a]	285535	1			T1	581		T2	12		T8	7
valid_sources[0x1b]	267485	1			T1	607		T2	3		T8	7
valid_sources[0x1c]	356742	1			T1	693		T2	19		T8	4
valid_sources[0x1d]	264490	1			T1	719		T2	12		T8	5
valid_sources[0x1e]	273868	1			T1	633		T2	11		T8	2
valid_sources[0x1f]	285251	1			T1	682		T2	13		T8	3
valid_sources[0x20]	271351	1			T1	534		T2	21		T8	3
valid_sources[0x21]	302580	1			T1	710		T2	12		T8	6
valid_sources[0x22]	277679	1			T1	662		T2	16		T8	4
valid_sources[0x23]	271359	1			T1	568		T2	21		T8	3
valid_sources[0x24]	296833	1			T1	667		T2	9		T8	5
valid_sources[0x25]	296493	1			T1	633		T2	17		T8	3
valid_sources[0x26]	350334	1			T1	739		T2	19		T8	4
valid_sources[0x27]	317843	1			T1	634		T2	21		T8	3
valid_sources[0x28]	271455	1			T1	529		T2	17		T8	2
valid_sources[0x29]	252070	1			T1	662		T2	9		T8	1
valid_sources[0x2a]	285995	1			T1	771		T2	16		T8	6
valid_sources[0x2b]	258455	1			T1	606		T2	11		T8	2
valid_sources[0x2c]	283820	1			T1	710		T2	13		T8	2
valid_sources[0x2d]	296603	1			T1	618		T2	11		T8	7
valid_sources[0x2e]	297449	1			T1	710		T2	13		T8	3
valid_sources[0x2f]	298634	1			T1	661		T2	15		T8	2
valid_sources[0x30]	278444	1			T1	627		T2	10		T8	3
valid_sources[0x31]	255095	1			T1	722		T2	7		T8	6
valid_sources[0x32]	267185	1			T1	651		T2	14		T8	1
valid_sources[0x33]	320267	1			T1	667		T2	9		T8	8
valid_sources[0x34]	302106	1			T1	611		T2	12		T8	4
valid_sources[0x35]	265751	1			T1	646		T2	11		T8	3
valid_sources[0x36]	277850	1			T1	654		T2	20		T8	5
valid_sources[0x37]	284261	1			T1	629		T2	15		T8	5
valid_sources[0x38]	310150	1			T1	642		T2	9		T8	4
valid_sources[0x39]	268803	1			T1	663		T2	16		T8	1
valid_sources[0x3a]	260409	1			T1	662		T2	10		T8	3
valid_sources[0x3b]	258139	1			T1	606		T2	20		T8	2
valid_sources[0x3c]	311311	1			T1	672		T2	9		T8	3
valid_sources[0x3d]	286508	1			T1	586		T2	14		T8	3
valid_sources[0x3e]	322117	1			T1	741		T2	19		T8	4
valid_sources[0x3f]	328265	1			T1	687		T2	16		T8	3
valid_sources[0x40]	253839	1			T1	646		T2	21		T8	7
valid_sources[0x41]	276265	1			T1	581		T2	25		T8	2
valid_sources[0x42]	258903	1			T1	617		T2	13		T8	5
valid_sources[0x43]	287885	1			T1	681		T2	13		T8	2
valid_sources[0x44]	335567	1			T1	772		T2	16		T8	6
valid_sources[0x45]	289099	1			T1	625		T2	15		T5	78
valid_sources[0x46]	278415	1			T1	664		T2	13		T8	5
valid_sources[0x47]	293190	1			T1	608		T2	15		T8	4
valid_sources[0x48]	252949	1			T1	719		T2	11		T8	2
valid_sources[0x49]	265645	1			T1	546		T2	9		T8	3
valid_sources[0x4a]	268698	1			T1	709		T2	11		T8	3
valid_sources[0x4b]	302004	1			T1	619		T2	7		T8	4
valid_sources[0x4c]	282601	1			T1	667		T2	16		T8	3
valid_sources[0x4d]	261768	1			T1	614		T2	17		T8	4
valid_sources[0x4e]	262615	1			T1	709		T2	16		T8	6
valid_sources[0x4f]	272778	1			T1	710		T2	13		T8	6
valid_sources[0x50]	294301	1			T1	744		T2	17		T8	3
valid_sources[0x51]	261728	1			T1	647		T2	11		T8	6
valid_sources[0x52]	312106	1			T1	564		T2	16		T8	8
valid_sources[0x53]	261236	1			T1	660		T2	17		T8	1
valid_sources[0x54]	291748	1			T1	611		T2	15		T8	8
valid_sources[0x55]	304915	1			T1	588		T2	11		T8	2
valid_sources[0x56]	263017	1			T1	610		T2	8		T8	4
valid_sources[0x57]	273234	1			T1	654		T2	8		T8	1
valid_sources[0x58]	271997	1			T1	650		T2	21		T8	3
valid_sources[0x59]	321002	1			T1	643		T2	10		T8	1
valid_sources[0x5a]	279606	1			T1	621		T2	6		T8	8
valid_sources[0x5b]	281185	1			T1	630		T2	18		T8	7
valid_sources[0x5c]	276366	1			T1	572		T2	19		T8	1
valid_sources[0x5d]	280308	1			T1	723		T2	11		T8	6
valid_sources[0x5e]	259259	1			T1	646		T2	16		T8	5
valid_sources[0x5f]	328507	1			T1	591		T2	7		T8	6
valid_sources[0x60]	256796	1			T1	562		T2	23		T8	7
valid_sources[0x61]	254362	1			T1	689		T2	4		T5	77
valid_sources[0x62]	267377	1			T1	669		T2	14		T8	1
valid_sources[0x63]	309713	1			T1	576		T2	26		T8	4
valid_sources[0x64]	272278	1			T1	687		T2	12		T8	3
valid_sources[0x65]	294651	1			T1	608		T2	11		T8	3
valid_sources[0x66]	272322	1			T1	716		T2	10		T8	3
valid_sources[0x67]	270807	1			T1	638		T2	14		T8	3
valid_sources[0x68]	357793	1			T1	615		T2	10		T8	3
valid_sources[0x69]	314379	1			T1	528		T2	9		T8	3
valid_sources[0x6a]	296370	1			T1	670		T2	10		T8	4
valid_sources[0x6b]	261495	1			T1	600		T2	19		T8	4
valid_sources[0x6c]	285443	1			T1	580		T2	9		T8	5
valid_sources[0x6d]	284119	1			T1	614		T2	7		T8	5
valid_sources[0x6e]	291196	1			T1	651		T2	18		T8	3
valid_sources[0x6f]	268789	1			T1	678		T2	6		T8	2
valid_sources[0x70]	271892	1			T1	649		T2	15		T8	6
valid_sources[0x71]	296892	1			T1	589		T2	19		T8	6
valid_sources[0x72]	275399	1			T1	643		T2	8		T8	2
valid_sources[0x73]	268122	1			T1	696		T2	9		T8	4
valid_sources[0x74]	256727	1			T1	652		T2	9		T8	4
valid_sources[0x75]	270577	1			T1	686		T2	16		T8	3
valid_sources[0x76]	306311	1			T1	662		T2	8		T8	3
valid_sources[0x77]	279188	1			T1	703		T2	16		T8	8
valid_sources[0x78]	295137	1			T1	645		T2	14		T8	2
valid_sources[0x79]	315316	1			T1	642		T2	6		T8	2
valid_sources[0x7a]	313358	1			T1	645		T2	17		T8	4
valid_sources[0x7b]	268915	1			T1	551		T2	16		T5	109
valid_sources[0x7c]	273030	1			T1	632		T2	16		T8	2
valid_sources[0x7d]	263456	1			T1	675		T2	22		T5	41
valid_sources[0x7e]	272684	1			T1	702		T2	18		T8	6
valid_sources[0x7f]	284146	1			T1	673		T2	14		T8	5
valid_sources[0x80]	262044	1			T1	623		T2	14		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29598440

1

T1

74907

T2

1631

T3

64

values[0x0]

all_enables

biggest_size

14900984

1

T1

37750

T2

765

T3

35

values[0x1]

all_enables

biggest_size

14903184

1

T1

37539

T2

818

T3

41

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

134657

1

T1

6

T2

18

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49867	1			T2	31		T6	29		T23	600
values[0x0]	58444	1			T1	13		T2	18		T4	6
values[0x1]	63360	1			T1	10		T2	13		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28029	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143642

1

T1

7

T2

22

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	491	1			T23	6		T47	1		T26	20
valid_sources[0x01]	696	1			T26	31		T27	4		T59	1
valid_sources[0x02]	518	1			T3	1		T28	1		T47	2
valid_sources[0x03]	671	1			T26	18		T27	11		T59	16
valid_sources[0x04]	685	1			T26	39		T27	24		T59	2
valid_sources[0x05]	622	1			T3	1		T6	2		T7	1
valid_sources[0x06]	535	1			T44	1		T7	1		T47	3
valid_sources[0x07]	625	1			T23	2		T7	2		T65	1
valid_sources[0x08]	723	1			T47	1		T65	1		T26	15
valid_sources[0x09]	538	1			T23	1		T47	1		T71	1
valid_sources[0x0a]	766	1			T23	3		T24	2		T26	27
valid_sources[0x0b]	890	1			T1	1		T7	3		T47	2
valid_sources[0x0c]	651	1			T11	1		T23	8		T7	1
valid_sources[0x0d]	655	1			T23	175		T47	3		T26	13
valid_sources[0x0e]	643	1			T47	1		T26	33		T27	25
valid_sources[0x0f]	593	1			T1	1		T6	2		T47	1
valid_sources[0x10]	705	1			T24	1		T47	1		T71	1
valid_sources[0x11]	608	1			T44	2		T76	2		T71	4
valid_sources[0x12]	689	1			T6	1		T23	141		T28	1
valid_sources[0x13]	769	1			T52	2		T7	1		T26	29
valid_sources[0x14]	614	1			T26	16		T27	20		T59	8
valid_sources[0x15]	576	1			T7	4		T21	32		T170	1
valid_sources[0x16]	970	1			T11	1		T23	100		T7	1
valid_sources[0x17]	586	1			T52	2		T26	30		T27	25
valid_sources[0x18]	775	1			T1	2		T7	1		T26	25
valid_sources[0x19]	591	1			T24	1		T47	1		T71	2
valid_sources[0x1a]	599	1			T44	1		T47	3		T26	13
valid_sources[0x1b]	832	1			T70	31		T47	1		T26	31
valid_sources[0x1c]	570	1			T7	5		T26	29		T27	28
valid_sources[0x1d]	743	1			T23	3		T47	1		T21	5
valid_sources[0x1e]	614	1			T1	1		T23	1		T44	1
valid_sources[0x1f]	677	1			T6	5		T7	1		T47	3
valid_sources[0x20]	572	1			T6	1		T12	1		T26	22
valid_sources[0x21]	597	1			T7	2		T47	1		T26	45
valid_sources[0x22]	678	1			T43	6		T65	3		T26	10
valid_sources[0x23]	734	1			T10	1		T7	2		T24	1
valid_sources[0x24]	564	1			T171	1		T26	37		T27	8
valid_sources[0x25]	516	1			T26	36		T27	10		T59	8
valid_sources[0x26]	581	1			T23	4		T26	36		T27	18
valid_sources[0x27]	949	1			T47	1		T65	7		T172	1
valid_sources[0x28]	765	1			T47	1		T65	2		T26	21
valid_sources[0x29]	758	1			T23	118		T44	1		T7	1
valid_sources[0x2a]	753	1			T7	3		T26	37		T27	5
valid_sources[0x2b]	657	1			T26	25		T27	15		T59	43
valid_sources[0x2c]	709	1			T11	1		T44	1		T26	29
valid_sources[0x2d]	686	1			T170	3		T26	13		T27	34
valid_sources[0x2e]	715	1			T23	1		T26	25		T27	8
valid_sources[0x2f]	544	1			T23	1		T7	2		T47	4
valid_sources[0x30]	583	1			T14	1		T26	22		T27	13
valid_sources[0x31]	537	1			T7	2		T47	2		T26	21
valid_sources[0x32]	1473	1			T6	6		T23	1		T28	5
valid_sources[0x33]	542	1			T26	38		T27	14		T59	1
valid_sources[0x34]	657	1			T1	1		T6	1		T23	4
valid_sources[0x35]	531	1			T7	1		T47	2		T26	25
valid_sources[0x36]	835	1			T5	6		T7	2		T28	2
valid_sources[0x37]	719	1			T1	1		T6	2		T23	1
valid_sources[0x38]	587	1			T11	1		T7	2		T24	1
valid_sources[0x39]	885	1			T23	123		T47	3		T26	20
valid_sources[0x3a]	620	1			T23	1		T7	2		T47	1
valid_sources[0x3b]	557	1			T11	1		T23	5		T47	1
valid_sources[0x3c]	578	1			T26	22		T27	18		T59	7
valid_sources[0x3d]	692	1			T11	1		T7	2		T47	1
valid_sources[0x3e]	723	1			T11	1		T7	1		T24	1
valid_sources[0x3f]	625	1			T26	21		T27	42		T59	42
valid_sources[0x40]	850	1			T14	1		T26	30		T27	37
valid_sources[0x41]	760	1			T26	24		T27	12		T59	6
valid_sources[0x42]	542	1			T6	3		T47	3		T26	39
valid_sources[0x43]	768	1			T6	7		T47	1		T65	2
valid_sources[0x44]	640	1			T23	3		T7	2		T47	1
valid_sources[0x45]	633	1			T7	2		T24	1		T47	3
valid_sources[0x46]	652	1			T23	1		T28	3		T47	1
valid_sources[0x47]	726	1			T23	2		T7	1		T170	3
valid_sources[0x48]	972	1			T47	2		T65	5		T26	39
valid_sources[0x49]	762	1			T23	24		T47	1		T26	29
valid_sources[0x4a]	559	1			T24	1		T47	1		T21	11
valid_sources[0x4b]	825	1			T1	1		T26	24		T59	20
valid_sources[0x4c]	502	1			T172	1		T26	23		T27	12
valid_sources[0x4d]	655	1			T7	1		T13	2		T170	3
valid_sources[0x4e]	691	1			T47	1		T26	13		T27	24
valid_sources[0x4f]	663	1			T23	32		T12	3		T71	3
valid_sources[0x50]	615	1			T24	3		T12	1		T26	23
valid_sources[0x51]	685	1			T1	1		T65	1		T172	1
valid_sources[0x52]	644	1			T1	3		T7	2		T26	23
valid_sources[0x53]	584	1			T65	2		T161	1		T26	15
valid_sources[0x54]	643	1			T24	1		T12	1		T47	1
valid_sources[0x55]	616	1			T47	1		T26	10		T27	41
valid_sources[0x56]	700	1			T23	54		T47	2		T172	2
valid_sources[0x57]	563	1			T23	3		T170	1		T26	35
valid_sources[0x58]	557	1			T23	1		T7	2		T26	41
valid_sources[0x59]	679	1			T23	63		T71	2		T26	23
valid_sources[0x5a]	572	1			T44	1		T47	2		T26	36
valid_sources[0x5b]	660	1			T26	24		T27	4		T59	60
valid_sources[0x5c]	601	1			T28	3		T24	2		T47	2
valid_sources[0x5d]	518	1			T65	1		T26	23		T27	5
valid_sources[0x5e]	589	1			T1	1		T11	1		T23	2
valid_sources[0x5f]	649	1			T4	2		T23	19		T24	1
valid_sources[0x60]	588	1			T23	3		T26	19		T27	11
valid_sources[0x61]	773	1			T7	1		T47	4		T172	1
valid_sources[0x62]	622	1			T26	32		T27	6		T59	2
valid_sources[0x63]	669	1			T23	1		T161	3		T26	26
valid_sources[0x64]	621	1			T7	3		T65	2		T26	43
valid_sources[0x65]	596	1			T7	1		T26	26		T27	34
valid_sources[0x66]	611	1			T23	2		T7	1		T71	1
valid_sources[0x67]	640	1			T23	21		T24	1		T47	2
valid_sources[0x68]	578	1			T26	27		T27	10		T59	19
valid_sources[0x69]	775	1			T26	12		T27	14		T59	75
valid_sources[0x6a]	519	1			T28	1		T47	1		T26	25
valid_sources[0x6b]	674	1			T47	1		T65	5		T26	25
valid_sources[0x6c]	694	1			T47	1		T26	22		T27	39
valid_sources[0x6d]	780	1			T28	2		T26	22		T27	3
valid_sources[0x6e]	718	1			T23	1		T47	1		T13	2
valid_sources[0x6f]	711	1			T47	1		T21	2		T26	25
valid_sources[0x70]	712	1			T6	6		T23	1		T26	39
valid_sources[0x71]	732	1			T1	3		T11	1		T23	1
valid_sources[0x72]	547	1			T6	1		T24	1		T47	5
valid_sources[0x73]	724	1			T23	64		T26	29		T27	11
valid_sources[0x74]	730	1			T23	3		T52	1		T7	1
valid_sources[0x75]	578	1			T52	1		T13	5		T173	1
valid_sources[0x76]	539	1			T1	3		T28	1		T47	1
valid_sources[0x77]	655	1			T44	1		T7	1		T24	1
valid_sources[0x78]	600	1			T7	1		T47	2		T65	6
valid_sources[0x79]	544	1			T23	19		T7	1		T24	1
valid_sources[0x7a]	592	1			T6	5		T7	1		T13	3
valid_sources[0x7b]	758	1			T44	1		T7	1		T26	30
valid_sources[0x7c]	1030	1			T4	6		T11	1		T44	1
valid_sources[0x7d]	944	1			T11	1		T71	1		T26	46
valid_sources[0x7e]	706	1			T9	1		T7	1		T47	1
valid_sources[0x7f]	587	1			T65	2		T161	6		T26	22
valid_sources[0x80]	666	1			T7	1		T47	3		T26	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36549

1

T2

12

T6

19

T23

532

values[0x0]

all_enables

biggest_size

49796

1

T1

5

T2

5

T4

2

values[0x1]

all_enables

biggest_size

48312

1

T1

1

T2

1

T8

1