Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13663892

1

T1

14996

T2

85

T3

596

full_word

54659649

1

T1

150196

T2

1022

T3

140

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68323221	1			T1	165192		T2	1107		T3	736
auto[TlIntgErrCmd]	96	1			T62	2		T63	4		T64	4
auto[TlIntgErrData]	112	1			T62	4		T63	3		T64	4
auto[TlIntgErrBoth]	112	1			T62	4		T63	3		T64	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31474002

1

T1

82398

T2

552

T3

349

auto[1]

36849539

1

T1

82794

T2

555

T3

387

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6541170	1			T1	7491		T2	41		T3	285
auto[TlIntgErrNone]	partial	auto[1]	7122429	1			T1	7505		T2	44		T3	311
auto[TlIntgErrNone]	full_word	auto[0]	24932671	1			T1	74907		T2	511		T3	64
auto[TlIntgErrNone]	full_word	auto[1]	29726951	1			T1	75289		T2	511		T3	76
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T62	1		T63	2		T64	3
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T63	2		T146	3		T150	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T152	1		T153	1		T154	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T62	1		T64	1		T147	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T62	1		T63	1		T64	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T62	3		T63	2		T146	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T64	2		T147	1		T148	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T148	2		T155	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T62	2		T63	1		T64	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T62	2		T63	1		T64	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T63	1		T147	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T157	2		T158	1		T159	1