Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	770202	1			T5	17		T6	1		T42	16480
auto[1]	10404211	1			T1	31472		T2	478		T5	2
auto[2]	635734	1			T5	11		T6	1		T42	14298
auto[3]	10282827	1			T1	31730		T2	494		T5	4

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14683192	1			T1	52784		T2	849		T5	29
auto[1]	2071159	1			T1	4964		T2	54		T5	2
auto[2]	2089286	1			T1	4965		T2	62		T5	2
auto[3]	3249337	1			T1	489		T2	7		T5	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9129567

1

T1

63136

T2

968

T5

34

auto[1]

12963407

1

T1

66

T2

4

T11

120

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	309242	1			T5	16		T6	1		T24	1648
auto[0]	auto[0]	auto[1]	31477	1			T5	1		T24	173		T70	1
auto[0]	auto[0]	auto[2]	31315	1			T24	172		T47	1492		T65	4
auto[0]	auto[0]	auto[3]	6111	1			T24	10		T47	154		T21	6
auto[0]	auto[1]	auto[0]	3457907	1			T1	26267		T2	420		T11	49793
auto[0]	auto[1]	auto[1]	361332	1			T1	2336		T2	21		T5	1
auto[0]	auto[1]	auto[2]	348512	1			T1	2593		T2	34		T11	5084
auto[0]	auto[1]	auto[3]	68477	1			T1	243		T2	1		T5	1
auto[0]	auto[2]	auto[0]	262401	1			T5	11		T24	1428		T70	10
auto[0]	auto[2]	auto[1]	26575	1			T24	164		T47	1408		T71	69
auto[0]	auto[2]	auto[2]	29934	1			T6	1		T24	108		T47	1027
auto[0]	auto[2]	auto[3]	5685	1			T24	10		T47	94		T65	7
auto[0]	auto[3]	auto[0]	3414668	1			T1	26460		T2	425		T5	2
auto[0]	auto[3]	auto[1]	345852	1			T1	2625		T2	33		T11	5101
auto[0]	auto[3]	auto[2]	359930	1			T1	2366		T2	28		T5	2
auto[0]	auto[3]	auto[3]	70149	1			T1	246		T2	6		T11	485
auto[1]	auto[0]	auto[0]	13322	1			T42	527		T47	13		T167	23
auto[1]	auto[0]	auto[1]	58248	1			T42	2390		T47	3		T167	1
auto[1]	auto[0]	auto[2]	58144	1			T42	2499		T47	3		T167	3
auto[1]	auto[0]	auto[3]	262343	1			T42	11064		T167	1		T115	2629
auto[1]	auto[1]	auto[0]	3609226	1			T1	31		T2	2		T11	39
auto[1]	auto[1]	auto[1]	628057	1			T1	1		T11	6		T44	7
auto[1]	auto[1]	auto[2]	596184	1			T1	1		T11	4		T42	392
auto[1]	auto[1]	auto[3]	1334516	1			T11	1		T44	1		T42	11090
auto[1]	auto[2]	auto[0]	9083	1			T42	509		T24	2		T47	16
auto[1]	auto[2]	auto[1]	40543	1			T42	2288		T24	1		T47	3
auto[1]	auto[2]	auto[2]	47428	1			T42	2110		T47	1		T167	1
auto[1]	auto[2]	auto[3]	214085	1			T42	9391		T115	2332		T168	1
auto[1]	auto[3]	auto[0]	3607343	1			T1	26		T2	2		T11	61
auto[1]	auto[3]	auto[1]	579075	1			T1	2		T11	2		T44	2
auto[1]	auto[3]	auto[2]	617839	1			T1	5		T11	7		T44	4
auto[1]	auto[3]	auto[3]	1287971	1			T42	9477		T45	1		T7	1