Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	334664986	197780	0	0
ctrl_regwen_rd_A	334664986	4262	0	0
exec_rd_A	334664986	3898	0	0
exec_regwen_rd_A	334664986	4468	0	0
readback_rd_A	334664986	3063	0	0
readback_regwen_rd_A	334664986	2743	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334664986	197780	0	0
T23	47147	3603	0	0
T25	1982	0	0	0
T26	0	9833	0	0
T27	0	6228	0	0
T30	2294	0	0	0
T42	984211	0	0	0
T44	262691	0	0	0
T45	415619	0	0	0
T52	44132	0	0	0
T54	0	3908	0	0
T59	0	9708	0	0
T61	0	1969	0	0
T72	0	7855	0	0
T73	0	2624	0	0
T74	0	738	0	0
T75	0	6284	0	0
T76	6900	0	0	0
T77	1770	0	0	0
T78	2113	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334664986	4262	0	0
T50	0	208	0	0
T74	22666	119	0	0
T75	108384	0	0	0
T128	0	140	0	0
T129	0	64	0	0
T130	0	215	0	0
T131	0	168	0	0
T132	0	521	0	0
T133	0	117	0	0
T134	0	241	0	0
T135	0	407	0	0
T136	1056	0	0	0
T137	72701	0	0	0
T138	3100	0	0	0
T139	20816	0	0	0
T140	92126	0	0	0
T141	13359	0	0	0
T142	86849	0	0	0
T143	560946	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334664986	3898	0	0
T50	0	193	0	0
T74	22666	69	0	0
T75	108384	0	0	0
T128	0	137	0	0
T129	0	59	0	0
T130	0	194	0	0
T131	0	213	0	0
T132	0	400	0	0
T133	0	107	0	0
T134	0	220	0	0
T135	0	424	0	0
T136	1056	0	0	0
T137	72701	0	0	0
T138	3100	0	0	0
T139	20816	0	0	0
T140	92126	0	0	0
T141	13359	0	0	0
T142	86849	0	0	0
T143	560946	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334664986	4468	0	0
T50	0	151	0	0
T74	22666	114	0	0
T75	108384	0	0	0
T128	0	185	0	0
T129	0	42	0	0
T130	0	149	0	0
T131	0	188	0	0
T132	0	473	0	0
T133	0	112	0	0
T134	0	288	0	0
T135	0	541	0	0
T136	1056	0	0	0
T137	72701	0	0	0
T138	3100	0	0	0
T139	20816	0	0	0
T140	92126	0	0	0
T141	13359	0	0	0
T142	86849	0	0	0
T143	560946	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334664986	3063	0	0
T50	0	194	0	0
T74	22666	48	0	0
T75	108384	0	0	0
T128	0	88	0	0
T129	0	32	0	0
T130	0	152	0	0
T131	0	214	0	0
T132	0	463	0	0
T133	0	106	0	0
T134	0	271	0	0
T135	0	495	0	0
T136	1056	0	0	0
T137	72701	0	0	0
T138	3100	0	0	0
T139	20816	0	0	0
T140	92126	0	0	0
T141	13359	0	0	0
T142	86849	0	0	0
T143	560946	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334664986	2743	0	0
T50	0	206	0	0
T74	22666	42	0	0
T75	108384	0	0	0
T128	0	176	0	0
T129	0	32	0	0
T130	0	83	0	0
T131	0	71	0	0
T132	0	505	0	0
T133	0	81	0	0
T134	0	194	0	0
T135	0	467	0	0
T136	1056	0	0	0
T137	72701	0	0	0
T138	3100	0	0	0
T139	20816	0	0	0
T140	92126	0	0	0
T141	13359	0	0	0
T142	86849	0	0	0
T143	560946	0	0	0