Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	136467442	1			T1	508278		T2	330882		T3	6650
instr_valid_dis	108057578	1			T1	508278		T2	330882		T3	6650
instr_en	20917044	1			T9	301186		T10	240306		T20	48

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9973750	1			T9	55470		T20	74268		T24	11120
sram_ifetch_valid_disable	107147441	1			T1	508278		T2	330882		T3	6650
sram_ifetch_enable	19346251	1			T9	308024		T10	109456		T20	14802

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	136467442	1			T1	508278		T2	330882		T3	6650
hw_debug_en_valid_off	107673843	1			T1	508278		T2	330882		T3	6650
hw_debug_en_on	19332197	1			T9	170458		T10	108768		T20	62296

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	107147441	1			T1	508278		T2	330882		T3	6650
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	94909261	1			T1	508278		T2	330882		T3	6650
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8706889	1			T9	95976		T10	166590		T20	48
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3584240	1			T9	14872		T20	74268		T132	67360
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1412682	1			T132	30620		T133	20000		T135	20634
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1534108	1			T9	14872		T132	36740		T134	23350
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3937658	1			T9	40598		T24	11120		T133	66
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1772272	1			T9	36018		T141	102676		T142	19438
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1764054	1			T9	4580		T24	11120		T133	66
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7417050	1			T9	82524		T10	97980		T20	47494
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3017136	1			T23	13684		T21	14384		T26	21916
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3330594	1			T9	82524		T10	97980		T132	42274

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8211185	1			T9	185758		T10	73716		T24	172800
lc_exec_en	7977489	1			T9	47336		T10	10788		T20	14802
valid_exec_dis	104536690	1			T1	508278		T2	330882		T3	6650
invalid_exec_dis	29320001	1			T9	363494		T10	109456		T20	89070