Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	40509561	1			T1	46533		T2	150392		T3	3001
triple_byte_access	2448848	1			T1	41558		T2	3031		T3	71
halfword_access	3673682	1			T1	62375		T2	4437		T3	104
byte_access	4904712	1			T1	82678		T2	6053		T3	121
zero_access	1234457	1			T1	20995		T2	1528		T3	28

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26331728

1

T1

126916

T2

82501

T3

1641

auto[1]

26439532

1

T1

127223

T2

82940

T3

1684

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	20205226	1			T1	23364		T2	75024		T3	1479
auto[0]	triple_byte_access	1221452	1			T1	20707		T2	1498		T3	32
auto[0]	halfword_access	1832733	1			T1	31067		T2	2206		T3	51
auto[0]	byte_access	2451254	1			T1	41319		T2	3016		T3	63
auto[0]	zero_access	621063	1			T1	10459		T2	757		T3	16
auto[1]	word_access	20304335	1			T1	23169		T2	75368		T3	1522
auto[1]	triple_byte_access	1227396	1			T1	20851		T2	1533		T3	39
auto[1]	halfword_access	1840949	1			T1	31308		T2	2231		T3	53
auto[1]	byte_access	2453458	1			T1	41359		T2	3037		T3	58
auto[1]	zero_access	613394	1			T1	10536		T2	771		T3	12