| T796 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.101001231 |
|
|
Jun 21 04:52:20 PM PDT 24 |
Jun 21 04:52:22 PM PDT 24 |
26621552 ps |
| T797 |
/workspace/coverage/default/6.sram_ctrl_stress_all.2875892796 |
|
|
Jun 21 04:50:04 PM PDT 24 |
Jun 21 05:17:56 PM PDT 24 |
102923957451 ps |
| T798 |
/workspace/coverage/default/21.sram_ctrl_executable.2386773898 |
|
|
Jun 21 04:50:49 PM PDT 24 |
Jun 21 05:10:41 PM PDT 24 |
148431691992 ps |
| T799 |
/workspace/coverage/default/6.sram_ctrl_bijection.782724268 |
|
|
Jun 21 04:50:07 PM PDT 24 |
Jun 21 04:50:48 PM PDT 24 |
2469606990 ps |
| T800 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3280407356 |
|
|
Jun 21 04:52:41 PM PDT 24 |
Jun 21 05:01:26 PM PDT 24 |
1639089791 ps |
| T801 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1532851653 |
|
|
Jun 21 04:52:48 PM PDT 24 |
Jun 21 04:52:52 PM PDT 24 |
15624541 ps |
| T802 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.2138903225 |
|
|
Jun 21 04:51:39 PM PDT 24 |
Jun 21 04:51:41 PM PDT 24 |
29079988 ps |
| T803 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1277724261 |
|
|
Jun 21 04:50:12 PM PDT 24 |
Jun 21 04:55:58 PM PDT 24 |
37963134064 ps |
| T804 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2863573419 |
|
|
Jun 21 04:52:45 PM PDT 24 |
Jun 21 04:53:02 PM PDT 24 |
3204468511 ps |
| T805 |
/workspace/coverage/default/6.sram_ctrl_partial_access.498531715 |
|
|
Jun 21 04:50:08 PM PDT 24 |
Jun 21 04:50:11 PM PDT 24 |
108354703 ps |
| T806 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2098739625 |
|
|
Jun 21 04:50:02 PM PDT 24 |
Jun 21 05:08:45 PM PDT 24 |
110442850588 ps |
| T807 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1643032565 |
|
|
Jun 21 04:51:00 PM PDT 24 |
Jun 21 04:51:09 PM PDT 24 |
497932661 ps |
| T30 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.2561984270 |
|
|
Jun 21 04:50:02 PM PDT 24 |
Jun 21 04:50:06 PM PDT 24 |
499347742 ps |
| T808 |
/workspace/coverage/default/7.sram_ctrl_stress_all.622873402 |
|
|
Jun 21 04:50:10 PM PDT 24 |
Jun 21 05:13:42 PM PDT 24 |
38751784184 ps |
| T809 |
/workspace/coverage/default/11.sram_ctrl_bijection.2907946939 |
|
|
Jun 21 04:50:22 PM PDT 24 |
Jun 21 04:51:21 PM PDT 24 |
3467561586 ps |
| T810 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.871089114 |
|
|
Jun 21 04:49:59 PM PDT 24 |
Jun 21 04:57:03 PM PDT 24 |
2447594874 ps |
| T811 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.514777562 |
|
|
Jun 21 04:51:22 PM PDT 24 |
Jun 21 05:04:23 PM PDT 24 |
12660962838 ps |
| T812 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3091459318 |
|
|
Jun 21 04:52:55 PM PDT 24 |
Jun 21 04:52:57 PM PDT 24 |
31534827 ps |
| T813 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3184391173 |
|
|
Jun 21 04:50:58 PM PDT 24 |
Jun 21 04:57:06 PM PDT 24 |
1032805616 ps |
| T814 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.585033615 |
|
|
Jun 21 04:50:33 PM PDT 24 |
Jun 21 05:02:16 PM PDT 24 |
21183040465 ps |
| T815 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1468320629 |
|
|
Jun 21 04:50:50 PM PDT 24 |
Jun 21 04:51:46 PM PDT 24 |
3562241836 ps |
| T816 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1249476228 |
|
|
Jun 21 04:51:29 PM PDT 24 |
Jun 21 05:38:27 PM PDT 24 |
31317472887 ps |
| T817 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1474598417 |
|
|
Jun 21 04:52:13 PM PDT 24 |
Jun 21 04:53:24 PM PDT 24 |
301950990 ps |
| T818 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2601328825 |
|
|
Jun 21 04:51:33 PM PDT 24 |
Jun 21 04:51:44 PM PDT 24 |
2203353557 ps |
| T819 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1396012476 |
|
|
Jun 21 04:52:21 PM PDT 24 |
Jun 21 04:57:33 PM PDT 24 |
13562004677 ps |
| T820 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.1346667414 |
|
|
Jun 21 04:50:30 PM PDT 24 |
Jun 21 04:50:36 PM PDT 24 |
1328803299 ps |
| T821 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3914774589 |
|
|
Jun 21 04:50:19 PM PDT 24 |
Jun 21 05:06:58 PM PDT 24 |
51658060421 ps |
| T822 |
/workspace/coverage/default/19.sram_ctrl_executable.2225068440 |
|
|
Jun 21 04:50:33 PM PDT 24 |
Jun 21 05:01:20 PM PDT 24 |
11480901836 ps |
| T823 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3794237452 |
|
|
Jun 21 04:50:18 PM PDT 24 |
Jun 21 04:50:23 PM PDT 24 |
423241406 ps |
| T824 |
/workspace/coverage/default/7.sram_ctrl_bijection.1510648720 |
|
|
Jun 21 04:50:09 PM PDT 24 |
Jun 21 04:50:39 PM PDT 24 |
1285382445 ps |
| T825 |
/workspace/coverage/default/39.sram_ctrl_bijection.2892134507 |
|
|
Jun 21 04:52:12 PM PDT 24 |
Jun 21 04:52:39 PM PDT 24 |
1386171249 ps |
| T826 |
/workspace/coverage/default/17.sram_ctrl_regwen.489190927 |
|
|
Jun 21 04:50:38 PM PDT 24 |
Jun 21 05:03:58 PM PDT 24 |
2875073255 ps |
| T827 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.120855863 |
|
|
Jun 21 04:51:59 PM PDT 24 |
Jun 21 04:55:06 PM PDT 24 |
2623176926 ps |
| T828 |
/workspace/coverage/default/42.sram_ctrl_alert_test.617218732 |
|
|
Jun 21 04:52:22 PM PDT 24 |
Jun 21 04:52:24 PM PDT 24 |
18325096 ps |
| T829 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3286446491 |
|
|
Jun 21 04:50:53 PM PDT 24 |
Jun 21 04:51:33 PM PDT 24 |
1008947477 ps |
| T830 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.3810133928 |
|
|
Jun 21 04:51:41 PM PDT 24 |
Jun 21 04:51:50 PM PDT 24 |
750896487 ps |
| T831 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1828358159 |
|
|
Jun 21 04:52:26 PM PDT 24 |
Jun 21 04:52:27 PM PDT 24 |
29733645 ps |
| T832 |
/workspace/coverage/default/12.sram_ctrl_regwen.3363804257 |
|
|
Jun 21 04:50:20 PM PDT 24 |
Jun 21 04:57:18 PM PDT 24 |
8520656960 ps |
| T833 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3604131463 |
|
|
Jun 21 04:50:40 PM PDT 24 |
Jun 21 04:59:51 PM PDT 24 |
90174132240 ps |
| T834 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2452105148 |
|
|
Jun 21 04:51:18 PM PDT 24 |
Jun 21 04:53:04 PM PDT 24 |
10122157389 ps |
| T835 |
/workspace/coverage/default/31.sram_ctrl_bijection.760685813 |
|
|
Jun 21 04:51:36 PM PDT 24 |
Jun 21 04:52:25 PM PDT 24 |
34748262901 ps |
| T836 |
/workspace/coverage/default/5.sram_ctrl_alert_test.2964206155 |
|
|
Jun 21 04:50:02 PM PDT 24 |
Jun 21 04:50:04 PM PDT 24 |
77950999 ps |
| T837 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2878072120 |
|
|
Jun 21 04:51:16 PM PDT 24 |
Jun 21 04:51:27 PM PDT 24 |
1221003798 ps |
| T838 |
/workspace/coverage/default/12.sram_ctrl_smoke.3321477053 |
|
|
Jun 21 04:50:18 PM PDT 24 |
Jun 21 04:50:35 PM PDT 24 |
154725462 ps |
| T839 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2523554784 |
|
|
Jun 21 04:51:58 PM PDT 24 |
Jun 21 04:52:15 PM PDT 24 |
287767981 ps |
| T840 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1448423151 |
|
|
Jun 21 04:51:05 PM PDT 24 |
Jun 21 04:51:07 PM PDT 24 |
13421926 ps |
| T841 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3881304210 |
|
|
Jun 21 04:50:22 PM PDT 24 |
Jun 21 04:53:52 PM PDT 24 |
11895885914 ps |
| T842 |
/workspace/coverage/default/7.sram_ctrl_executable.677908361 |
|
|
Jun 21 04:50:09 PM PDT 24 |
Jun 21 05:01:50 PM PDT 24 |
115580318990 ps |
| T843 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1354684558 |
|
|
Jun 21 04:52:40 PM PDT 24 |
Jun 21 04:52:45 PM PDT 24 |
331369119 ps |
| T844 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3226306899 |
|
|
Jun 21 04:50:15 PM PDT 24 |
Jun 21 04:50:16 PM PDT 24 |
48121296 ps |
| T845 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.993530869 |
|
|
Jun 21 04:51:18 PM PDT 24 |
Jun 21 05:07:22 PM PDT 24 |
53603777290 ps |
| T846 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.964859466 |
|
|
Jun 21 04:52:39 PM PDT 24 |
Jun 21 04:54:30 PM PDT 24 |
476831898 ps |
| T847 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.59529169 |
|
|
Jun 21 04:52:20 PM PDT 24 |
Jun 21 04:52:26 PM PDT 24 |
78533528 ps |
| T848 |
/workspace/coverage/default/3.sram_ctrl_bijection.35183083 |
|
|
Jun 21 04:50:03 PM PDT 24 |
Jun 21 04:51:04 PM PDT 24 |
4966372886 ps |
| T849 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.2188941149 |
|
|
Jun 21 04:50:03 PM PDT 24 |
Jun 21 04:54:03 PM PDT 24 |
2484249124 ps |
| T850 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1897558099 |
|
|
Jun 21 04:52:00 PM PDT 24 |
Jun 21 04:59:29 PM PDT 24 |
19613231751 ps |
| T851 |
/workspace/coverage/default/47.sram_ctrl_regwen.2517297760 |
|
|
Jun 21 04:52:50 PM PDT 24 |
Jun 21 05:13:38 PM PDT 24 |
56556996203 ps |
| T852 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2253607792 |
|
|
Jun 21 04:49:54 PM PDT 24 |
Jun 21 04:50:00 PM PDT 24 |
1471663483 ps |
| T853 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.2266296071 |
|
|
Jun 21 04:50:19 PM PDT 24 |
Jun 21 04:51:01 PM PDT 24 |
369802567 ps |
| T854 |
/workspace/coverage/default/9.sram_ctrl_executable.272890729 |
|
|
Jun 21 04:50:18 PM PDT 24 |
Jun 21 04:52:43 PM PDT 24 |
30391510375 ps |
| T855 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2644388951 |
|
|
Jun 21 04:52:34 PM PDT 24 |
Jun 21 04:56:19 PM PDT 24 |
3212581915 ps |
| T856 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.2844836316 |
|
|
Jun 21 04:50:23 PM PDT 24 |
Jun 21 04:51:23 PM PDT 24 |
110331527 ps |
| T857 |
/workspace/coverage/default/25.sram_ctrl_regwen.2147506754 |
|
|
Jun 21 04:51:15 PM PDT 24 |
Jun 21 04:59:38 PM PDT 24 |
2398636477 ps |
| T858 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.146653413 |
|
|
Jun 21 04:51:17 PM PDT 24 |
Jun 21 05:10:14 PM PDT 24 |
60558160755 ps |
| T859 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.352924578 |
|
|
Jun 21 04:50:20 PM PDT 24 |
Jun 21 04:52:10 PM PDT 24 |
594949942 ps |
| T860 |
/workspace/coverage/default/16.sram_ctrl_executable.3138445276 |
|
|
Jun 21 04:50:32 PM PDT 24 |
Jun 21 04:59:51 PM PDT 24 |
29991870594 ps |
| T861 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.64100757 |
|
|
Jun 21 04:50:32 PM PDT 24 |
Jun 21 05:03:44 PM PDT 24 |
13586280722 ps |
| T862 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3446063749 |
|
|
Jun 21 04:52:46 PM PDT 24 |
Jun 21 05:12:30 PM PDT 24 |
57045790742 ps |
| T863 |
/workspace/coverage/default/14.sram_ctrl_stress_all.636048280 |
|
|
Jun 21 04:50:29 PM PDT 24 |
Jun 21 05:10:10 PM PDT 24 |
22723245940 ps |
| T864 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4143716299 |
|
|
Jun 21 04:52:35 PM PDT 24 |
Jun 21 04:53:09 PM PDT 24 |
400494648 ps |
| T865 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.214118215 |
|
|
Jun 21 04:52:45 PM PDT 24 |
Jun 21 04:55:51 PM PDT 24 |
8853196723 ps |
| T866 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1583232461 |
|
|
Jun 21 04:50:34 PM PDT 24 |
Jun 21 05:03:21 PM PDT 24 |
25969620832 ps |
| T867 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2537385500 |
|
|
Jun 21 04:51:41 PM PDT 24 |
Jun 21 04:52:38 PM PDT 24 |
806038922 ps |
| T868 |
/workspace/coverage/default/39.sram_ctrl_executable.2706312737 |
|
|
Jun 21 04:52:10 PM PDT 24 |
Jun 21 04:59:36 PM PDT 24 |
2103635756 ps |
| T869 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.4065509022 |
|
|
Jun 21 04:50:28 PM PDT 24 |
Jun 21 04:50:57 PM PDT 24 |
373441245 ps |
| T870 |
/workspace/coverage/default/14.sram_ctrl_regwen.992648059 |
|
|
Jun 21 04:50:27 PM PDT 24 |
Jun 21 04:54:18 PM PDT 24 |
669412061 ps |
| T871 |
/workspace/coverage/default/24.sram_ctrl_executable.4010254215 |
|
|
Jun 21 04:51:02 PM PDT 24 |
Jun 21 05:19:50 PM PDT 24 |
10437996354 ps |
| T872 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2951014137 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:53:57 PM PDT 24 |
24820826544 ps |
| T873 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.2244311851 |
|
|
Jun 21 04:51:39 PM PDT 24 |
Jun 21 05:05:09 PM PDT 24 |
15613906084 ps |
| T874 |
/workspace/coverage/default/4.sram_ctrl_bijection.1244372109 |
|
|
Jun 21 04:50:02 PM PDT 24 |
Jun 21 04:51:04 PM PDT 24 |
32527138556 ps |
| T875 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.2810420258 |
|
|
Jun 21 04:50:22 PM PDT 24 |
Jun 21 04:50:36 PM PDT 24 |
457518706 ps |
| T876 |
/workspace/coverage/default/43.sram_ctrl_smoke.3171452795 |
|
|
Jun 21 04:52:23 PM PDT 24 |
Jun 21 04:52:35 PM PDT 24 |
2570435546 ps |
| T877 |
/workspace/coverage/default/8.sram_ctrl_smoke.2558906622 |
|
|
Jun 21 04:50:06 PM PDT 24 |
Jun 21 04:50:11 PM PDT 24 |
107336466 ps |
| T878 |
/workspace/coverage/default/27.sram_ctrl_bijection.2078686130 |
|
|
Jun 21 04:51:06 PM PDT 24 |
Jun 21 04:51:49 PM PDT 24 |
5414221148 ps |
| T879 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.1686188369 |
|
|
Jun 21 04:51:45 PM PDT 24 |
Jun 21 04:51:51 PM PDT 24 |
1491952751 ps |
| T31 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1666638471 |
|
|
Jun 21 04:49:44 PM PDT 24 |
Jun 21 04:49:54 PM PDT 24 |
1303675079 ps |
| T880 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.38628647 |
|
|
Jun 21 04:50:06 PM PDT 24 |
Jun 21 04:50:08 PM PDT 24 |
27683345 ps |
| T881 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3633325832 |
|
|
Jun 21 04:51:02 PM PDT 24 |
Jun 21 04:51:10 PM PDT 24 |
733867895 ps |
| T882 |
/workspace/coverage/default/41.sram_ctrl_smoke.191943602 |
|
|
Jun 21 04:52:15 PM PDT 24 |
Jun 21 04:52:30 PM PDT 24 |
3503807022 ps |
| T883 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2630192807 |
|
|
Jun 21 04:49:56 PM PDT 24 |
Jun 21 05:13:21 PM PDT 24 |
4816743990 ps |
| T884 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.476044211 |
|
|
Jun 21 04:52:27 PM PDT 24 |
Jun 21 04:52:30 PM PDT 24 |
40786724 ps |
| T885 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.191124278 |
|
|
Jun 21 04:52:20 PM PDT 24 |
Jun 21 04:54:22 PM PDT 24 |
1324153861 ps |
| T886 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3677997628 |
|
|
Jun 21 04:50:34 PM PDT 24 |
Jun 21 05:13:15 PM PDT 24 |
17658652132 ps |
| T887 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3979653365 |
|
|
Jun 21 04:52:26 PM PDT 24 |
Jun 21 04:56:05 PM PDT 24 |
2793268099 ps |
| T888 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1002183956 |
|
|
Jun 21 04:51:44 PM PDT 24 |
Jun 21 04:59:14 PM PDT 24 |
22247139749 ps |
| T889 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1612853922 |
|
|
Jun 21 04:50:14 PM PDT 24 |
Jun 21 04:50:18 PM PDT 24 |
110332277 ps |
| T890 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1890949954 |
|
|
Jun 21 04:50:57 PM PDT 24 |
Jun 21 04:51:03 PM PDT 24 |
46833554 ps |
| T891 |
/workspace/coverage/default/9.sram_ctrl_smoke.2599643107 |
|
|
Jun 21 04:50:19 PM PDT 24 |
Jun 21 04:50:31 PM PDT 24 |
1236593243 ps |
| T892 |
/workspace/coverage/default/1.sram_ctrl_smoke.3888195608 |
|
|
Jun 21 04:49:34 PM PDT 24 |
Jun 21 04:49:59 PM PDT 24 |
2526304596 ps |
| T893 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.4283317315 |
|
|
Jun 21 04:50:28 PM PDT 24 |
Jun 21 04:50:30 PM PDT 24 |
89468117 ps |
| T894 |
/workspace/coverage/default/19.sram_ctrl_stress_all.391710547 |
|
|
Jun 21 04:50:32 PM PDT 24 |
Jun 21 05:13:38 PM PDT 24 |
63984338359 ps |
| T895 |
/workspace/coverage/default/43.sram_ctrl_regwen.259216296 |
|
|
Jun 21 04:52:19 PM PDT 24 |
Jun 21 04:52:47 PM PDT 24 |
5453355510 ps |
| T896 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2051664430 |
|
|
Jun 21 04:51:59 PM PDT 24 |
Jun 21 04:56:19 PM PDT 24 |
4706824820 ps |
| T897 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1722491917 |
|
|
Jun 21 04:52:57 PM PDT 24 |
Jun 21 04:59:40 PM PDT 24 |
65142692607 ps |
| T898 |
/workspace/coverage/default/36.sram_ctrl_executable.2518426160 |
|
|
Jun 21 04:51:59 PM PDT 24 |
Jun 21 05:20:13 PM PDT 24 |
13776613088 ps |
| T899 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3947842086 |
|
|
Jun 21 04:50:33 PM PDT 24 |
Jun 21 04:50:42 PM PDT 24 |
186462165 ps |
| T900 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1178048389 |
|
|
Jun 21 04:49:36 PM PDT 24 |
Jun 21 04:49:47 PM PDT 24 |
34466160 ps |
| T901 |
/workspace/coverage/default/1.sram_ctrl_regwen.560593644 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 05:09:26 PM PDT 24 |
74218551734 ps |
| T902 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.499260542 |
|
|
Jun 21 04:51:20 PM PDT 24 |
Jun 21 04:51:28 PM PDT 24 |
1394160329 ps |
| T903 |
/workspace/coverage/default/45.sram_ctrl_alert_test.4245570559 |
|
|
Jun 21 04:52:33 PM PDT 24 |
Jun 21 04:52:34 PM PDT 24 |
28572375 ps |
| T904 |
/workspace/coverage/default/22.sram_ctrl_partial_access.2159928686 |
|
|
Jun 21 04:50:49 PM PDT 24 |
Jun 21 04:51:14 PM PDT 24 |
218927949 ps |
| T905 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2514916889 |
|
|
Jun 21 04:51:59 PM PDT 24 |
Jun 21 05:02:23 PM PDT 24 |
46014208607 ps |
| T906 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2556805170 |
|
|
Jun 21 04:52:33 PM PDT 24 |
Jun 21 04:55:23 PM PDT 24 |
1627064923 ps |
| T907 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2928381622 |
|
|
Jun 21 04:51:46 PM PDT 24 |
Jun 21 04:56:47 PM PDT 24 |
1913396527 ps |
| T908 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2668266280 |
|
|
Jun 21 04:52:14 PM PDT 24 |
Jun 21 05:15:30 PM PDT 24 |
7954369233 ps |
| T909 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.742409293 |
|
|
Jun 21 04:52:57 PM PDT 24 |
Jun 21 04:53:50 PM PDT 24 |
226595979 ps |
| T910 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.950019276 |
|
|
Jun 21 04:52:34 PM PDT 24 |
Jun 21 05:13:12 PM PDT 24 |
19366924515 ps |
| T911 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.1192725983 |
|
|
Jun 21 04:51:35 PM PDT 24 |
Jun 21 04:59:05 PM PDT 24 |
5185861296 ps |
| T912 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2215494796 |
|
|
Jun 21 04:51:38 PM PDT 24 |
Jun 21 04:51:49 PM PDT 24 |
680888016 ps |
| T913 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3441434395 |
|
|
Jun 21 04:50:32 PM PDT 24 |
Jun 21 04:55:20 PM PDT 24 |
3037250328 ps |
| T914 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3506665483 |
|
|
Jun 21 04:51:31 PM PDT 24 |
Jun 21 04:55:11 PM PDT 24 |
2913516896 ps |
| T915 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1751167307 |
|
|
Jun 21 04:52:18 PM PDT 24 |
Jun 21 05:15:53 PM PDT 24 |
5675572030 ps |
| T916 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1647945076 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
21329493 ps |
| T917 |
/workspace/coverage/default/22.sram_ctrl_regwen.800600040 |
|
|
Jun 21 04:50:54 PM PDT 24 |
Jun 21 04:56:51 PM PDT 24 |
8495812202 ps |
| T918 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3401257201 |
|
|
Jun 21 04:50:00 PM PDT 24 |
Jun 21 04:50:04 PM PDT 24 |
83502706 ps |
| T919 |
/workspace/coverage/default/0.sram_ctrl_bijection.83922690 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:50:14 PM PDT 24 |
1989535412 ps |
| T920 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.327157377 |
|
|
Jun 21 04:51:15 PM PDT 24 |
Jun 21 04:51:17 PM PDT 24 |
37445684 ps |
| T921 |
/workspace/coverage/default/3.sram_ctrl_smoke.2981936098 |
|
|
Jun 21 04:49:55 PM PDT 24 |
Jun 21 04:50:29 PM PDT 24 |
899254109 ps |
| T922 |
/workspace/coverage/default/32.sram_ctrl_bijection.886708200 |
|
|
Jun 21 04:51:31 PM PDT 24 |
Jun 21 04:52:21 PM PDT 24 |
2658737540 ps |
| T923 |
/workspace/coverage/default/27.sram_ctrl_partial_access.329715538 |
|
|
Jun 21 04:51:18 PM PDT 24 |
Jun 21 04:51:43 PM PDT 24 |
179229226 ps |
| T924 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.522346978 |
|
|
Jun 21 04:51:07 PM PDT 24 |
Jun 21 04:51:09 PM PDT 24 |
29379638 ps |
| T925 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.70937541 |
|
|
Jun 21 04:51:05 PM PDT 24 |
Jun 21 04:54:49 PM PDT 24 |
4827637469 ps |
| T926 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3791073133 |
|
|
Jun 21 04:52:20 PM PDT 24 |
Jun 21 04:52:22 PM PDT 24 |
40259341 ps |
| T927 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1201173055 |
|
|
Jun 21 04:52:31 PM PDT 24 |
Jun 21 04:52:37 PM PDT 24 |
79777082 ps |
| T928 |
/workspace/coverage/default/8.sram_ctrl_bijection.955548253 |
|
|
Jun 21 04:50:10 PM PDT 24 |
Jun 21 04:50:33 PM PDT 24 |
368440153 ps |
| T929 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.4289437797 |
|
|
Jun 21 04:50:33 PM PDT 24 |
Jun 21 04:53:31 PM PDT 24 |
7458053020 ps |
| T930 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2910174616 |
|
|
Jun 21 04:51:16 PM PDT 24 |
Jun 21 04:53:48 PM PDT 24 |
518943894 ps |
| T931 |
/workspace/coverage/default/28.sram_ctrl_regwen.623808788 |
|
|
Jun 21 04:51:20 PM PDT 24 |
Jun 21 05:16:39 PM PDT 24 |
40556836051 ps |
| T932 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.3627359848 |
|
|
Jun 21 04:51:45 PM PDT 24 |
Jun 21 04:51:46 PM PDT 24 |
92795976 ps |
| T933 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3728661798 |
|
|
Jun 21 04:50:53 PM PDT 24 |
Jun 21 04:50:58 PM PDT 24 |
92065115 ps |
| T934 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.709419150 |
|
|
Jun 21 04:51:14 PM PDT 24 |
Jun 21 04:51:21 PM PDT 24 |
192663704 ps |
| T935 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1366876175 |
|
|
Jun 21 04:50:57 PM PDT 24 |
Jun 21 04:54:09 PM PDT 24 |
28336471688 ps |
| T60 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3299763223 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:34 PM PDT 24 |
966955326 ps |
| T936 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1605596508 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:34 PM PDT 24 |
37676137 ps |
| T937 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2971753179 |
|
|
Jun 21 04:49:34 PM PDT 24 |
Jun 21 04:49:46 PM PDT 24 |
168147163 ps |
| T61 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3319008341 |
|
|
Jun 21 04:49:36 PM PDT 24 |
Jun 21 04:49:47 PM PDT 24 |
21847770 ps |
| T62 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.228160263 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:39 PM PDT 24 |
18047277 ps |
| T69 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3185042414 |
|
|
Jun 21 04:49:24 PM PDT 24 |
Jun 21 04:49:29 PM PDT 24 |
28057348 ps |
| T70 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3545533176 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:35 PM PDT 24 |
12685841 ps |
| T71 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3729608573 |
|
|
Jun 21 04:49:24 PM PDT 24 |
Jun 21 04:49:31 PM PDT 24 |
241493578 ps |
| T99 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1739976501 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
17103063 ps |
| T72 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1883884411 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:42 PM PDT 24 |
25172755 ps |
| T107 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.304242990 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
52476023 ps |
| T57 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3766286372 |
|
|
Jun 21 04:49:29 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
301015814 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1347336004 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:34 PM PDT 24 |
114746526 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3476547233 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:44 PM PDT 24 |
1231417831 ps |
| T939 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1540301952 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:34 PM PDT 24 |
1170905431 ps |
| T100 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1276930929 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:35 PM PDT 24 |
13162015 ps |
| T74 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1728307401 |
|
|
Jun 21 04:49:24 PM PDT 24 |
Jun 21 04:49:31 PM PDT 24 |
229197184 ps |
| T940 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3958577932 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:34 PM PDT 24 |
74266498 ps |
| T941 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1766037225 |
|
|
Jun 21 04:49:36 PM PDT 24 |
Jun 21 04:49:47 PM PDT 24 |
46794393 ps |
| T942 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.231541951 |
|
|
Jun 21 04:49:27 PM PDT 24 |
Jun 21 04:49:38 PM PDT 24 |
212477922 ps |
| T943 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2978701323 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:47 PM PDT 24 |
222896072 ps |
| T75 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2199376246 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:42 PM PDT 24 |
68793612 ps |
| T944 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2602077721 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:33 PM PDT 24 |
781937779 ps |
| T945 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1082055821 |
|
|
Jun 21 04:49:23 PM PDT 24 |
Jun 21 04:49:29 PM PDT 24 |
68601029 ps |
| T946 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4234558457 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:42 PM PDT 24 |
24722660 ps |
| T58 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.539055489 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:44 PM PDT 24 |
268613200 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3244906623 |
|
|
Jun 21 04:49:24 PM PDT 24 |
Jun 21 04:49:32 PM PDT 24 |
43595487 ps |
| T59 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2349440814 |
|
|
Jun 21 04:49:33 PM PDT 24 |
Jun 21 04:49:47 PM PDT 24 |
1156038929 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1646008438 |
|
|
Jun 21 04:49:32 PM PDT 24 |
Jun 21 04:49:46 PM PDT 24 |
128164169 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.911226516 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:37 PM PDT 24 |
685501483 ps |
| T947 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3236680284 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
126239976 ps |
| T93 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2207974449 |
|
|
Jun 21 04:49:19 PM PDT 24 |
Jun 21 04:49:24 PM PDT 24 |
2815070051 ps |
| T948 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.986096207 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:34 PM PDT 24 |
291825529 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.928149351 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:31 PM PDT 24 |
44403297 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.626035877 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
112043528 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3067196858 |
|
|
Jun 21 04:49:23 PM PDT 24 |
Jun 21 04:49:29 PM PDT 24 |
11985176 ps |
| T951 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.14950638 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:38 PM PDT 24 |
48293099 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3337847435 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
50378745 ps |
| T118 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3388591733 |
|
|
Jun 21 04:49:29 PM PDT 24 |
Jun 21 04:49:41 PM PDT 24 |
319824770 ps |
| T81 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1403463424 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
16010110 ps |
| T953 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3953255399 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
511852920 ps |
| T954 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1104808381 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:36 PM PDT 24 |
50815950 ps |
| T82 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.128327976 |
|
|
Jun 21 04:49:32 PM PDT 24 |
Jun 21 04:49:47 PM PDT 24 |
403692537 ps |
| T955 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.173047564 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:42 PM PDT 24 |
11600576 ps |
| T122 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.605446439 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:44 PM PDT 24 |
148352648 ps |
| T956 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1786546879 |
|
|
Jun 21 04:49:29 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
50768018 ps |
| T957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1882452922 |
|
|
Jun 21 04:49:33 PM PDT 24 |
Jun 21 04:49:46 PM PDT 24 |
134836470 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3950311915 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:42 PM PDT 24 |
16541588 ps |
| T958 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2743922956 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:35 PM PDT 24 |
18785087 ps |
| T959 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.843333784 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
26516692 ps |
| T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3449526782 |
|
|
Jun 21 04:49:23 PM PDT 24 |
Jun 21 04:49:30 PM PDT 24 |
38696873 ps |
| T961 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.601031363 |
|
|
Jun 21 04:49:27 PM PDT 24 |
Jun 21 04:49:37 PM PDT 24 |
118291436 ps |
| T962 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.483811370 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:45 PM PDT 24 |
234610458 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4253051357 |
|
|
Jun 21 04:49:35 PM PDT 24 |
Jun 21 04:49:47 PM PDT 24 |
32278792 ps |
| T84 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2608578833 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:33 PM PDT 24 |
390869172 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3606755106 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
22713422 ps |
| T965 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.417528457 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
29498617 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2351740031 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:36 PM PDT 24 |
24690208 ps |
| T129 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1816268481 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:36 PM PDT 24 |
519690859 ps |
| T95 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1094919312 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:38 PM PDT 24 |
15615452 ps |
| T967 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2039860185 |
|
|
Jun 21 04:49:29 PM PDT 24 |
Jun 21 04:49:42 PM PDT 24 |
98612064 ps |
| T94 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3976151861 |
|
|
Jun 21 04:49:32 PM PDT 24 |
Jun 21 04:49:46 PM PDT 24 |
406106696 ps |
| T968 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3917767872 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:38 PM PDT 24 |
57342172 ps |
| T969 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2795430511 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
25543408 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3075362670 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:45 PM PDT 24 |
310982253 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1246810223 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:46 PM PDT 24 |
132617148 ps |
| T96 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1550365069 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:41 PM PDT 24 |
433578502 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2574981300 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
669923356 ps |
| T128 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1800193335 |
|
|
Jun 21 04:49:36 PM PDT 24 |
Jun 21 04:49:49 PM PDT 24 |
661382726 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.214210617 |
|
|
Jun 21 04:49:29 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
35715765 ps |
| T130 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4032983073 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:44 PM PDT 24 |
784245569 ps |
| T126 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1511059273 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:36 PM PDT 24 |
130813099 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.910109111 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
41031844 ps |
| T123 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.497883593 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
100887279 ps |
| T97 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2229791764 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:45 PM PDT 24 |
468491064 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1285284430 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
58119023 ps |
| T976 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1498124579 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:46 PM PDT 24 |
555869471 ps |
| T977 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.67112567 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:39 PM PDT 24 |
1549860225 ps |
| T978 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3117868323 |
|
|
Jun 21 04:49:28 PM PDT 24 |
Jun 21 04:49:41 PM PDT 24 |
817793389 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3902889833 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:32 PM PDT 24 |
122253698 ps |
| T980 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4118724925 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:34 PM PDT 24 |
143162026 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.73337092 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
57180639 ps |
| T982 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2415420310 |
|
|
Jun 21 04:49:27 PM PDT 24 |
Jun 21 04:49:38 PM PDT 24 |
13705116 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.966159924 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
20898628 ps |
| T984 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4269478055 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
137322795 ps |
| T985 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1508547948 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:39 PM PDT 24 |
628959323 ps |
| T986 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.709050601 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:35 PM PDT 24 |
46561519 ps |
| T987 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3706717967 |
|
|
Jun 21 04:49:23 PM PDT 24 |
Jun 21 04:49:29 PM PDT 24 |
20491272 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3240773187 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:32 PM PDT 24 |
34201707 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3518175254 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:33 PM PDT 24 |
91930392 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3655078970 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:36 PM PDT 24 |
27002148 ps |
| T991 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.684774594 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:44 PM PDT 24 |
31687727 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3434210344 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:36 PM PDT 24 |
101292992 ps |
| T993 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2150780351 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:32 PM PDT 24 |
58500109 ps |
| T994 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1478671842 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:36 PM PDT 24 |
1869297525 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2850552222 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:36 PM PDT 24 |
36762802 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.333777570 |
|
|
Jun 21 04:49:25 PM PDT 24 |
Jun 21 04:49:35 PM PDT 24 |
614045197 ps |
| T997 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4176510038 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
31704247 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2179634516 |
|
|
Jun 21 04:49:27 PM PDT 24 |
Jun 21 04:49:37 PM PDT 24 |
59632358 ps |
| T999 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2810302361 |
|
|
Jun 21 04:49:22 PM PDT 24 |
Jun 21 04:49:26 PM PDT 24 |
17735222 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1765178958 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:44 PM PDT 24 |
71858449 ps |
| T1001 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2956630946 |
|
|
Jun 21 04:49:27 PM PDT 24 |
Jun 21 04:49:39 PM PDT 24 |
80992540 ps |
| T1002 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.513399560 |
|
|
Jun 21 04:49:24 PM PDT 24 |
Jun 21 04:49:31 PM PDT 24 |
45461886 ps |
| T1003 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.43783403 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:46 PM PDT 24 |
172279905 ps |
| T1004 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4101826877 |
|
|
Jun 21 04:49:31 PM PDT 24 |
Jun 21 04:49:43 PM PDT 24 |
26324924 ps |
| T1005 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.914173630 |
|
|
Jun 21 04:49:26 PM PDT 24 |
Jun 21 04:49:37 PM PDT 24 |
256189137 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3462793009 |
|
|
Jun 21 04:49:29 PM PDT 24 |
Jun 21 04:49:40 PM PDT 24 |
56185374 ps |
| T1006 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3414288574 |
|
|
Jun 21 04:49:30 PM PDT 24 |
Jun 21 04:49:42 PM PDT 24 |
43515866 ps |