Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145850882	1			T1	17694		T2	18580		T3	12014
instr_valid_dis	111696772	1			T1	17694		T2	18580		T3	12014
instr_en	25862402	1			T7	277474		T21	20026		T42	235072

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9993976	1			T7	110598		T22	20444		T42	99356
sram_ifetch_valid_disable	114096011	1			T1	17694		T2	18580		T3	12014
sram_ifetch_enable	21760895	1			T13	22874		T7	486200		T22	58784

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145850882	1			T1	17694		T2	18580		T3	12014
hw_debug_en_valid_off	112580139	1			T1	17694		T2	18580		T3	12014
hw_debug_en_on	23256309	1			T13	22874		T7	379040		T21	20026

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114096011	1			T1	17694		T2	18580		T3	12014
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99897141	1			T1	17694		T2	18580		T3	12014
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10853756	1			T7	66036		T21	20026		T42	67598
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4122582	1			T7	21588		T42	16420		T41	8982
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1689382	1			T7	21588		T41	8982		T9	73212
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1778964	1			T42	16420		T8	44624		T9	58380
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4290360	1			T7	53960		T22	670		T42	82936
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1476780	1			T7	53960		T22	670		T8	19100
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1981172	1			T42	82936		T9	60000		T136	89538
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9730353	1			T7	20106		T21	20026		T22	6590
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3646405	1			T22	6590		T42	52468		T8	65646
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4583864	1			T21	20026		T41	35402		T8	19858

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10429958	1			T7	211438		T42	68118		T41	101144
lc_exec_en	9235596	1			T13	22874		T7	304974		T22	18346
valid_exec_dis	108187029	1			T1	17694		T2	18580		T3	12014
invalid_exec_dis	31754871	1			T13	22874		T7	596798		T22	79228