Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43685312	1			T1	8076		T2	7586		T3	4885
triple_byte_access	2483657	1			T1	151		T2	320		T3	226
halfword_access	3725156	1			T1	237		T2	495		T3	326
byte_access	4977124	1			T1	302		T2	734		T3	449
zero_access	1252623	1			T1	81		T2	155		T3	121

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28002073

1

T1

4438

T2

4649

T3

3042

auto[1]

28121799

1

T1

4409

T2

4641

T3

2965

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21787221	1			T1	4043		T2	3785		T3	2478
auto[0]	triple_byte_access	1238310	1			T1	80		T2	163		T3	114
auto[0]	halfword_access	1859484	1			T1	119		T2	256		T3	162
auto[0]	byte_access	2487280	1			T1	147		T2	363		T3	223
auto[0]	zero_access	629778	1			T1	49		T2	82		T3	65
auto[1]	word_access	21898091	1			T1	4033		T2	3801		T3	2407
auto[1]	triple_byte_access	1245347	1			T1	71		T2	157		T3	112
auto[1]	halfword_access	1865672	1			T1	118		T2	239		T3	164
auto[1]	byte_access	2489844	1			T1	155		T2	371		T3	226
auto[1]	zero_access	622845	1			T1	32		T2	73		T3	56