| T787 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2488145669 |
|
|
Jun 22 06:18:45 PM PDT 24 |
Jun 22 06:20:09 PM PDT 24 |
1729606308 ps |
| T788 |
/workspace/coverage/default/27.sram_ctrl_bijection.1141521677 |
|
|
Jun 22 06:14:57 PM PDT 24 |
Jun 22 06:16:09 PM PDT 24 |
4479784643 ps |
| T789 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2388131073 |
|
|
Jun 22 06:16:32 PM PDT 24 |
Jun 22 06:19:05 PM PDT 24 |
6713246443 ps |
| T790 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.596053180 |
|
|
Jun 22 06:13:53 PM PDT 24 |
Jun 22 06:13:59 PM PDT 24 |
3621994632 ps |
| T791 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.871008030 |
|
|
Jun 22 06:14:58 PM PDT 24 |
Jun 22 06:41:33 PM PDT 24 |
11391611754 ps |
| T792 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3132991832 |
|
|
Jun 22 06:15:06 PM PDT 24 |
Jun 22 06:20:51 PM PDT 24 |
3642090150 ps |
| T793 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1026090791 |
|
|
Jun 22 06:18:33 PM PDT 24 |
Jun 22 06:25:06 PM PDT 24 |
5429651156 ps |
| T794 |
/workspace/coverage/default/23.sram_ctrl_smoke.710264841 |
|
|
Jun 22 06:14:26 PM PDT 24 |
Jun 22 06:14:57 PM PDT 24 |
407344986 ps |
| T795 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1183095690 |
|
|
Jun 22 06:14:16 PM PDT 24 |
Jun 22 06:14:33 PM PDT 24 |
302943729 ps |
| T796 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2926193448 |
|
|
Jun 22 06:14:07 PM PDT 24 |
Jun 22 06:25:56 PM PDT 24 |
5244830519 ps |
| T797 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1689613159 |
|
|
Jun 22 06:13:54 PM PDT 24 |
Jun 22 06:13:57 PM PDT 24 |
78460919 ps |
| T798 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4090596511 |
|
|
Jun 22 06:12:40 PM PDT 24 |
Jun 22 06:34:35 PM PDT 24 |
6546272532 ps |
| T799 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2422504338 |
|
|
Jun 22 06:12:47 PM PDT 24 |
Jun 22 06:12:58 PM PDT 24 |
1134624157 ps |
| T800 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1914516388 |
|
|
Jun 22 06:12:50 PM PDT 24 |
Jun 22 06:26:49 PM PDT 24 |
14936598012 ps |
| T801 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.667304262 |
|
|
Jun 22 06:12:51 PM PDT 24 |
Jun 22 06:47:01 PM PDT 24 |
11196800254 ps |
| T802 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.741498807 |
|
|
Jun 22 06:12:38 PM PDT 24 |
Jun 22 06:20:52 PM PDT 24 |
73840280992 ps |
| T803 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2151938622 |
|
|
Jun 22 06:14:01 PM PDT 24 |
Jun 22 06:16:25 PM PDT 24 |
542577268 ps |
| T804 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2734136080 |
|
|
Jun 22 06:15:21 PM PDT 24 |
Jun 22 06:18:43 PM PDT 24 |
2730876083 ps |
| T805 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2651934813 |
|
|
Jun 22 06:14:48 PM PDT 24 |
Jun 22 06:14:59 PM PDT 24 |
1678191287 ps |
| T806 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2064148094 |
|
|
Jun 22 06:13:59 PM PDT 24 |
Jun 22 06:15:52 PM PDT 24 |
528372917 ps |
| T807 |
/workspace/coverage/default/40.sram_ctrl_executable.2833105893 |
|
|
Jun 22 06:17:00 PM PDT 24 |
Jun 22 06:23:18 PM PDT 24 |
6196961665 ps |
| T808 |
/workspace/coverage/default/38.sram_ctrl_executable.3377601066 |
|
|
Jun 22 06:16:49 PM PDT 24 |
Jun 22 06:27:56 PM PDT 24 |
26964883668 ps |
| T809 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3251924736 |
|
|
Jun 22 06:16:24 PM PDT 24 |
Jun 22 06:16:28 PM PDT 24 |
942844705 ps |
| T30 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.3573066085 |
|
|
Jun 22 06:12:51 PM PDT 24 |
Jun 22 06:12:54 PM PDT 24 |
1038993055 ps |
| T810 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1606125146 |
|
|
Jun 22 06:15:30 PM PDT 24 |
Jun 22 06:17:30 PM PDT 24 |
159287615 ps |
| T811 |
/workspace/coverage/default/39.sram_ctrl_alert_test.4073211086 |
|
|
Jun 22 06:16:56 PM PDT 24 |
Jun 22 06:16:57 PM PDT 24 |
26010723 ps |
| T812 |
/workspace/coverage/default/12.sram_ctrl_regwen.3062388452 |
|
|
Jun 22 06:13:27 PM PDT 24 |
Jun 22 06:24:12 PM PDT 24 |
10336138126 ps |
| T813 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2400243731 |
|
|
Jun 22 06:12:52 PM PDT 24 |
Jun 22 06:19:40 PM PDT 24 |
4288393678 ps |
| T814 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2031617806 |
|
|
Jun 22 06:13:42 PM PDT 24 |
Jun 22 06:13:56 PM PDT 24 |
271029453 ps |
| T815 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.131907729 |
|
|
Jun 22 06:17:01 PM PDT 24 |
Jun 22 06:20:58 PM PDT 24 |
9788418277 ps |
| T816 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3553408557 |
|
|
Jun 22 06:13:07 PM PDT 24 |
Jun 22 06:19:56 PM PDT 24 |
23128720890 ps |
| T817 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.156435413 |
|
|
Jun 22 06:17:44 PM PDT 24 |
Jun 22 06:39:24 PM PDT 24 |
3804341978 ps |
| T818 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1231782324 |
|
|
Jun 22 06:13:25 PM PDT 24 |
Jun 22 06:13:29 PM PDT 24 |
52764075 ps |
| T819 |
/workspace/coverage/default/45.sram_ctrl_regwen.2849650449 |
|
|
Jun 22 06:17:58 PM PDT 24 |
Jun 22 06:36:35 PM PDT 24 |
26685362129 ps |
| T820 |
/workspace/coverage/default/23.sram_ctrl_partial_access.449424147 |
|
|
Jun 22 06:14:24 PM PDT 24 |
Jun 22 06:14:40 PM PDT 24 |
218649510 ps |
| T821 |
/workspace/coverage/default/11.sram_ctrl_executable.4190915393 |
|
|
Jun 22 06:13:26 PM PDT 24 |
Jun 22 06:21:52 PM PDT 24 |
17779238780 ps |
| T822 |
/workspace/coverage/default/0.sram_ctrl_executable.2721603680 |
|
|
Jun 22 06:12:50 PM PDT 24 |
Jun 22 06:21:03 PM PDT 24 |
1812977830 ps |
| T823 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.237810044 |
|
|
Jun 22 06:13:20 PM PDT 24 |
Jun 22 06:19:28 PM PDT 24 |
2045233505 ps |
| T824 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3441367891 |
|
|
Jun 22 06:17:16 PM PDT 24 |
Jun 22 06:44:29 PM PDT 24 |
6540301911 ps |
| T825 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1469851672 |
|
|
Jun 22 06:15:48 PM PDT 24 |
Jun 22 06:15:53 PM PDT 24 |
282339443 ps |
| T826 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.191285046 |
|
|
Jun 22 06:16:48 PM PDT 24 |
Jun 22 06:16:53 PM PDT 24 |
421595865 ps |
| T827 |
/workspace/coverage/default/18.sram_ctrl_smoke.2610875303 |
|
|
Jun 22 06:13:53 PM PDT 24 |
Jun 22 06:16:10 PM PDT 24 |
3278118427 ps |
| T828 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1451957026 |
|
|
Jun 22 06:13:05 PM PDT 24 |
Jun 22 06:13:06 PM PDT 24 |
35107083 ps |
| T829 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2928670395 |
|
|
Jun 22 06:12:42 PM PDT 24 |
Jun 22 06:12:49 PM PDT 24 |
176589937 ps |
| T830 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3117214661 |
|
|
Jun 22 06:12:53 PM PDT 24 |
Jun 22 06:15:54 PM PDT 24 |
2428638776 ps |
| T831 |
/workspace/coverage/default/26.sram_ctrl_regwen.2480667119 |
|
|
Jun 22 06:14:52 PM PDT 24 |
Jun 22 06:21:26 PM PDT 24 |
10011552951 ps |
| T832 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.716381574 |
|
|
Jun 22 06:15:15 PM PDT 24 |
Jun 22 06:20:45 PM PDT 24 |
14417458566 ps |
| T833 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4037446420 |
|
|
Jun 22 06:17:42 PM PDT 24 |
Jun 22 06:22:19 PM PDT 24 |
19980948980 ps |
| T834 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2060439053 |
|
|
Jun 22 06:17:44 PM PDT 24 |
Jun 22 06:17:49 PM PDT 24 |
1677254975 ps |
| T835 |
/workspace/coverage/default/40.sram_ctrl_bijection.1110814028 |
|
|
Jun 22 06:16:55 PM PDT 24 |
Jun 22 06:17:41 PM PDT 24 |
2879301720 ps |
| T836 |
/workspace/coverage/default/32.sram_ctrl_partial_access.1143623791 |
|
|
Jun 22 06:15:43 PM PDT 24 |
Jun 22 06:15:46 PM PDT 24 |
49298726 ps |
| T837 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3939662128 |
|
|
Jun 22 06:12:58 PM PDT 24 |
Jun 22 06:27:44 PM PDT 24 |
8488403948 ps |
| T838 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1910491116 |
|
|
Jun 22 06:14:09 PM PDT 24 |
Jun 22 06:14:11 PM PDT 24 |
28574320 ps |
| T839 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1252791032 |
|
|
Jun 22 06:18:09 PM PDT 24 |
Jun 22 06:18:16 PM PDT 24 |
2243443044 ps |
| T840 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2133592416 |
|
|
Jun 22 06:16:49 PM PDT 24 |
Jun 22 06:16:53 PM PDT 24 |
98557533 ps |
| T841 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1964281654 |
|
|
Jun 22 06:18:21 PM PDT 24 |
Jun 22 06:28:51 PM PDT 24 |
2867264532 ps |
| T842 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.3124242268 |
|
|
Jun 22 06:12:39 PM PDT 24 |
Jun 22 06:34:34 PM PDT 24 |
3158622178 ps |
| T843 |
/workspace/coverage/default/6.sram_ctrl_executable.2288984281 |
|
|
Jun 22 06:13:04 PM PDT 24 |
Jun 22 06:21:48 PM PDT 24 |
4148124869 ps |
| T844 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2344913905 |
|
|
Jun 22 06:14:17 PM PDT 24 |
Jun 22 06:14:23 PM PDT 24 |
867669017 ps |
| T845 |
/workspace/coverage/default/32.sram_ctrl_smoke.3102964262 |
|
|
Jun 22 06:15:43 PM PDT 24 |
Jun 22 06:15:46 PM PDT 24 |
66893682 ps |
| T846 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.475514859 |
|
|
Jun 22 06:18:21 PM PDT 24 |
Jun 22 06:18:22 PM PDT 24 |
33528463 ps |
| T847 |
/workspace/coverage/default/47.sram_ctrl_regwen.410292566 |
|
|
Jun 22 06:18:22 PM PDT 24 |
Jun 22 06:23:38 PM PDT 24 |
5108637090 ps |
| T848 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2133069322 |
|
|
Jun 22 06:13:12 PM PDT 24 |
Jun 22 06:15:21 PM PDT 24 |
1858903433 ps |
| T849 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.181861530 |
|
|
Jun 22 06:16:46 PM PDT 24 |
Jun 22 06:19:23 PM PDT 24 |
719717318 ps |
| T850 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1317050314 |
|
|
Jun 22 06:16:03 PM PDT 24 |
Jun 22 06:22:26 PM PDT 24 |
10541091949 ps |
| T851 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.143504235 |
|
|
Jun 22 06:16:09 PM PDT 24 |
Jun 22 06:16:44 PM PDT 24 |
124749177 ps |
| T852 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.243424775 |
|
|
Jun 22 06:12:40 PM PDT 24 |
Jun 22 06:12:51 PM PDT 24 |
448928685 ps |
| T853 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1794048265 |
|
|
Jun 22 06:12:39 PM PDT 24 |
Jun 22 06:18:44 PM PDT 24 |
21179616731 ps |
| T854 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.141903215 |
|
|
Jun 22 06:13:12 PM PDT 24 |
Jun 22 06:15:17 PM PDT 24 |
3936342888 ps |
| T855 |
/workspace/coverage/default/41.sram_ctrl_smoke.1566853600 |
|
|
Jun 22 06:17:14 PM PDT 24 |
Jun 22 06:17:22 PM PDT 24 |
49971868 ps |
| T856 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2820080824 |
|
|
Jun 22 06:18:53 PM PDT 24 |
Jun 22 06:18:57 PM PDT 24 |
381895388 ps |
| T857 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.384484307 |
|
|
Jun 22 06:14:31 PM PDT 24 |
Jun 22 06:14:33 PM PDT 24 |
676755485 ps |
| T858 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3954362363 |
|
|
Jun 22 06:18:51 PM PDT 24 |
Jun 22 07:21:17 PM PDT 24 |
48819865942 ps |
| T859 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3209038846 |
|
|
Jun 22 06:15:41 PM PDT 24 |
Jun 22 07:32:57 PM PDT 24 |
69610434821 ps |
| T860 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3703590538 |
|
|
Jun 22 06:15:28 PM PDT 24 |
Jun 22 06:15:35 PM PDT 24 |
351568280 ps |
| T861 |
/workspace/coverage/default/18.sram_ctrl_executable.3869860573 |
|
|
Jun 22 06:13:58 PM PDT 24 |
Jun 22 06:30:09 PM PDT 24 |
11345974401 ps |
| T862 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3935476221 |
|
|
Jun 22 06:12:41 PM PDT 24 |
Jun 22 06:14:56 PM PDT 24 |
719714027 ps |
| T863 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1233924638 |
|
|
Jun 22 06:12:41 PM PDT 24 |
Jun 22 06:13:55 PM PDT 24 |
251261801 ps |
| T864 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.478735212 |
|
|
Jun 22 06:15:46 PM PDT 24 |
Jun 22 06:21:13 PM PDT 24 |
3266059690 ps |
| T865 |
/workspace/coverage/default/33.sram_ctrl_stress_all.3595411991 |
|
|
Jun 22 06:16:03 PM PDT 24 |
Jun 22 06:18:29 PM PDT 24 |
6924712377 ps |
| T866 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1610357674 |
|
|
Jun 22 06:13:26 PM PDT 24 |
Jun 22 06:37:40 PM PDT 24 |
14860183255 ps |
| T867 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2739455280 |
|
|
Jun 22 06:14:53 PM PDT 24 |
Jun 22 06:27:47 PM PDT 24 |
2016741547 ps |
| T868 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2188776845 |
|
|
Jun 22 06:17:54 PM PDT 24 |
Jun 22 06:18:54 PM PDT 24 |
196377815 ps |
| T869 |
/workspace/coverage/default/31.sram_ctrl_smoke.1503458912 |
|
|
Jun 22 06:15:29 PM PDT 24 |
Jun 22 06:15:32 PM PDT 24 |
60678376 ps |
| T870 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.3452593378 |
|
|
Jun 22 06:12:59 PM PDT 24 |
Jun 22 06:13:04 PM PDT 24 |
291639668 ps |
| T871 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.678136631 |
|
|
Jun 22 06:12:40 PM PDT 24 |
Jun 22 06:12:57 PM PDT 24 |
66812613 ps |
| T872 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.577088860 |
|
|
Jun 22 06:14:06 PM PDT 24 |
Jun 22 06:14:13 PM PDT 24 |
172060231 ps |
| T873 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.2941432185 |
|
|
Jun 22 06:14:56 PM PDT 24 |
Jun 22 06:15:05 PM PDT 24 |
1388644099 ps |
| T874 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1449787703 |
|
|
Jun 22 06:13:26 PM PDT 24 |
Jun 22 06:23:38 PM PDT 24 |
2223873022 ps |
| T875 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.444656717 |
|
|
Jun 22 06:15:22 PM PDT 24 |
Jun 22 06:24:57 PM PDT 24 |
39927587534 ps |
| T876 |
/workspace/coverage/default/24.sram_ctrl_partial_access.162786005 |
|
|
Jun 22 06:14:39 PM PDT 24 |
Jun 22 06:15:04 PM PDT 24 |
10952682328 ps |
| T877 |
/workspace/coverage/default/1.sram_ctrl_smoke.4268833913 |
|
|
Jun 22 06:12:39 PM PDT 24 |
Jun 22 06:12:41 PM PDT 24 |
38077061 ps |
| T878 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2852409880 |
|
|
Jun 22 06:12:54 PM PDT 24 |
Jun 22 06:13:40 PM PDT 24 |
787325467 ps |
| T879 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.3741677565 |
|
|
Jun 22 06:13:26 PM PDT 24 |
Jun 22 06:16:09 PM PDT 24 |
3620188901 ps |
| T880 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3780739734 |
|
|
Jun 22 06:12:43 PM PDT 24 |
Jun 22 06:12:45 PM PDT 24 |
28053100 ps |
| T881 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.2840443411 |
|
|
Jun 22 06:12:53 PM PDT 24 |
Jun 22 06:12:59 PM PDT 24 |
187124831 ps |
| T882 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.808312053 |
|
|
Jun 22 06:13:11 PM PDT 24 |
Jun 22 06:13:17 PM PDT 24 |
338161793 ps |
| T883 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2903936806 |
|
|
Jun 22 06:17:09 PM PDT 24 |
Jun 22 06:19:25 PM PDT 24 |
1792719397 ps |
| T884 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2189935405 |
|
|
Jun 22 06:16:56 PM PDT 24 |
Jun 22 06:17:02 PM PDT 24 |
234809338 ps |
| T885 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.4177967495 |
|
|
Jun 22 06:13:18 PM PDT 24 |
Jun 22 06:15:40 PM PDT 24 |
138378131 ps |
| T886 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1851596515 |
|
|
Jun 22 06:15:32 PM PDT 24 |
Jun 22 06:22:54 PM PDT 24 |
90434721110 ps |
| T887 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2897499053 |
|
|
Jun 22 06:13:21 PM PDT 24 |
Jun 22 06:15:19 PM PDT 24 |
594791128 ps |
| T888 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3133929096 |
|
|
Jun 22 06:14:16 PM PDT 24 |
Jun 22 06:16:30 PM PDT 24 |
1351031909 ps |
| T889 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1352127383 |
|
|
Jun 22 06:13:53 PM PDT 24 |
Jun 22 06:16:12 PM PDT 24 |
25107222144 ps |
| T890 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2779416266 |
|
|
Jun 22 06:16:07 PM PDT 24 |
Jun 22 06:17:05 PM PDT 24 |
633572566 ps |
| T891 |
/workspace/coverage/default/48.sram_ctrl_executable.639883056 |
|
|
Jun 22 06:18:37 PM PDT 24 |
Jun 22 06:29:56 PM PDT 24 |
11445914071 ps |
| T892 |
/workspace/coverage/default/14.sram_ctrl_partial_access.2021271750 |
|
|
Jun 22 06:13:27 PM PDT 24 |
Jun 22 06:13:39 PM PDT 24 |
483739445 ps |
| T893 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.4140680461 |
|
|
Jun 22 06:13:18 PM PDT 24 |
Jun 22 06:26:56 PM PDT 24 |
2182729513 ps |
| T894 |
/workspace/coverage/default/1.sram_ctrl_stress_all.965072685 |
|
|
Jun 22 06:12:39 PM PDT 24 |
Jun 22 07:16:02 PM PDT 24 |
40914726144 ps |
| T895 |
/workspace/coverage/default/15.sram_ctrl_bijection.4027693750 |
|
|
Jun 22 06:13:34 PM PDT 24 |
Jun 22 06:14:47 PM PDT 24 |
4911889765 ps |
| T896 |
/workspace/coverage/default/37.sram_ctrl_executable.2596402932 |
|
|
Jun 22 06:16:35 PM PDT 24 |
Jun 22 06:19:28 PM PDT 24 |
1698738108 ps |
| T897 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3402892196 |
|
|
Jun 22 06:12:39 PM PDT 24 |
Jun 22 06:13:06 PM PDT 24 |
495891874 ps |
| T898 |
/workspace/coverage/default/11.sram_ctrl_stress_all.2787287638 |
|
|
Jun 22 06:13:26 PM PDT 24 |
Jun 22 07:09:12 PM PDT 24 |
31008613453 ps |
| T899 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3585992242 |
|
|
Jun 22 06:13:11 PM PDT 24 |
Jun 22 06:15:30 PM PDT 24 |
5964462677 ps |
| T900 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2579362859 |
|
|
Jun 22 06:17:33 PM PDT 24 |
Jun 22 06:17:36 PM PDT 24 |
674035970 ps |
| T901 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1921212850 |
|
|
Jun 22 06:17:01 PM PDT 24 |
Jun 22 06:17:07 PM PDT 24 |
599449417 ps |
| T902 |
/workspace/coverage/default/15.sram_ctrl_smoke.1072920356 |
|
|
Jun 22 06:13:34 PM PDT 24 |
Jun 22 06:13:39 PM PDT 24 |
261933637 ps |
| T903 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.4221034595 |
|
|
Jun 22 06:17:00 PM PDT 24 |
Jun 22 06:18:33 PM PDT 24 |
464555997 ps |
| T904 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2554322830 |
|
|
Jun 22 06:15:25 PM PDT 24 |
Jun 22 06:19:42 PM PDT 24 |
634652561 ps |
| T905 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2475553164 |
|
|
Jun 22 06:15:31 PM PDT 24 |
Jun 22 06:17:38 PM PDT 24 |
5261407243 ps |
| T906 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.1310216892 |
|
|
Jun 22 06:15:01 PM PDT 24 |
Jun 22 06:15:33 PM PDT 24 |
85599260 ps |
| T907 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.483918023 |
|
|
Jun 22 06:14:14 PM PDT 24 |
Jun 22 06:14:18 PM PDT 24 |
239889997 ps |
| T908 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2885138114 |
|
|
Jun 22 06:17:35 PM PDT 24 |
Jun 22 06:35:53 PM PDT 24 |
21125784008 ps |
| T909 |
/workspace/coverage/default/34.sram_ctrl_smoke.237137250 |
|
|
Jun 22 06:16:05 PM PDT 24 |
Jun 22 06:16:06 PM PDT 24 |
292069000 ps |
| T910 |
/workspace/coverage/default/43.sram_ctrl_bijection.3282045726 |
|
|
Jun 22 06:17:31 PM PDT 24 |
Jun 22 06:18:47 PM PDT 24 |
24163836009 ps |
| T911 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.483996953 |
|
|
Jun 22 06:15:00 PM PDT 24 |
Jun 22 06:27:37 PM PDT 24 |
41629947839 ps |
| T912 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.285472563 |
|
|
Jun 22 06:14:58 PM PDT 24 |
Jun 22 06:16:06 PM PDT 24 |
498017877 ps |
| T913 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3048184012 |
|
|
Jun 22 06:18:43 PM PDT 24 |
Jun 22 06:21:15 PM PDT 24 |
1614614696 ps |
| T914 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2057429525 |
|
|
Jun 22 06:18:15 PM PDT 24 |
Jun 22 06:18:36 PM PDT 24 |
1005613107 ps |
| T915 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3947214607 |
|
|
Jun 22 06:14:08 PM PDT 24 |
Jun 22 06:20:46 PM PDT 24 |
5766195661 ps |
| T31 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2600672753 |
|
|
Jun 22 06:12:37 PM PDT 24 |
Jun 22 06:12:39 PM PDT 24 |
118892798 ps |
| T916 |
/workspace/coverage/default/29.sram_ctrl_smoke.3747057011 |
|
|
Jun 22 06:15:15 PM PDT 24 |
Jun 22 06:15:33 PM PDT 24 |
1472569755 ps |
| T917 |
/workspace/coverage/default/49.sram_ctrl_smoke.955793255 |
|
|
Jun 22 06:18:38 PM PDT 24 |
Jun 22 06:19:33 PM PDT 24 |
418271014 ps |
| T918 |
/workspace/coverage/default/15.sram_ctrl_regwen.1228257486 |
|
|
Jun 22 06:13:31 PM PDT 24 |
Jun 22 06:32:36 PM PDT 24 |
5962054158 ps |
| T919 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.2641911759 |
|
|
Jun 22 06:16:25 PM PDT 24 |
Jun 22 06:16:26 PM PDT 24 |
49828866 ps |
| T920 |
/workspace/coverage/default/47.sram_ctrl_executable.1727019232 |
|
|
Jun 22 06:18:24 PM PDT 24 |
Jun 22 06:48:47 PM PDT 24 |
28960683431 ps |
| T921 |
/workspace/coverage/default/6.sram_ctrl_regwen.368696499 |
|
|
Jun 22 06:13:00 PM PDT 24 |
Jun 22 06:16:09 PM PDT 24 |
2609833143 ps |
| T922 |
/workspace/coverage/default/23.sram_ctrl_stress_all.587291682 |
|
|
Jun 22 06:14:32 PM PDT 24 |
Jun 22 07:07:52 PM PDT 24 |
52270691329 ps |
| T923 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2095588050 |
|
|
Jun 22 06:16:10 PM PDT 24 |
Jun 22 06:16:17 PM PDT 24 |
694271669 ps |
| T924 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1783796746 |
|
|
Jun 22 06:14:55 PM PDT 24 |
Jun 22 06:17:45 PM PDT 24 |
2795172603 ps |
| T925 |
/workspace/coverage/default/5.sram_ctrl_executable.991100482 |
|
|
Jun 22 06:12:56 PM PDT 24 |
Jun 22 06:27:21 PM PDT 24 |
41301293855 ps |
| T926 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.2832827441 |
|
|
Jun 22 06:13:10 PM PDT 24 |
Jun 22 06:14:42 PM PDT 24 |
258467946 ps |
| T927 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1638683967 |
|
|
Jun 22 06:17:36 PM PDT 24 |
Jun 22 06:58:28 PM PDT 24 |
60262304583 ps |
| T928 |
/workspace/coverage/default/13.sram_ctrl_regwen.2032253773 |
|
|
Jun 22 06:13:25 PM PDT 24 |
Jun 22 06:15:44 PM PDT 24 |
268361945 ps |
| T929 |
/workspace/coverage/default/6.sram_ctrl_bijection.1925111322 |
|
|
Jun 22 06:12:55 PM PDT 24 |
Jun 22 06:13:12 PM PDT 24 |
3071074386 ps |
| T61 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2420933492 |
|
|
Jun 22 04:46:12 PM PDT 24 |
Jun 22 04:46:16 PM PDT 24 |
799959352 ps |
| T62 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2395035220 |
|
|
Jun 22 04:46:09 PM PDT 24 |
Jun 22 04:46:12 PM PDT 24 |
13569036 ps |
| T930 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.93598528 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:22 PM PDT 24 |
51390153 ps |
| T63 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1714310301 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:21 PM PDT 24 |
26149125 ps |
| T931 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4148790257 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:22 PM PDT 24 |
51899086 ps |
| T94 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.708111343 |
|
|
Jun 22 04:46:05 PM PDT 24 |
Jun 22 04:46:07 PM PDT 24 |
25307432 ps |
| T932 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.799370068 |
|
|
Jun 22 04:46:11 PM PDT 24 |
Jun 22 04:46:15 PM PDT 24 |
84352580 ps |
| T58 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1249249625 |
|
|
Jun 22 04:46:10 PM PDT 24 |
Jun 22 04:46:13 PM PDT 24 |
85091436 ps |
| T933 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2174688509 |
|
|
Jun 22 04:46:10 PM PDT 24 |
Jun 22 04:46:14 PM PDT 24 |
41055325 ps |
| T73 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3452166173 |
|
|
Jun 22 04:46:37 PM PDT 24 |
Jun 22 04:46:41 PM PDT 24 |
1068440093 ps |
| T74 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.975392968 |
|
|
Jun 22 04:46:09 PM PDT 24 |
Jun 22 04:46:14 PM PDT 24 |
622214567 ps |
| T75 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.943587901 |
|
|
Jun 22 04:46:17 PM PDT 24 |
Jun 22 04:46:21 PM PDT 24 |
1549776558 ps |
| T95 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1697814428 |
|
|
Jun 22 04:46:25 PM PDT 24 |
Jun 22 04:46:27 PM PDT 24 |
51881857 ps |
| T76 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.280875184 |
|
|
Jun 22 04:46:06 PM PDT 24 |
Jun 22 04:46:08 PM PDT 24 |
16937122 ps |
| T934 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1035066553 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:24 PM PDT 24 |
40199397 ps |
| T103 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3175491559 |
|
|
Jun 22 04:46:18 PM PDT 24 |
Jun 22 04:46:20 PM PDT 24 |
37843610 ps |
| T935 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.637715971 |
|
|
Jun 22 04:46:22 PM PDT 24 |
Jun 22 04:46:24 PM PDT 24 |
71835543 ps |
| T96 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.499750335 |
|
|
Jun 22 04:46:11 PM PDT 24 |
Jun 22 04:46:13 PM PDT 24 |
139630376 ps |
| T97 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1466771534 |
|
|
Jun 22 04:46:16 PM PDT 24 |
Jun 22 04:46:18 PM PDT 24 |
26665273 ps |
| T936 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3311696299 |
|
|
Jun 22 04:46:06 PM PDT 24 |
Jun 22 04:46:08 PM PDT 24 |
33507801 ps |
| T77 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2679434534 |
|
|
Jun 22 04:46:17 PM PDT 24 |
Jun 22 04:46:21 PM PDT 24 |
763533724 ps |
| T78 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1376961504 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:21 PM PDT 24 |
27943355 ps |
| T79 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1714957226 |
|
|
Jun 22 04:46:11 PM PDT 24 |
Jun 22 04:46:15 PM PDT 24 |
1902354064 ps |
| T937 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1581788794 |
|
|
Jun 22 04:46:24 PM PDT 24 |
Jun 22 04:46:26 PM PDT 24 |
116226212 ps |
| T938 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2923747070 |
|
|
Jun 22 04:46:25 PM PDT 24 |
Jun 22 04:46:26 PM PDT 24 |
35412546 ps |
| T83 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.751232916 |
|
|
Jun 22 04:46:25 PM PDT 24 |
Jun 22 04:46:27 PM PDT 24 |
37858585 ps |
| T59 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2198324568 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:22 PM PDT 24 |
895969596 ps |
| T939 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.702487889 |
|
|
Jun 22 04:46:18 PM PDT 24 |
Jun 22 04:46:20 PM PDT 24 |
30914732 ps |
| T940 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3032434759 |
|
|
Jun 22 04:46:05 PM PDT 24 |
Jun 22 04:46:10 PM PDT 24 |
486805130 ps |
| T84 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1966244569 |
|
|
Jun 22 04:46:24 PM PDT 24 |
Jun 22 04:46:27 PM PDT 24 |
436702253 ps |
| T60 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.811550519 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:21 PM PDT 24 |
259227003 ps |
| T941 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1571472455 |
|
|
Jun 22 04:46:32 PM PDT 24 |
Jun 22 04:46:33 PM PDT 24 |
32141123 ps |
| T942 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1294034616 |
|
|
Jun 22 04:46:23 PM PDT 24 |
Jun 22 04:46:25 PM PDT 24 |
17972672 ps |
| T126 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4056726946 |
|
|
Jun 22 04:46:09 PM PDT 24 |
Jun 22 04:46:13 PM PDT 24 |
204124377 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2110019280 |
|
|
Jun 22 04:46:16 PM PDT 24 |
Jun 22 04:46:18 PM PDT 24 |
57735473 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.715198239 |
|
|
Jun 22 04:46:03 PM PDT 24 |
Jun 22 04:46:06 PM PDT 24 |
482202101 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.421158125 |
|
|
Jun 22 04:46:18 PM PDT 24 |
Jun 22 04:46:19 PM PDT 24 |
44663354 ps |
| T85 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1791525764 |
|
|
Jun 22 04:46:25 PM PDT 24 |
Jun 22 04:46:28 PM PDT 24 |
879892065 ps |
| T90 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3685066169 |
|
|
Jun 22 04:46:29 PM PDT 24 |
Jun 22 04:46:33 PM PDT 24 |
3611338640 ps |
| T945 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3655347276 |
|
|
Jun 22 04:46:45 PM PDT 24 |
Jun 22 04:46:47 PM PDT 24 |
54693351 ps |
| T91 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.459551579 |
|
|
Jun 22 04:46:20 PM PDT 24 |
Jun 22 04:46:22 PM PDT 24 |
238776654 ps |
| T946 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2997954172 |
|
|
Jun 22 04:46:34 PM PDT 24 |
Jun 22 04:46:35 PM PDT 24 |
99690017 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4099720621 |
|
|
Jun 22 04:46:16 PM PDT 24 |
Jun 22 04:46:17 PM PDT 24 |
18549362 ps |
| T125 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2771940709 |
|
|
Jun 22 04:46:18 PM PDT 24 |
Jun 22 04:46:22 PM PDT 24 |
193295114 ps |
| T948 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.592402305 |
|
|
Jun 22 04:46:18 PM PDT 24 |
Jun 22 04:46:22 PM PDT 24 |
56717700 ps |
| T949 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.209629270 |
|
|
Jun 22 04:46:18 PM PDT 24 |
Jun 22 04:46:21 PM PDT 24 |
1007897232 ps |
| T950 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3848523051 |
|
|
Jun 22 04:46:38 PM PDT 24 |
Jun 22 04:46:39 PM PDT 24 |
72853430 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3559919203 |
|
|
Jun 22 04:46:01 PM PDT 24 |
Jun 22 04:46:03 PM PDT 24 |
109926687 ps |
| T952 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2655715070 |
|
|
Jun 22 04:46:42 PM PDT 24 |
Jun 22 04:46:43 PM PDT 24 |
115309947 ps |
| T92 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3587280088 |
|
|
Jun 22 04:46:18 PM PDT 24 |
Jun 22 04:46:22 PM PDT 24 |
2038375271 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.413856031 |
|
|
Jun 22 04:46:37 PM PDT 24 |
Jun 22 04:46:39 PM PDT 24 |
314428849 ps |
| T954 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2715859757 |
|
|
Jun 22 04:46:30 PM PDT 24 |
Jun 22 04:46:32 PM PDT 24 |
56750432 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.766389287 |
|
|
Jun 22 04:46:08 PM PDT 24 |
Jun 22 04:46:10 PM PDT 24 |
49358569 ps |
| T956 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1986879545 |
|
|
Jun 22 04:46:23 PM PDT 24 |
Jun 22 04:46:26 PM PDT 24 |
135683350 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2583157961 |
|
|
Jun 22 04:46:25 PM PDT 24 |
Jun 22 04:46:27 PM PDT 24 |
46776615 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.905633019 |
|
|
Jun 22 04:46:09 PM PDT 24 |
Jun 22 04:46:13 PM PDT 24 |
165823396 ps |
| T959 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2683495195 |
|
|
Jun 22 04:46:30 PM PDT 24 |
Jun 22 04:46:34 PM PDT 24 |
129211168 ps |
| T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.746252577 |
|
|
Jun 22 04:46:24 PM PDT 24 |
Jun 22 04:46:25 PM PDT 24 |
36595387 ps |
| T961 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1626041302 |
|
|
Jun 22 04:46:32 PM PDT 24 |
Jun 22 04:46:35 PM PDT 24 |
129840669 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4212411589 |
|
|
Jun 22 04:46:08 PM PDT 24 |
Jun 22 04:46:10 PM PDT 24 |
44317690 ps |
| T963 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2299559321 |
|
|
Jun 22 04:46:30 PM PDT 24 |
Jun 22 04:46:31 PM PDT 24 |
34650108 ps |
| T128 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1566592588 |
|
|
Jun 22 04:46:10 PM PDT 24 |
Jun 22 04:46:13 PM PDT 24 |
336904434 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.290191546 |
|
|
Jun 22 04:46:05 PM PDT 24 |
Jun 22 04:46:07 PM PDT 24 |
34562861 ps |
| T121 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2239004412 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:22 PM PDT 24 |
200653845 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1130491541 |
|
|
Jun 22 04:46:10 PM PDT 24 |
Jun 22 04:46:12 PM PDT 24 |
24519975 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3392632304 |
|
|
Jun 22 04:46:18 PM PDT 24 |
Jun 22 04:46:20 PM PDT 24 |
42944150 ps |
| T967 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.441470887 |
|
|
Jun 22 04:46:29 PM PDT 24 |
Jun 22 04:46:30 PM PDT 24 |
14457079 ps |
| T968 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.539733747 |
|
|
Jun 22 04:46:31 PM PDT 24 |
Jun 22 04:46:35 PM PDT 24 |
392077279 ps |
| T969 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2593614999 |
|
|
Jun 22 04:46:39 PM PDT 24 |
Jun 22 04:46:40 PM PDT 24 |
52355410 ps |
| T970 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3614652269 |
|
|
Jun 22 04:46:40 PM PDT 24 |
Jun 22 04:46:41 PM PDT 24 |
39389992 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.13938797 |
|
|
Jun 22 04:46:05 PM PDT 24 |
Jun 22 04:46:10 PM PDT 24 |
519654875 ps |
| T972 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1860115616 |
|
|
Jun 22 04:46:37 PM PDT 24 |
Jun 22 04:46:41 PM PDT 24 |
153762484 ps |
| T973 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2227207919 |
|
|
Jun 22 04:46:39 PM PDT 24 |
Jun 22 04:46:42 PM PDT 24 |
414107605 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2682312967 |
|
|
Jun 22 04:46:10 PM PDT 24 |
Jun 22 04:46:12 PM PDT 24 |
12987229 ps |
| T975 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2535466035 |
|
|
Jun 22 04:46:11 PM PDT 24 |
Jun 22 04:46:13 PM PDT 24 |
28868343 ps |
| T976 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.713162305 |
|
|
Jun 22 04:46:26 PM PDT 24 |
Jun 22 04:46:27 PM PDT 24 |
36392903 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1253391800 |
|
|
Jun 22 04:46:26 PM PDT 24 |
Jun 22 04:46:28 PM PDT 24 |
296374468 ps |
| T93 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1565914471 |
|
|
Jun 22 04:46:25 PM PDT 24 |
Jun 22 04:46:28 PM PDT 24 |
411735212 ps |
| T122 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1517337259 |
|
|
Jun 22 04:46:33 PM PDT 24 |
Jun 22 04:46:36 PM PDT 24 |
855775964 ps |
| T123 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2367036878 |
|
|
Jun 22 04:46:03 PM PDT 24 |
Jun 22 04:46:05 PM PDT 24 |
321039252 ps |
| T978 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2960012885 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:21 PM PDT 24 |
33124889 ps |
| T127 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2572052520 |
|
|
Jun 22 04:46:13 PM PDT 24 |
Jun 22 04:46:16 PM PDT 24 |
650705499 ps |
| T979 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2380461882 |
|
|
Jun 22 04:46:30 PM PDT 24 |
Jun 22 04:46:32 PM PDT 24 |
240200300 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1112239381 |
|
|
Jun 22 04:46:09 PM PDT 24 |
Jun 22 04:46:12 PM PDT 24 |
38087276 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.240973612 |
|
|
Jun 22 04:46:12 PM PDT 24 |
Jun 22 04:46:13 PM PDT 24 |
47487194 ps |
| T982 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3507259273 |
|
|
Jun 22 04:46:25 PM PDT 24 |
Jun 22 04:46:26 PM PDT 24 |
39134448 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4115836053 |
|
|
Jun 22 04:46:31 PM PDT 24 |
Jun 22 04:46:34 PM PDT 24 |
62094795 ps |
| T984 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.12124172 |
|
|
Jun 22 04:46:31 PM PDT 24 |
Jun 22 04:46:35 PM PDT 24 |
1706737001 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3927144434 |
|
|
Jun 22 04:46:13 PM PDT 24 |
Jun 22 04:46:16 PM PDT 24 |
2945961239 ps |
| T986 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3107174131 |
|
|
Jun 22 04:46:30 PM PDT 24 |
Jun 22 04:46:31 PM PDT 24 |
22773249 ps |
| T987 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.828865274 |
|
|
Jun 22 04:46:19 PM PDT 24 |
Jun 22 04:46:24 PM PDT 24 |
126115875 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3194910783 |
|
|
Jun 22 04:46:15 PM PDT 24 |
Jun 22 04:46:17 PM PDT 24 |
63767878 ps |
| T989 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1756177666 |
|
|
Jun 22 04:46:10 PM PDT 24 |
Jun 22 04:46:13 PM PDT 24 |
147624405 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1589220462 |
|
|
Jun 22 04:46:15 PM PDT 24 |
Jun 22 04:46:17 PM PDT 24 |
45856607 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3129196572 |
|
|
Jun 22 04:46:31 PM PDT 24 |
Jun 22 04:46:33 PM PDT 24 |
152602776 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.367020893 |
|
|
Jun 22 04:46:23 PM PDT 24 |
Jun 22 04:46:25 PM PDT 24 |
15802779 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3043793576 |
|
|
Jun 22 04:46:24 PM PDT 24 |
Jun 22 04:46:27 PM PDT 24 |
60459085 ps |
| T994 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4004117719 |
|
|
Jun 22 04:46:18 PM PDT 24 |
Jun 22 04:46:19 PM PDT 24 |
19932647 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3890436926 |
|
|
Jun 22 04:46:04 PM PDT 24 |
Jun 22 04:46:08 PM PDT 24 |
54058128 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.127839202 |
|
|
Jun 22 04:46:14 PM PDT 24 |
Jun 22 04:46:16 PM PDT 24 |
129095379 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1751564608 |
|
|
Jun 22 04:46:29 PM PDT 24 |
Jun 22 04:46:30 PM PDT 24 |
32968920 ps |
| T998 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4184074751 |
|
|
Jun 22 04:46:24 PM PDT 24 |
Jun 22 04:46:29 PM PDT 24 |
272388256 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2948170600 |
|
|
Jun 22 04:46:38 PM PDT 24 |
Jun 22 04:46:40 PM PDT 24 |
233316001 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2527291151 |
|
|
Jun 22 04:46:25 PM PDT 24 |
Jun 22 04:46:27 PM PDT 24 |
54783450 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.27693999 |
|
|
Jun 22 04:46:11 PM PDT 24 |
Jun 22 04:46:13 PM PDT 24 |
101023831 ps |