Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145365494	1			T1	2038		T3	362222		T5	36864
instr_valid_dis	113029909	1			T1	2038		T3	362222		T5	36864
instr_en	25085934	1			T10	368520		T8	108088		T23	329676

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11038897	1			T10	141374		T8	145488		T23	102906
sram_ifetch_valid_disable	112960404	1			T1	2038		T3	362222		T5	36864
sram_ifetch_enable	21366193	1			T10	15016		T8	231674		T23	220710

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145365494	1			T1	2038		T3	362222		T5	36864
hw_debug_en_valid_off	112942632	1			T1	2038		T3	362222		T5	36864
hw_debug_en_on	21080050	1			T10	92662		T8	189568		T23	129138

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	112960404	1			T1	2038		T3	362222		T5	36864
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99838522	1			T1	2038		T3	362222		T5	36864
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10301682	1			T10	212130		T8	71262		T23	173692
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4869623	1			T10	42536		T8	104494		T9	13670
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1790132	1			T8	82740		T82	18688		T19	18702
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2201546	1			T10	42536		T8	21754		T19	22950
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4302480	1			T8	17472		T9	127312		T19	96188
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1763098	1			T8	16734		T19	34894		T132	29920
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2169856	1			T8	738		T19	41808		T67	43740
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8444038	1			T10	92662		T8	111876		T23	35128
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3339298	1			T8	60614		T23	35128		T9	58644
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3943306	1			T10	92662		T8	51262		T82	4044

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9635800	1			T10	15016		T8	14334		T23	129552
lc_exec_en	8333532	1			T8	60220		T23	94010		T18	2428
valid_exec_dis	108672451	1			T1	2038		T3	362222		T5	36864
invalid_exec_dis	32405090	1			T10	156390		T8	377162		T23	323616