Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43322192	1			T1	48		T3	32968		T5	18432
triple_byte_access	2477910	1			T1	132		T3	29520		T4	180
halfword_access	3722901	1			T1	231		T3	44534		T4	284
byte_access	4970936	1			T1	422		T3	59165		T4	371
zero_access	1251486	1			T1	186		T3	14924		T4	95

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27816631

1

T1

400

T3

90820

T5

9216

auto[1]

27928794

1

T1

619

T3

90291

T5

9216

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21609061	1			T1	3		T3	16461		T5	9216
auto[0]	triple_byte_access	1235718	1			T1	15		T3	14920		T4	85
auto[0]	halfword_access	1859218	1			T1	57		T3	22380		T4	139
auto[0]	byte_access	2482968	1			T1	186		T3	29599		T4	199
auto[0]	zero_access	629666	1			T1	139		T3	7460		T4	53
auto[1]	word_access	21713131	1			T1	45		T3	16507		T5	9216
auto[1]	triple_byte_access	1242192	1			T1	117		T3	14600		T4	95
auto[1]	halfword_access	1863683	1			T1	174		T3	22154		T4	145
auto[1]	byte_access	2487968	1			T1	236		T3	29566		T4	172
auto[1]	zero_access	621820	1			T1	47		T3	7464		T4	42