| T798 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1618215918 |
|
|
Jun 24 05:46:33 PM PDT 24 |
Jun 24 05:49:31 PM PDT 24 |
7144687189 ps |
| T799 |
/workspace/coverage/default/6.sram_ctrl_alert_test.201204657 |
|
|
Jun 24 05:45:27 PM PDT 24 |
Jun 24 05:45:30 PM PDT 24 |
38351650 ps |
| T800 |
/workspace/coverage/default/40.sram_ctrl_alert_test.2131458514 |
|
|
Jun 24 05:47:23 PM PDT 24 |
Jun 24 05:47:25 PM PDT 24 |
25244116 ps |
| T801 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2985802084 |
|
|
Jun 24 05:47:32 PM PDT 24 |
Jun 24 05:57:34 PM PDT 24 |
4203914555 ps |
| T802 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.2241353871 |
|
|
Jun 24 05:45:37 PM PDT 24 |
Jun 24 05:45:47 PM PDT 24 |
255506080 ps |
| T803 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2913804771 |
|
|
Jun 24 05:47:34 PM PDT 24 |
Jun 24 05:47:55 PM PDT 24 |
2320589572 ps |
| T804 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.247963699 |
|
|
Jun 24 05:45:09 PM PDT 24 |
Jun 24 05:46:47 PM PDT 24 |
533148066 ps |
| T805 |
/workspace/coverage/default/48.sram_ctrl_smoke.3191461851 |
|
|
Jun 24 05:48:09 PM PDT 24 |
Jun 24 05:48:51 PM PDT 24 |
97887258 ps |
| T806 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.62015455 |
|
|
Jun 24 05:45:36 PM PDT 24 |
Jun 24 05:45:39 PM PDT 24 |
83929333 ps |
| T807 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3543107111 |
|
|
Jun 24 05:46:34 PM PDT 24 |
Jun 24 05:53:53 PM PDT 24 |
2050735532 ps |
| T808 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.757072335 |
|
|
Jun 24 05:45:55 PM PDT 24 |
Jun 24 05:46:07 PM PDT 24 |
357196430 ps |
| T809 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.230871279 |
|
|
Jun 24 05:46:11 PM PDT 24 |
Jun 24 05:46:32 PM PDT 24 |
537792013 ps |
| T810 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.4109805279 |
|
|
Jun 24 05:45:19 PM PDT 24 |
Jun 24 05:50:28 PM PDT 24 |
25840708871 ps |
| T811 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.4175634790 |
|
|
Jun 24 05:45:46 PM PDT 24 |
Jun 24 05:45:52 PM PDT 24 |
694296953 ps |
| T812 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1655318035 |
|
|
Jun 24 05:45:50 PM PDT 24 |
Jun 24 05:49:01 PM PDT 24 |
38357272854 ps |
| T813 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2900862520 |
|
|
Jun 24 05:45:40 PM PDT 24 |
Jun 24 05:45:42 PM PDT 24 |
76394262 ps |
| T814 |
/workspace/coverage/default/45.sram_ctrl_bijection.2152561208 |
|
|
Jun 24 05:47:54 PM PDT 24 |
Jun 24 05:48:13 PM PDT 24 |
275325473 ps |
| T815 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.1955193848 |
|
|
Jun 24 05:46:06 PM PDT 24 |
Jun 24 05:46:14 PM PDT 24 |
947189306 ps |
| T816 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.702179230 |
|
|
Jun 24 05:47:25 PM PDT 24 |
Jun 24 05:51:19 PM PDT 24 |
3111315254 ps |
| T817 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2078000226 |
|
|
Jun 24 05:46:20 PM PDT 24 |
Jun 24 05:59:40 PM PDT 24 |
3316240302 ps |
| T818 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3875392630 |
|
|
Jun 24 05:46:18 PM PDT 24 |
Jun 24 05:50:57 PM PDT 24 |
1729258697 ps |
| T819 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1306244771 |
|
|
Jun 24 05:45:27 PM PDT 24 |
Jun 24 05:45:32 PM PDT 24 |
58981152 ps |
| T820 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2250236856 |
|
|
Jun 24 05:46:03 PM PDT 24 |
Jun 24 05:46:07 PM PDT 24 |
57787757 ps |
| T821 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3213600366 |
|
|
Jun 24 05:46:39 PM PDT 24 |
Jun 24 05:46:49 PM PDT 24 |
270034586 ps |
| T822 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3126893747 |
|
|
Jun 24 05:45:29 PM PDT 24 |
Jun 24 06:00:03 PM PDT 24 |
2963321911 ps |
| T823 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1742144696 |
|
|
Jun 24 05:45:21 PM PDT 24 |
Jun 24 05:46:34 PM PDT 24 |
1469146118 ps |
| T824 |
/workspace/coverage/default/3.sram_ctrl_executable.3216072901 |
|
|
Jun 24 05:45:09 PM PDT 24 |
Jun 24 05:56:25 PM PDT 24 |
17353071740 ps |
| T825 |
/workspace/coverage/default/2.sram_ctrl_alert_test.813112795 |
|
|
Jun 24 05:45:17 PM PDT 24 |
Jun 24 05:45:24 PM PDT 24 |
17712696 ps |
| T826 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.3202084554 |
|
|
Jun 24 05:46:16 PM PDT 24 |
Jun 24 05:47:06 PM PDT 24 |
230677067 ps |
| T827 |
/workspace/coverage/default/36.sram_ctrl_regwen.2610397513 |
|
|
Jun 24 05:47:03 PM PDT 24 |
Jun 24 05:53:39 PM PDT 24 |
1147492996 ps |
| T828 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3104952415 |
|
|
Jun 24 05:46:24 PM PDT 24 |
Jun 24 05:46:26 PM PDT 24 |
86170732 ps |
| T829 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3566588278 |
|
|
Jun 24 05:45:33 PM PDT 24 |
Jun 24 05:45:37 PM PDT 24 |
44289569 ps |
| T830 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1410397058 |
|
|
Jun 24 05:48:16 PM PDT 24 |
Jun 24 06:08:27 PM PDT 24 |
46887759337 ps |
| T831 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2418875829 |
|
|
Jun 24 05:45:47 PM PDT 24 |
Jun 24 05:46:07 PM PDT 24 |
102167806 ps |
| T832 |
/workspace/coverage/default/20.sram_ctrl_regwen.1241503240 |
|
|
Jun 24 05:46:10 PM PDT 24 |
Jun 24 05:51:38 PM PDT 24 |
5199350993 ps |
| T833 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.577952776 |
|
|
Jun 24 05:45:33 PM PDT 24 |
Jun 24 05:45:36 PM PDT 24 |
338312562 ps |
| T834 |
/workspace/coverage/default/0.sram_ctrl_executable.523292138 |
|
|
Jun 24 05:45:22 PM PDT 24 |
Jun 24 05:48:43 PM PDT 24 |
5401073935 ps |
| T835 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.4257173827 |
|
|
Jun 24 05:46:42 PM PDT 24 |
Jun 24 05:52:38 PM PDT 24 |
50606318108 ps |
| T836 |
/workspace/coverage/default/7.sram_ctrl_bijection.2291097766 |
|
|
Jun 24 05:45:24 PM PDT 24 |
Jun 24 05:45:57 PM PDT 24 |
1392286384 ps |
| T837 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.672871192 |
|
|
Jun 24 05:45:44 PM PDT 24 |
Jun 24 05:45:50 PM PDT 24 |
178911921 ps |
| T838 |
/workspace/coverage/default/0.sram_ctrl_smoke.2050348353 |
|
|
Jun 24 05:45:06 PM PDT 24 |
Jun 24 05:45:20 PM PDT 24 |
1063953672 ps |
| T839 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1589853994 |
|
|
Jun 24 05:46:00 PM PDT 24 |
Jun 24 05:46:10 PM PDT 24 |
1393835605 ps |
| T840 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3378831023 |
|
|
Jun 24 05:47:41 PM PDT 24 |
Jun 24 05:49:22 PM PDT 24 |
2025666746 ps |
| T841 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2359999785 |
|
|
Jun 24 05:46:16 PM PDT 24 |
Jun 24 05:52:13 PM PDT 24 |
5222797106 ps |
| T842 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3672821992 |
|
|
Jun 24 05:45:23 PM PDT 24 |
Jun 24 05:46:18 PM PDT 24 |
3712680796 ps |
| T843 |
/workspace/coverage/default/16.sram_ctrl_smoke.3906145949 |
|
|
Jun 24 05:45:51 PM PDT 24 |
Jun 24 05:46:06 PM PDT 24 |
1282356563 ps |
| T844 |
/workspace/coverage/default/49.sram_ctrl_alert_test.3211642914 |
|
|
Jun 24 05:48:24 PM PDT 24 |
Jun 24 05:48:26 PM PDT 24 |
15074147 ps |
| T845 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.358537224 |
|
|
Jun 24 05:46:27 PM PDT 24 |
Jun 24 05:50:53 PM PDT 24 |
6872034445 ps |
| T846 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2424613032 |
|
|
Jun 24 05:45:10 PM PDT 24 |
Jun 24 05:51:35 PM PDT 24 |
6400842401 ps |
| T847 |
/workspace/coverage/default/32.sram_ctrl_bijection.862025933 |
|
|
Jun 24 05:46:37 PM PDT 24 |
Jun 24 05:47:23 PM PDT 24 |
1646155125 ps |
| T848 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3723136859 |
|
|
Jun 24 05:46:54 PM PDT 24 |
Jun 24 05:47:13 PM PDT 24 |
502509500 ps |
| T849 |
/workspace/coverage/default/0.sram_ctrl_alert_test.946791988 |
|
|
Jun 24 05:45:18 PM PDT 24 |
Jun 24 05:45:19 PM PDT 24 |
51165909 ps |
| T850 |
/workspace/coverage/default/45.sram_ctrl_executable.3451254014 |
|
|
Jun 24 05:47:50 PM PDT 24 |
Jun 24 05:56:22 PM PDT 24 |
34592592951 ps |
| T851 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.1149398719 |
|
|
Jun 24 05:45:49 PM PDT 24 |
Jun 24 05:45:53 PM PDT 24 |
53399381 ps |
| T852 |
/workspace/coverage/default/21.sram_ctrl_stress_all.2869959853 |
|
|
Jun 24 05:45:59 PM PDT 24 |
Jun 24 06:28:20 PM PDT 24 |
48586227799 ps |
| T853 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.49735163 |
|
|
Jun 24 05:47:05 PM PDT 24 |
Jun 24 06:02:22 PM PDT 24 |
20059987270 ps |
| T854 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3422159841 |
|
|
Jun 24 05:45:49 PM PDT 24 |
Jun 24 05:47:22 PM PDT 24 |
139620205 ps |
| T855 |
/workspace/coverage/default/2.sram_ctrl_bijection.3500302392 |
|
|
Jun 24 05:45:12 PM PDT 24 |
Jun 24 05:45:50 PM PDT 24 |
3224456557 ps |
| T856 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.17023881 |
|
|
Jun 24 05:47:02 PM PDT 24 |
Jun 24 05:47:58 PM PDT 24 |
387563350 ps |
| T857 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2411314270 |
|
|
Jun 24 05:46:12 PM PDT 24 |
Jun 24 06:11:17 PM PDT 24 |
7902310096 ps |
| T858 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.510404557 |
|
|
Jun 24 05:45:10 PM PDT 24 |
Jun 24 05:45:44 PM PDT 24 |
2228739857 ps |
| T859 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.1406625419 |
|
|
Jun 24 05:47:22 PM PDT 24 |
Jun 24 05:47:35 PM PDT 24 |
183422490 ps |
| T860 |
/workspace/coverage/default/24.sram_ctrl_smoke.980678478 |
|
|
Jun 24 05:46:02 PM PDT 24 |
Jun 24 05:46:22 PM PDT 24 |
1163162694 ps |
| T861 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3369006090 |
|
|
Jun 24 05:47:13 PM PDT 24 |
Jun 24 05:53:09 PM PDT 24 |
2370097347 ps |
| T862 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2421556756 |
|
|
Jun 24 05:46:20 PM PDT 24 |
Jun 24 05:46:26 PM PDT 24 |
67417977 ps |
| T863 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2755514010 |
|
|
Jun 24 05:48:00 PM PDT 24 |
Jun 24 05:50:32 PM PDT 24 |
1612770864 ps |
| T864 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.3593680396 |
|
|
Jun 24 05:46:14 PM PDT 24 |
Jun 24 05:46:22 PM PDT 24 |
2111001306 ps |
| T865 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1229704199 |
|
|
Jun 24 05:48:17 PM PDT 24 |
Jun 24 05:48:20 PM PDT 24 |
59048456 ps |
| T866 |
/workspace/coverage/default/42.sram_ctrl_bijection.1302002557 |
|
|
Jun 24 05:47:33 PM PDT 24 |
Jun 24 05:48:18 PM PDT 24 |
1276617572 ps |
| T867 |
/workspace/coverage/default/34.sram_ctrl_executable.1287744290 |
|
|
Jun 24 05:46:52 PM PDT 24 |
Jun 24 05:51:38 PM PDT 24 |
27943826720 ps |
| T868 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3230560436 |
|
|
Jun 24 05:46:51 PM PDT 24 |
Jun 24 05:49:44 PM PDT 24 |
4705057248 ps |
| T869 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3492434705 |
|
|
Jun 24 05:46:14 PM PDT 24 |
Jun 24 05:48:08 PM PDT 24 |
561193498 ps |
| T870 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.2044486603 |
|
|
Jun 24 05:48:07 PM PDT 24 |
Jun 24 05:50:33 PM PDT 24 |
274282069 ps |
| T871 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.4154324337 |
|
|
Jun 24 05:45:06 PM PDT 24 |
Jun 24 05:46:37 PM PDT 24 |
414812499 ps |
| T872 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2751975443 |
|
|
Jun 24 05:45:12 PM PDT 24 |
Jun 24 06:03:38 PM PDT 24 |
5448064861 ps |
| T873 |
/workspace/coverage/default/8.sram_ctrl_partial_access.2369260537 |
|
|
Jun 24 05:45:33 PM PDT 24 |
Jun 24 05:45:48 PM PDT 24 |
10450920774 ps |
| T874 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.249122051 |
|
|
Jun 24 05:47:42 PM PDT 24 |
Jun 24 05:58:22 PM PDT 24 |
16761412625 ps |
| T875 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1609279493 |
|
|
Jun 24 05:46:20 PM PDT 24 |
Jun 24 05:49:49 PM PDT 24 |
4348489451 ps |
| T876 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2763617959 |
|
|
Jun 24 05:45:37 PM PDT 24 |
Jun 24 05:57:13 PM PDT 24 |
24328002205 ps |
| T877 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.299502880 |
|
|
Jun 24 05:45:32 PM PDT 24 |
Jun 24 05:45:39 PM PDT 24 |
342686034 ps |
| T878 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.1578833533 |
|
|
Jun 24 05:46:09 PM PDT 24 |
Jun 24 05:46:19 PM PDT 24 |
137470831 ps |
| T879 |
/workspace/coverage/default/38.sram_ctrl_smoke.1421594284 |
|
|
Jun 24 05:47:06 PM PDT 24 |
Jun 24 05:47:18 PM PDT 24 |
296527834 ps |
| T880 |
/workspace/coverage/default/19.sram_ctrl_regwen.75352246 |
|
|
Jun 24 05:45:59 PM PDT 24 |
Jun 24 05:57:40 PM PDT 24 |
12469486435 ps |
| T881 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1577915832 |
|
|
Jun 24 05:45:55 PM PDT 24 |
Jun 24 05:45:59 PM PDT 24 |
199489839 ps |
| T882 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2287938045 |
|
|
Jun 24 05:48:18 PM PDT 24 |
Jun 24 05:48:23 PM PDT 24 |
93113542 ps |
| T883 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.225788913 |
|
|
Jun 24 05:45:53 PM PDT 24 |
Jun 24 05:47:39 PM PDT 24 |
668281649 ps |
| T884 |
/workspace/coverage/default/10.sram_ctrl_alert_test.3279018488 |
|
|
Jun 24 05:45:47 PM PDT 24 |
Jun 24 05:45:48 PM PDT 24 |
96647760 ps |
| T885 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2631402500 |
|
|
Jun 24 05:45:23 PM PDT 24 |
Jun 24 05:45:28 PM PDT 24 |
59875793 ps |
| T886 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2264964384 |
|
|
Jun 24 05:45:21 PM PDT 24 |
Jun 24 05:45:23 PM PDT 24 |
86177745 ps |
| T887 |
/workspace/coverage/default/12.sram_ctrl_alert_test.533089461 |
|
|
Jun 24 05:45:39 PM PDT 24 |
Jun 24 05:45:41 PM PDT 24 |
16160770 ps |
| T888 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.129969451 |
|
|
Jun 24 05:47:03 PM PDT 24 |
Jun 24 05:50:21 PM PDT 24 |
2063122273 ps |
| T889 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3097011920 |
|
|
Jun 24 05:45:26 PM PDT 24 |
Jun 24 05:59:44 PM PDT 24 |
2424442391 ps |
| T890 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3115673950 |
|
|
Jun 24 05:47:54 PM PDT 24 |
Jun 24 05:50:52 PM PDT 24 |
16430938297 ps |
| T891 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.514256763 |
|
|
Jun 24 05:46:23 PM PDT 24 |
Jun 24 05:50:19 PM PDT 24 |
3369495213 ps |
| T892 |
/workspace/coverage/default/13.sram_ctrl_executable.3264577819 |
|
|
Jun 24 05:45:35 PM PDT 24 |
Jun 24 05:57:42 PM PDT 24 |
31372139621 ps |
| T893 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3464900463 |
|
|
Jun 24 05:45:33 PM PDT 24 |
Jun 24 06:02:40 PM PDT 24 |
2756907260 ps |
| T894 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.1399728180 |
|
|
Jun 24 05:47:25 PM PDT 24 |
Jun 24 05:47:29 PM PDT 24 |
118978753 ps |
| T895 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1461228981 |
|
|
Jun 24 05:47:02 PM PDT 24 |
Jun 24 06:35:28 PM PDT 24 |
38439635248 ps |
| T896 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3929688376 |
|
|
Jun 24 05:45:57 PM PDT 24 |
Jun 24 05:46:01 PM PDT 24 |
29198593 ps |
| T897 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1284185626 |
|
|
Jun 24 05:48:09 PM PDT 24 |
Jun 24 05:49:08 PM PDT 24 |
215922163 ps |
| T898 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.732820959 |
|
|
Jun 24 05:47:19 PM PDT 24 |
Jun 24 05:47:26 PM PDT 24 |
898051681 ps |
| T899 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.1763641906 |
|
|
Jun 24 05:46:26 PM PDT 24 |
Jun 24 05:46:37 PM PDT 24 |
4567913005 ps |
| T900 |
/workspace/coverage/default/1.sram_ctrl_stress_all.3529021890 |
|
|
Jun 24 05:45:21 PM PDT 24 |
Jun 24 06:07:51 PM PDT 24 |
58258818662 ps |
| T901 |
/workspace/coverage/default/26.sram_ctrl_executable.1360292287 |
|
|
Jun 24 05:46:21 PM PDT 24 |
Jun 24 05:58:22 PM PDT 24 |
2246636324 ps |
| T902 |
/workspace/coverage/default/22.sram_ctrl_smoke.3112035760 |
|
|
Jun 24 05:46:06 PM PDT 24 |
Jun 24 05:48:48 PM PDT 24 |
145636904 ps |
| T903 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.409507542 |
|
|
Jun 24 05:47:23 PM PDT 24 |
Jun 24 05:47:27 PM PDT 24 |
46990233 ps |
| T904 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4094166743 |
|
|
Jun 24 05:46:22 PM PDT 24 |
Jun 24 05:46:41 PM PDT 24 |
84731327 ps |
| T905 |
/workspace/coverage/default/44.sram_ctrl_regwen.1403186643 |
|
|
Jun 24 05:47:43 PM PDT 24 |
Jun 24 06:13:21 PM PDT 24 |
13687299556 ps |
| T906 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1269898917 |
|
|
Jun 24 05:46:13 PM PDT 24 |
Jun 24 05:46:27 PM PDT 24 |
654101096 ps |
| T907 |
/workspace/coverage/default/30.sram_ctrl_regwen.2867190674 |
|
|
Jun 24 05:46:34 PM PDT 24 |
Jun 24 05:51:29 PM PDT 24 |
6674860581 ps |
| T908 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2104001658 |
|
|
Jun 24 05:47:02 PM PDT 24 |
Jun 24 05:48:46 PM PDT 24 |
1052987214 ps |
| T909 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2160256913 |
|
|
Jun 24 05:47:05 PM PDT 24 |
Jun 24 05:47:43 PM PDT 24 |
902209802 ps |
| T910 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.3257779750 |
|
|
Jun 24 05:45:59 PM PDT 24 |
Jun 24 05:46:13 PM PDT 24 |
64348895 ps |
| T911 |
/workspace/coverage/default/46.sram_ctrl_smoke.4238003761 |
|
|
Jun 24 05:47:54 PM PDT 24 |
Jun 24 05:48:11 PM PDT 24 |
245830661 ps |
| T912 |
/workspace/coverage/default/17.sram_ctrl_regwen.752453376 |
|
|
Jun 24 05:45:57 PM PDT 24 |
Jun 24 06:00:28 PM PDT 24 |
5613955119 ps |
| T913 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2606081840 |
|
|
Jun 24 05:46:52 PM PDT 24 |
Jun 24 05:46:56 PM PDT 24 |
44932587 ps |
| T914 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.633605183 |
|
|
Jun 24 05:45:28 PM PDT 24 |
Jun 24 05:45:38 PM PDT 24 |
279234273 ps |
| T915 |
/workspace/coverage/default/35.sram_ctrl_smoke.265489300 |
|
|
Jun 24 05:46:53 PM PDT 24 |
Jun 24 05:47:13 PM PDT 24 |
5211718199 ps |
| T916 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2980492951 |
|
|
Jun 24 05:45:33 PM PDT 24 |
Jun 24 05:50:16 PM PDT 24 |
11380339210 ps |
| T917 |
/workspace/coverage/default/0.sram_ctrl_regwen.1748664154 |
|
|
Jun 24 05:45:06 PM PDT 24 |
Jun 24 05:56:17 PM PDT 24 |
1926009642 ps |
| T918 |
/workspace/coverage/default/27.sram_ctrl_bijection.437402206 |
|
|
Jun 24 05:46:18 PM PDT 24 |
Jun 24 05:47:32 PM PDT 24 |
3349296172 ps |
| T919 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.664754374 |
|
|
Jun 24 05:47:53 PM PDT 24 |
Jun 24 05:48:00 PM PDT 24 |
222349722 ps |
| T920 |
/workspace/coverage/default/45.sram_ctrl_partial_access.647099349 |
|
|
Jun 24 05:47:50 PM PDT 24 |
Jun 24 05:47:57 PM PDT 24 |
346753936 ps |
| T921 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2387399767 |
|
|
Jun 24 05:46:06 PM PDT 24 |
Jun 24 05:51:37 PM PDT 24 |
3784223903 ps |
| T922 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3732436947 |
|
|
Jun 24 05:45:30 PM PDT 24 |
Jun 24 05:50:47 PM PDT 24 |
12062222087 ps |
| T923 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1845474311 |
|
|
Jun 24 05:45:54 PM PDT 24 |
Jun 24 05:48:01 PM PDT 24 |
545479733 ps |
| T924 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2564042812 |
|
|
Jun 24 05:47:21 PM PDT 24 |
Jun 24 06:11:58 PM PDT 24 |
62836920519 ps |
| T925 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3264126461 |
|
|
Jun 24 05:45:49 PM PDT 24 |
Jun 24 06:29:39 PM PDT 24 |
10139874981 ps |
| T926 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.139873770 |
|
|
Jun 24 05:45:21 PM PDT 24 |
Jun 24 05:46:48 PM PDT 24 |
477501247 ps |
| T927 |
/workspace/coverage/default/12.sram_ctrl_partial_access.4018204979 |
|
|
Jun 24 05:45:40 PM PDT 24 |
Jun 24 05:45:43 PM PDT 24 |
151082565 ps |
| T928 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1689409242 |
|
|
Jun 24 05:46:26 PM PDT 24 |
Jun 24 05:46:39 PM PDT 24 |
71960787 ps |
| T929 |
/workspace/coverage/default/10.sram_ctrl_smoke.3745666610 |
|
|
Jun 24 05:45:41 PM PDT 24 |
Jun 24 05:46:02 PM PDT 24 |
417022890 ps |
| T930 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.2753222487 |
|
|
Jun 24 05:46:03 PM PDT 24 |
Jun 24 05:46:07 PM PDT 24 |
85808235 ps |
| T931 |
/workspace/coverage/default/49.sram_ctrl_stress_all.1541977522 |
|
|
Jun 24 05:48:28 PM PDT 24 |
Jun 24 06:46:36 PM PDT 24 |
38831149523 ps |
| T932 |
/workspace/coverage/default/40.sram_ctrl_smoke.696189146 |
|
|
Jun 24 05:47:12 PM PDT 24 |
Jun 24 05:47:31 PM PDT 24 |
3093533848 ps |
| T933 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1909300129 |
|
|
Jun 24 05:45:26 PM PDT 24 |
Jun 24 05:45:31 PM PDT 24 |
191597903 ps |
| T934 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3629846812 |
|
|
Jun 24 05:45:31 PM PDT 24 |
Jun 24 05:56:12 PM PDT 24 |
2388819871 ps |
| T935 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1265698695 |
|
|
Jun 24 05:45:55 PM PDT 24 |
Jun 24 05:46:01 PM PDT 24 |
160038253 ps |
| T936 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.881369300 |
|
|
Jun 24 05:45:34 PM PDT 24 |
Jun 24 05:48:51 PM PDT 24 |
7656675702 ps |
| T937 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1530134759 |
|
|
Jun 24 05:46:33 PM PDT 24 |
Jun 24 05:46:36 PM PDT 24 |
29118295 ps |
| T938 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1087594645 |
|
|
Jun 24 05:47:26 PM PDT 24 |
Jun 24 05:47:33 PM PDT 24 |
1469854397 ps |
| T939 |
/workspace/coverage/default/13.sram_ctrl_partial_access.659994617 |
|
|
Jun 24 05:46:00 PM PDT 24 |
Jun 24 05:48:04 PM PDT 24 |
420546305 ps |
| T63 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2288174162 |
|
|
Jun 24 05:44:33 PM PDT 24 |
Jun 24 05:44:37 PM PDT 24 |
11563897 ps |
| T64 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3720158813 |
|
|
Jun 24 05:44:25 PM PDT 24 |
Jun 24 05:44:26 PM PDT 24 |
24703922 ps |
| T65 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2276264753 |
|
|
Jun 24 05:44:21 PM PDT 24 |
Jun 24 05:44:23 PM PDT 24 |
51769966 ps |
| T106 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2635573044 |
|
|
Jun 24 05:44:32 PM PDT 24 |
Jun 24 05:44:36 PM PDT 24 |
32825934 ps |
| T60 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1992419394 |
|
|
Jun 24 05:44:36 PM PDT 24 |
Jun 24 05:44:40 PM PDT 24 |
440145899 ps |
| T940 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1686396776 |
|
|
Jun 24 05:44:42 PM PDT 24 |
Jun 24 05:44:50 PM PDT 24 |
144527633 ps |
| T941 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2889161240 |
|
|
Jun 24 05:44:26 PM PDT 24 |
Jun 24 05:44:30 PM PDT 24 |
101279838 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.264355124 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:36 PM PDT 24 |
431103756 ps |
| T74 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1408838966 |
|
|
Jun 24 05:44:48 PM PDT 24 |
Jun 24 05:44:51 PM PDT 24 |
15073739 ps |
| T61 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2534065271 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:34 PM PDT 24 |
424798234 ps |
| T107 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.293954489 |
|
|
Jun 24 05:44:31 PM PDT 24 |
Jun 24 05:44:35 PM PDT 24 |
11581731 ps |
| T98 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.865449533 |
|
|
Jun 24 05:44:29 PM PDT 24 |
Jun 24 05:44:34 PM PDT 24 |
415163057 ps |
| T942 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.646945688 |
|
|
Jun 24 05:44:19 PM PDT 24 |
Jun 24 05:44:26 PM PDT 24 |
395916661 ps |
| T99 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2837349976 |
|
|
Jun 24 05:44:37 PM PDT 24 |
Jun 24 05:44:40 PM PDT 24 |
71987020 ps |
| T943 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1504311792 |
|
|
Jun 24 05:44:25 PM PDT 24 |
Jun 24 05:44:27 PM PDT 24 |
130200756 ps |
| T62 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1626173492 |
|
|
Jun 24 05:44:47 PM PDT 24 |
Jun 24 05:44:51 PM PDT 24 |
409925068 ps |
| T944 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2356610711 |
|
|
Jun 24 05:44:39 PM PDT 24 |
Jun 24 05:44:43 PM PDT 24 |
14887622 ps |
| T116 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2918452121 |
|
|
Jun 24 05:44:33 PM PDT 24 |
Jun 24 05:44:38 PM PDT 24 |
110808947 ps |
| T75 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3669025613 |
|
|
Jun 24 05:44:28 PM PDT 24 |
Jun 24 05:44:31 PM PDT 24 |
88057516 ps |
| T115 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2248553241 |
|
|
Jun 24 05:44:35 PM PDT 24 |
Jun 24 05:44:39 PM PDT 24 |
118636025 ps |
| T76 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.797560383 |
|
|
Jun 24 05:44:35 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
657101427 ps |
| T945 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2269023151 |
|
|
Jun 24 05:44:36 PM PDT 24 |
Jun 24 05:44:40 PM PDT 24 |
88614461 ps |
| T946 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3614510255 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:35 PM PDT 24 |
375560134 ps |
| T77 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1200178258 |
|
|
Jun 24 05:44:27 PM PDT 24 |
Jun 24 05:44:30 PM PDT 24 |
52471842 ps |
| T117 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1363947508 |
|
|
Jun 24 05:44:38 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
1411940143 ps |
| T118 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3874951165 |
|
|
Jun 24 05:44:37 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
228172491 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3174813413 |
|
|
Jun 24 05:44:23 PM PDT 24 |
Jun 24 05:44:28 PM PDT 24 |
1850738016 ps |
| T948 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2876879909 |
|
|
Jun 24 05:44:27 PM PDT 24 |
Jun 24 05:44:30 PM PDT 24 |
49794651 ps |
| T949 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.960479329 |
|
|
Jun 24 05:44:26 PM PDT 24 |
Jun 24 05:44:31 PM PDT 24 |
303248460 ps |
| T119 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3479116123 |
|
|
Jun 24 05:44:41 PM PDT 24 |
Jun 24 05:44:45 PM PDT 24 |
114132296 ps |
| T950 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3685974459 |
|
|
Jun 24 05:44:26 PM PDT 24 |
Jun 24 05:44:29 PM PDT 24 |
235422594 ps |
| T951 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1004859772 |
|
|
Jun 24 05:44:41 PM PDT 24 |
Jun 24 05:44:49 PM PDT 24 |
920033829 ps |
| T952 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2813716775 |
|
|
Jun 24 05:44:22 PM PDT 24 |
Jun 24 05:44:25 PM PDT 24 |
1369115292 ps |
| T953 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1048542713 |
|
|
Jun 24 05:44:29 PM PDT 24 |
Jun 24 05:44:32 PM PDT 24 |
33651654 ps |
| T128 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3724153744 |
|
|
Jun 24 05:44:36 PM PDT 24 |
Jun 24 05:44:40 PM PDT 24 |
81590387 ps |
| T120 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1789826934 |
|
|
Jun 24 05:44:26 PM PDT 24 |
Jun 24 05:44:30 PM PDT 24 |
581138357 ps |
| T954 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3776107372 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:35 PM PDT 24 |
38339410 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3754900394 |
|
|
Jun 24 05:44:22 PM PDT 24 |
Jun 24 05:44:27 PM PDT 24 |
139054689 ps |
| T956 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.153586408 |
|
|
Jun 24 05:44:37 PM PDT 24 |
Jun 24 05:44:41 PM PDT 24 |
44433508 ps |
| T100 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2751100899 |
|
|
Jun 24 05:44:29 PM PDT 24 |
Jun 24 05:44:32 PM PDT 24 |
32816488 ps |
| T957 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2824347684 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:38 PM PDT 24 |
547836136 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1836278607 |
|
|
Jun 24 05:44:35 PM PDT 24 |
Jun 24 05:44:38 PM PDT 24 |
15477109 ps |
| T101 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4042725529 |
|
|
Jun 24 05:44:47 PM PDT 24 |
Jun 24 05:44:50 PM PDT 24 |
16137126 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.736601096 |
|
|
Jun 24 05:44:34 PM PDT 24 |
Jun 24 05:44:38 PM PDT 24 |
282034622 ps |
| T78 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.73487422 |
|
|
Jun 24 05:44:40 PM PDT 24 |
Jun 24 05:44:47 PM PDT 24 |
767325831 ps |
| T129 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2780514167 |
|
|
Jun 24 05:44:25 PM PDT 24 |
Jun 24 05:44:28 PM PDT 24 |
323566974 ps |
| T79 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2711422044 |
|
|
Jun 24 05:44:33 PM PDT 24 |
Jun 24 05:44:36 PM PDT 24 |
46105784 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.482772711 |
|
|
Jun 24 05:44:51 PM PDT 24 |
Jun 24 05:44:54 PM PDT 24 |
33837180 ps |
| T126 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3028279472 |
|
|
Jun 24 05:44:29 PM PDT 24 |
Jun 24 05:44:34 PM PDT 24 |
354626934 ps |
| T961 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3516173064 |
|
|
Jun 24 05:44:48 PM PDT 24 |
Jun 24 05:44:52 PM PDT 24 |
308117354 ps |
| T962 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3948723763 |
|
|
Jun 24 05:44:34 PM PDT 24 |
Jun 24 05:44:37 PM PDT 24 |
20365650 ps |
| T80 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1829770770 |
|
|
Jun 24 05:44:39 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
12115989 ps |
| T963 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1279962315 |
|
|
Jun 24 05:44:33 PM PDT 24 |
Jun 24 05:44:38 PM PDT 24 |
39785890 ps |
| T83 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3022495475 |
|
|
Jun 24 05:44:38 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
506628410 ps |
| T964 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1125490394 |
|
|
Jun 24 05:44:37 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
620530066 ps |
| T84 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3127881793 |
|
|
Jun 24 05:44:19 PM PDT 24 |
Jun 24 05:44:23 PM PDT 24 |
528707837 ps |
| T965 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1586310010 |
|
|
Jun 24 05:44:25 PM PDT 24 |
Jun 24 05:44:28 PM PDT 24 |
2211871492 ps |
| T85 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2543240702 |
|
|
Jun 24 05:44:37 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
220732025 ps |
| T966 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2113150761 |
|
|
Jun 24 05:44:39 PM PDT 24 |
Jun 24 05:44:43 PM PDT 24 |
130259701 ps |
| T86 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1337431089 |
|
|
Jun 24 05:44:25 PM PDT 24 |
Jun 24 05:44:29 PM PDT 24 |
846762397 ps |
| T121 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.260270225 |
|
|
Jun 24 05:44:29 PM PDT 24 |
Jun 24 05:44:34 PM PDT 24 |
342855005 ps |
| T967 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3787911318 |
|
|
Jun 24 05:44:35 PM PDT 24 |
Jun 24 05:44:38 PM PDT 24 |
30125723 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2675663840 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:34 PM PDT 24 |
63230744 ps |
| T122 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3548687100 |
|
|
Jun 24 05:44:25 PM PDT 24 |
Jun 24 05:44:28 PM PDT 24 |
126857676 ps |
| T969 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2549040796 |
|
|
Jun 24 05:44:56 PM PDT 24 |
Jun 24 05:44:57 PM PDT 24 |
21896252 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3905204755 |
|
|
Jun 24 05:44:25 PM PDT 24 |
Jun 24 05:44:28 PM PDT 24 |
77060240 ps |
| T971 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.483372044 |
|
|
Jun 24 05:44:35 PM PDT 24 |
Jun 24 05:44:39 PM PDT 24 |
60244504 ps |
| T972 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3717812680 |
|
|
Jun 24 05:44:16 PM PDT 24 |
Jun 24 05:44:20 PM PDT 24 |
115559543 ps |
| T127 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2367081029 |
|
|
Jun 24 05:44:31 PM PDT 24 |
Jun 24 05:44:37 PM PDT 24 |
1304783610 ps |
| T91 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4129365858 |
|
|
Jun 24 05:44:15 PM PDT 24 |
Jun 24 05:44:19 PM PDT 24 |
50951901 ps |
| T973 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3753280269 |
|
|
Jun 24 05:44:34 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
522369067 ps |
| T90 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1082988217 |
|
|
Jun 24 05:44:33 PM PDT 24 |
Jun 24 05:44:39 PM PDT 24 |
4940124309 ps |
| T974 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1992493165 |
|
|
Jun 24 05:44:38 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
17302045 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.412705701 |
|
|
Jun 24 05:44:31 PM PDT 24 |
Jun 24 05:44:35 PM PDT 24 |
14452972 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1641924871 |
|
|
Jun 24 05:44:29 PM PDT 24 |
Jun 24 05:44:33 PM PDT 24 |
15367219 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1500173759 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:35 PM PDT 24 |
67125370 ps |
| T977 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.842720737 |
|
|
Jun 24 05:44:41 PM PDT 24 |
Jun 24 05:44:45 PM PDT 24 |
101875957 ps |
| T978 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1651813210 |
|
|
Jun 24 05:44:31 PM PDT 24 |
Jun 24 05:44:34 PM PDT 24 |
62623040 ps |
| T979 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2906462858 |
|
|
Jun 24 05:44:25 PM PDT 24 |
Jun 24 05:44:28 PM PDT 24 |
14782040 ps |
| T980 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4139942868 |
|
|
Jun 24 05:44:24 PM PDT 24 |
Jun 24 05:44:27 PM PDT 24 |
319664903 ps |
| T92 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3659959415 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:37 PM PDT 24 |
1729157280 ps |
| T981 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1686083175 |
|
|
Jun 24 05:44:43 PM PDT 24 |
Jun 24 05:44:51 PM PDT 24 |
600500975 ps |
| T123 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3442119420 |
|
|
Jun 24 05:44:31 PM PDT 24 |
Jun 24 05:44:36 PM PDT 24 |
209135306 ps |
| T982 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3966230992 |
|
|
Jun 24 05:44:36 PM PDT 24 |
Jun 24 05:44:39 PM PDT 24 |
106924399 ps |
| T983 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.113726483 |
|
|
Jun 24 05:44:39 PM PDT 24 |
Jun 24 05:44:43 PM PDT 24 |
222148100 ps |
| T93 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2653376477 |
|
|
Jun 24 05:44:25 PM PDT 24 |
Jun 24 05:44:30 PM PDT 24 |
789602835 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3141809810 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:37 PM PDT 24 |
43074382 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3306352127 |
|
|
Jun 24 05:44:14 PM PDT 24 |
Jun 24 05:44:18 PM PDT 24 |
1564303984 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1771153491 |
|
|
Jun 24 05:44:21 PM PDT 24 |
Jun 24 05:44:23 PM PDT 24 |
15488619 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1949761410 |
|
|
Jun 24 05:44:31 PM PDT 24 |
Jun 24 05:44:35 PM PDT 24 |
22179210 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1493801223 |
|
|
Jun 24 05:44:33 PM PDT 24 |
Jun 24 05:44:36 PM PDT 24 |
48082933 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3141728418 |
|
|
Jun 24 05:44:41 PM PDT 24 |
Jun 24 05:44:47 PM PDT 24 |
1046768783 ps |
| T97 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2962189889 |
|
|
Jun 24 05:44:31 PM PDT 24 |
Jun 24 05:44:37 PM PDT 24 |
1516048359 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.124109686 |
|
|
Jun 24 05:44:28 PM PDT 24 |
Jun 24 05:44:33 PM PDT 24 |
200056137 ps |
| T989 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4011649802 |
|
|
Jun 24 05:44:35 PM PDT 24 |
Jun 24 05:44:51 PM PDT 24 |
113459463 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.835348421 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:38 PM PDT 24 |
232664835 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4021817363 |
|
|
Jun 24 05:44:27 PM PDT 24 |
Jun 24 05:44:30 PM PDT 24 |
30237459 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.270775193 |
|
|
Jun 24 05:44:31 PM PDT 24 |
Jun 24 05:44:35 PM PDT 24 |
32549202 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1656250590 |
|
|
Jun 24 05:44:17 PM PDT 24 |
Jun 24 05:44:21 PM PDT 24 |
72060482 ps |
| T994 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.823602014 |
|
|
Jun 24 05:44:39 PM PDT 24 |
Jun 24 05:44:42 PM PDT 24 |
52334532 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2612187345 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:34 PM PDT 24 |
342750058 ps |
| T996 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1516157629 |
|
|
Jun 24 05:44:16 PM PDT 24 |
Jun 24 05:44:19 PM PDT 24 |
26104344 ps |
| T997 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2279754015 |
|
|
Jun 24 05:44:54 PM PDT 24 |
Jun 24 05:44:56 PM PDT 24 |
76191046 ps |
| T124 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.694945086 |
|
|
Jun 24 05:44:29 PM PDT 24 |
Jun 24 05:44:35 PM PDT 24 |
619280285 ps |
| T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3110468876 |
|
|
Jun 24 05:44:39 PM PDT 24 |
Jun 24 05:44:45 PM PDT 24 |
2319932242 ps |
| T999 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3172490850 |
|
|
Jun 24 05:44:16 PM PDT 24 |
Jun 24 05:44:19 PM PDT 24 |
22385197 ps |
| T1000 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2263747084 |
|
|
Jun 24 05:44:38 PM PDT 24 |
Jun 24 05:44:41 PM PDT 24 |
30878335 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2864828831 |
|
|
Jun 24 05:44:30 PM PDT 24 |
Jun 24 05:44:34 PM PDT 24 |
55806494 ps |