Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	150393268	1			T1	261764		T2	315782		T3	12284
instr_valid_dis	118613039	1			T1	261764		T3	12284		T8	61440
instr_en	22314075	1			T2	315782		T24	102928		T20	21150

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11564478	1			T2	74874		T12	116598		T24	142366
sram_ifetch_valid_disable	115991498	1			T1	261764		T2	128640		T3	12284
sram_ifetch_enable	22837292	1			T2	112268		T12	289068		T24	316864

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	150393268	1			T1	261764		T2	315782		T3	12284
hw_debug_en_valid_off	117954565	1			T1	261764		T2	92492		T3	12284
hw_debug_en_on	21165463	1			T2	222852		T12	141820		T24	527192

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115991498	1			T1	261764		T2	128640		T3	12284
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	103580124	1			T1	261764		T3	12284		T8	61440
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8726293	1			T2	128640		T24	570058		T20	21150
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4775556	1			T2	29656		T12	35234		T24	56302
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2432590	1			T12	35234		T68	6298		T136	67272
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1640976	1			T2	29656		T24	56302		T67	39374
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4442608	1			T2	45218		T12	69870		T24	35110
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1756984	1			T12	69870		T68	21860		T7	8660
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1973274	1			T2	45218		T24	35110		T67	66472
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8532451	1			T2	75100		T12	51950		T24	390080
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3671478	1			T12	51950		T67	18658		T137	58734
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3778527	1			T2	75100		T24	390080		T20	21150

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8922764	1			T2	112268		T24	316864		T67	332106
lc_exec_en	8190404	1			T2	102534		T12	20000		T24	102002
valid_exec_dis	112599228	1			T1	261764		T2	53540		T3	12284
invalid_exec_dis	34401770	1			T2	187142		T12	405666		T24	459230