Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45517595	1			T1	119084		T2	57691		T3	6142
triple_byte_access	2451279	1			T1	2370		T2	1197		T4	5005
halfword_access	3674587	1			T1	3583		T2	1725		T4	7493
byte_access	4909874	1			T1	4645		T2	2322		T4	9826
zero_access	1235847	1			T1	1200		T2	565		T4	2446

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28836503

1

T1

65147

T2

31883

T3

2048

auto[1]

28952679

1

T1

65735

T2

31617

T3

4094

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22706523	1			T1	59206		T2	28967		T3	2048
auto[0]	triple_byte_access	1221393	1			T1	1190		T2	606		T4	2463
auto[0]	halfword_access	1833120	1			T1	1801		T2	886		T4	3776
auto[0]	byte_access	2453557	1			T1	2374		T2	1144		T4	4933
auto[0]	zero_access	621910	1			T1	576		T2	280		T4	1251
auto[1]	word_access	22811072	1			T1	59878		T2	28724		T3	4094
auto[1]	triple_byte_access	1229886	1			T1	1180		T2	591		T4	2542
auto[1]	halfword_access	1841467	1			T1	1782		T2	839		T4	3717
auto[1]	byte_access	2456317	1			T1	2271		T2	1178		T4	4893
auto[1]	zero_access	613937	1			T1	624		T2	285		T4	1195