Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	152097226	1			T1	257114		T3	42856		T4	10572
instr_valid_dis	114885448	1			T1	98		T3	42856		T4	10572
instr_en	27167721	1			T5	15188		T11	423474		T42	24586

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11455500	1			T1	73198		T3	20024		T5	36868
sram_ifetch_valid_disable	117597039	1			T1	105310		T3	22832		T4	10572
sram_ifetch_enable	23044687	1			T1	78606		T5	34894		T11	129868

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	152097226	1			T1	257114		T3	42856		T4	10572
hw_debug_en_valid_off	116323635	1			T1	117320		T3	22832		T4	10572
hw_debug_en_on	25544103	1			T1	61464		T3	20024		T5	76852

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	117597039	1			T1	105310		T3	22832		T4	10572
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102109570	1			T1	98		T3	22832		T4	10572
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11554405	1			T11	193970		T130	62926		T7	1194
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4021256	1			T1	73198		T5	15188		T11	44810
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1270392	1			T42	11988		T7	54488		T118	52332
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2057570	1			T5	15188		T11	44810		T63	89092
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5196700	1			T3	20024		T5	21680		T11	37186
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1956420	1			T3	20024		T64	73096		T120	28626
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2593734	1			T11	37186		T63	20000		T21	65842
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10432181	1			T1	34408		T5	55172		T11	97570
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3127804	1			T130	12770		T7	8078		T21	12614
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5860285	1			T11	97570		T130	14008		T63	38782

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10069574	1			T11	129868		T42	14448		T130	37760
lc_exec_en	9915222	1			T1	27056		T11	64874		T42	52352
valid_exec_dis	112054620	1			T1	31700		T3	22832		T4	10572
invalid_exec_dis	34500187	1			T1	151804		T3	20024		T5	71762