Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1033
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.91 82.91 96.10 96.10 82.58 82.58 95.32 95.32 71.43 71.43 87.92 87.92 94.40 94.40 52.65 52.65 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1848877105
88.10 5.19 96.27 0.17 85.19 2.61 95.74 0.42 71.43 0.00 89.61 1.69 95.28 0.88 83.18 30.53 /workspace/coverage/default/38.sram_ctrl_regwen.2450039695
91.36 3.26 97.29 1.02 85.31 0.12 95.74 0.00 90.48 19.05 91.55 1.93 96.02 0.74 83.18 0.00 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1659551618
94.15 2.79 98.64 1.36 88.27 2.96 96.78 1.04 100.00 9.52 94.69 3.14 96.61 0.59 84.10 0.91 /workspace/coverage/default/0.sram_ctrl_sec_cm.1062592114
94.98 0.82 98.81 0.17 89.69 1.42 97.05 0.28 100.00 0.00 95.65 0.97 96.61 0.00 87.02 2.93 /workspace/coverage/default/48.sram_ctrl_stress_all.2342278322
95.79 0.82 98.81 0.00 90.28 0.59 97.05 0.00 100.00 0.00 95.65 0.00 96.61 0.00 92.14 5.12 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.397422359
96.43 0.64 98.81 0.00 90.28 0.00 98.58 1.53 100.00 0.00 95.89 0.24 96.76 0.15 94.70 2.56 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1661114163
96.71 0.28 99.07 0.25 90.28 0.00 98.61 0.03 100.00 0.00 96.14 0.24 97.79 1.03 95.06 0.37 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2468997952
96.89 0.18 99.07 0.00 90.28 0.00 98.68 0.07 100.00 0.00 96.14 0.00 98.97 1.18 95.06 0.00 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1198287009
97.03 0.14 99.15 0.08 90.28 0.00 99.58 0.90 100.00 0.00 96.14 0.00 98.97 0.00 95.06 0.00 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2259358705
97.13 0.10 99.15 0.00 90.28 0.00 99.58 0.00 100.00 0.00 96.14 0.00 98.97 0.00 95.80 0.73 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1410171506
97.22 0.09 99.15 0.00 90.64 0.36 99.65 0.07 100.00 0.00 96.14 0.00 98.97 0.00 95.98 0.18 /workspace/coverage/default/32.sram_ctrl_alert_test.2018207654
97.30 0.08 99.15 0.00 90.64 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.53 0.55 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2439831370
97.37 0.07 99.15 0.00 90.76 0.12 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.89 0.37 /workspace/coverage/default/7.sram_ctrl_stress_all.1253571183
97.40 0.03 99.15 0.00 91.00 0.24 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.89 0.00 /workspace/coverage/default/0.sram_ctrl_lc_escalation.796653103
97.43 0.03 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.07 0.18 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3951049647
97.45 0.03 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.26 0.18 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.135084817
97.48 0.03 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.44 0.18 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.443681925
97.50 0.02 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 99.12 0.15 97.44 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1011838870
97.51 0.01 99.15 0.00 91.00 0.00 99.72 0.07 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.00 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1911961353

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1769337131
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3461666069
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3424902495
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.289626416
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1359446351
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3670594584
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1008830585
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.357808505
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3120789139
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2925770072
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.980025632
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3590109792
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2420057361
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2609919351
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2655620616
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1465953779
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1576673741
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4246440475
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3812292252
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4206388143
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2603810356
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2419912141
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4190328181
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.370028264
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3733499964
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4203171730
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2535199307
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3968725261
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3854701596
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.537048164
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3792349584
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3318298428
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1851405762
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3521384855
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1826608504
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1562161927
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.771893786
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1884424003
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1274090694
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3421863569
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.412631881
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3683983505
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.692716373
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.242281630
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1087293890
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1447171288
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1667787685
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4106383558
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.604352084
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3837830077
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2269758265
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.219062871
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.310877392
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1426871035
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1124706154
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1181522442
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3104422516
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3219094168
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2399942690
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.176811408
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3403189450
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1750351802
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.920060349
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1077299068
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1970479921
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3130036691
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.325254458
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1850468077
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2288491190
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4173484887
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2273026220
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3561390088
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1377043598
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2156141731
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.726983166
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.605700276
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3749901287
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2148309694
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1578656121
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1205616684
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.454459739
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1884210374
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3303427169
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.957254713
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.394516871
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3649870189
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2291276462
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3582101677
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2940814765
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2894854151
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.427513984
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3112811549
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3331675947
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3414910514
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1173843497
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3300898651
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.271993152
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2270270852
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3360995402
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2441761427
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1718799807
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3485592820
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1429346581
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1599302045
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.282772442
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1743284638
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2748741862
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3873488739
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2399725769
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.126301651
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1371070711
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1437204499
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.765986030
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.23283589
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1977850160
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3424099965
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2352116897
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2412602225
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2758046781
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3877595874
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.591136503
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3246849959
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1103644666
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2407107316
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1828199842
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3192680831
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.513417720
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1206964341
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2774340976
/workspace/coverage/default/0.sram_ctrl_alert_test.4188856957
/workspace/coverage/default/0.sram_ctrl_bijection.3008759341
/workspace/coverage/default/0.sram_ctrl_executable.946103918
/workspace/coverage/default/0.sram_ctrl_max_throughput.2130674410
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1344428595
/workspace/coverage/default/0.sram_ctrl_mem_walk.2728157922
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2446231446
/workspace/coverage/default/0.sram_ctrl_partial_access.577574387
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2795214908
/workspace/coverage/default/0.sram_ctrl_ram_cfg.352440271
/workspace/coverage/default/0.sram_ctrl_regwen.742937460
/workspace/coverage/default/0.sram_ctrl_smoke.754324031
/workspace/coverage/default/0.sram_ctrl_stress_all.4153440193
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3045978996
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1772951023
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.6368490
/workspace/coverage/default/1.sram_ctrl_alert_test.361566742
/workspace/coverage/default/1.sram_ctrl_bijection.101026608
/workspace/coverage/default/1.sram_ctrl_executable.3331073979
/workspace/coverage/default/1.sram_ctrl_lc_escalation.121673777
/workspace/coverage/default/1.sram_ctrl_max_throughput.2961211661
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1360005923
/workspace/coverage/default/1.sram_ctrl_mem_walk.1960925753
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2916197051
/workspace/coverage/default/1.sram_ctrl_partial_access.3836088361
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2902557131
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2945106889
/workspace/coverage/default/1.sram_ctrl_regwen.3625583667
/workspace/coverage/default/1.sram_ctrl_sec_cm.2849465133
/workspace/coverage/default/1.sram_ctrl_smoke.341278144
/workspace/coverage/default/1.sram_ctrl_stress_all.1953770102
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1888018092
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2104485045
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1589778633
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1904544331
/workspace/coverage/default/10.sram_ctrl_alert_test.4188429512
/workspace/coverage/default/10.sram_ctrl_bijection.1092901802
/workspace/coverage/default/10.sram_ctrl_executable.2051834978
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1369454543
/workspace/coverage/default/10.sram_ctrl_max_throughput.2745021565
/workspace/coverage/default/10.sram_ctrl_mem_walk.2727087803
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4019151247
/workspace/coverage/default/10.sram_ctrl_partial_access.4042241230
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2383064171
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2351949496
/workspace/coverage/default/10.sram_ctrl_regwen.2678504806
/workspace/coverage/default/10.sram_ctrl_smoke.3388339984
/workspace/coverage/default/10.sram_ctrl_stress_all.468375454
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3722747897
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.677964804
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1856149610
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.967156488
/workspace/coverage/default/11.sram_ctrl_alert_test.3395020031
/workspace/coverage/default/11.sram_ctrl_bijection.2513995604
/workspace/coverage/default/11.sram_ctrl_executable.2051361373
/workspace/coverage/default/11.sram_ctrl_lc_escalation.476325903
/workspace/coverage/default/11.sram_ctrl_max_throughput.469467022
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4123354167
/workspace/coverage/default/11.sram_ctrl_mem_walk.533262345
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3205469763
/workspace/coverage/default/11.sram_ctrl_partial_access.1354490033
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1692594525
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1719520702
/workspace/coverage/default/11.sram_ctrl_regwen.2877411191
/workspace/coverage/default/11.sram_ctrl_smoke.1037761465
/workspace/coverage/default/11.sram_ctrl_stress_all.3703787149
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1945284203
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.862625085
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3709765315
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.827738117
/workspace/coverage/default/12.sram_ctrl_alert_test.2679358424
/workspace/coverage/default/12.sram_ctrl_bijection.2454443126
/workspace/coverage/default/12.sram_ctrl_executable.44200415
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2271964934
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/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3885988191
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1021041925
/workspace/coverage/default/43.sram_ctrl_alert_test.2105039226
/workspace/coverage/default/43.sram_ctrl_bijection.690417640
/workspace/coverage/default/43.sram_ctrl_executable.3947508105
/workspace/coverage/default/43.sram_ctrl_lc_escalation.123726251
/workspace/coverage/default/43.sram_ctrl_max_throughput.4156503268
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.4014690621
/workspace/coverage/default/43.sram_ctrl_mem_walk.247733739
/workspace/coverage/default/43.sram_ctrl_multiple_keys.180841991
/workspace/coverage/default/43.sram_ctrl_partial_access.3873306899
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2132823469
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3806269656
/workspace/coverage/default/43.sram_ctrl_regwen.3356176757
/workspace/coverage/default/43.sram_ctrl_smoke.4177175997
/workspace/coverage/default/43.sram_ctrl_stress_all.2386381451
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4277916902
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.154613063
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3577937450
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1516158491
/workspace/coverage/default/44.sram_ctrl_alert_test.1578696762
/workspace/coverage/default/44.sram_ctrl_bijection.2956753506
/workspace/coverage/default/44.sram_ctrl_executable.2386515540
/workspace/coverage/default/44.sram_ctrl_lc_escalation.4062069782
/workspace/coverage/default/44.sram_ctrl_max_throughput.988370391
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1241726219
/workspace/coverage/default/44.sram_ctrl_mem_walk.718293276
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1143971644
/workspace/coverage/default/44.sram_ctrl_partial_access.3772801826
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.639295318
/workspace/coverage/default/44.sram_ctrl_ram_cfg.959494599
/workspace/coverage/default/44.sram_ctrl_regwen.3473947312
/workspace/coverage/default/44.sram_ctrl_smoke.2808954990
/workspace/coverage/default/44.sram_ctrl_stress_all.791539361
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1126546926
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3420586536
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.378463493
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3573519244
/workspace/coverage/default/45.sram_ctrl_alert_test.4086490577
/workspace/coverage/default/45.sram_ctrl_bijection.2287023687
/workspace/coverage/default/45.sram_ctrl_executable.1916112606
/workspace/coverage/default/45.sram_ctrl_lc_escalation.762363577
/workspace/coverage/default/45.sram_ctrl_max_throughput.1745173584
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3922376708
/workspace/coverage/default/45.sram_ctrl_mem_walk.143983991
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2160780830
/workspace/coverage/default/45.sram_ctrl_partial_access.3156709899
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.936664599
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1659744456
/workspace/coverage/default/45.sram_ctrl_regwen.3555636109
/workspace/coverage/default/45.sram_ctrl_smoke.1149942705
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2945519697
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.563958511
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2978450159
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2088208463
/workspace/coverage/default/46.sram_ctrl_alert_test.2890600013
/workspace/coverage/default/46.sram_ctrl_bijection.4248205718
/workspace/coverage/default/46.sram_ctrl_executable.26440419
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3887369992
/workspace/coverage/default/46.sram_ctrl_max_throughput.2401310177
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.4283978424
/workspace/coverage/default/46.sram_ctrl_mem_walk.1707624141
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3344232087
/workspace/coverage/default/46.sram_ctrl_partial_access.1078196268
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3874597669
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3118155322
/workspace/coverage/default/46.sram_ctrl_regwen.2187507224
/workspace/coverage/default/46.sram_ctrl_smoke.1246674793
/workspace/coverage/default/46.sram_ctrl_stress_all.477767631
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3005403105
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2756600471
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1822218440
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.410481635
/workspace/coverage/default/47.sram_ctrl_alert_test.718823700
/workspace/coverage/default/47.sram_ctrl_bijection.2763726513
/workspace/coverage/default/47.sram_ctrl_executable.1064033637
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1384646512
/workspace/coverage/default/47.sram_ctrl_max_throughput.612653554
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3899362396
/workspace/coverage/default/47.sram_ctrl_mem_walk.115946717
/workspace/coverage/default/47.sram_ctrl_multiple_keys.612508722
/workspace/coverage/default/47.sram_ctrl_partial_access.2705009162
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1618659512
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2000006137
/workspace/coverage/default/47.sram_ctrl_regwen.827531282
/workspace/coverage/default/47.sram_ctrl_smoke.1982033103
/workspace/coverage/default/47.sram_ctrl_stress_all.1235217229
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3042930326
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1161098229
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1712342333
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.179395274
/workspace/coverage/default/48.sram_ctrl_alert_test.448018617
/workspace/coverage/default/48.sram_ctrl_bijection.2715676430
/workspace/coverage/default/48.sram_ctrl_executable.4136582853
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2667941933
/workspace/coverage/default/48.sram_ctrl_max_throughput.494722980
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.698067797
/workspace/coverage/default/48.sram_ctrl_mem_walk.1924980299
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3266474612
/workspace/coverage/default/48.sram_ctrl_partial_access.1847318534
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2122378286
/workspace/coverage/default/48.sram_ctrl_ram_cfg.790696382
/workspace/coverage/default/48.sram_ctrl_regwen.1071744959
/workspace/coverage/default/48.sram_ctrl_smoke.1344748205
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3067055926
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3894940768
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3807967392
/workspace/coverage/default/49.sram_ctrl_alert_test.37587771
/workspace/coverage/default/49.sram_ctrl_bijection.2018848516
/workspace/coverage/default/49.sram_ctrl_executable.1850746499
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2769547019
/workspace/coverage/default/49.sram_ctrl_max_throughput.3334469707
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.326455133
/workspace/coverage/default/49.sram_ctrl_mem_walk.2640374021
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1255369802
/workspace/coverage/default/49.sram_ctrl_partial_access.1205527570
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.927370260
/workspace/coverage/default/49.sram_ctrl_ram_cfg.345727488
/workspace/coverage/default/49.sram_ctrl_regwen.1612721638
/workspace/coverage/default/49.sram_ctrl_smoke.2619814969
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1600293568
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1747806071
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2122196758
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.940212569
/workspace/coverage/default/5.sram_ctrl_alert_test.4031965228
/workspace/coverage/default/5.sram_ctrl_bijection.4178481294
/workspace/coverage/default/5.sram_ctrl_executable.428862774
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4121416866
/workspace/coverage/default/5.sram_ctrl_max_throughput.2821482224
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2046372340
/workspace/coverage/default/5.sram_ctrl_mem_walk.1997752223
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1789715286
/workspace/coverage/default/5.sram_ctrl_partial_access.1647870513
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2915874830
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2262847560
/workspace/coverage/default/5.sram_ctrl_regwen.2189814376
/workspace/coverage/default/5.sram_ctrl_smoke.4080324671
/workspace/coverage/default/5.sram_ctrl_stress_all.3468107831
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2680663015
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2182593743
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.507668777
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3165886002
/workspace/coverage/default/6.sram_ctrl_alert_test.1809221155
/workspace/coverage/default/6.sram_ctrl_bijection.406013810
/workspace/coverage/default/6.sram_ctrl_executable.1805983880
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3313227457
/workspace/coverage/default/6.sram_ctrl_max_throughput.3726633739
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2263693241
/workspace/coverage/default/6.sram_ctrl_mem_walk.2092436963
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3156194092
/workspace/coverage/default/6.sram_ctrl_partial_access.2731861392
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3915740482
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3868826145
/workspace/coverage/default/6.sram_ctrl_regwen.3859416819
/workspace/coverage/default/6.sram_ctrl_smoke.3232659323
/workspace/coverage/default/6.sram_ctrl_stress_all.1108918785
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2303605224
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1163644535
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.512532540
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.85867554
/workspace/coverage/default/7.sram_ctrl_alert_test.322088120
/workspace/coverage/default/7.sram_ctrl_bijection.3547204048
/workspace/coverage/default/7.sram_ctrl_executable.3174736927
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1652256540
/workspace/coverage/default/7.sram_ctrl_max_throughput.4030271095
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2187323639
/workspace/coverage/default/7.sram_ctrl_mem_walk.2010958853
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3474810785
/workspace/coverage/default/7.sram_ctrl_partial_access.1387997752
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1415074297
/workspace/coverage/default/7.sram_ctrl_ram_cfg.74938859
/workspace/coverage/default/7.sram_ctrl_regwen.957725808
/workspace/coverage/default/7.sram_ctrl_smoke.125723248
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1336031446
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.306792064
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3627822012
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.682996353
/workspace/coverage/default/8.sram_ctrl_alert_test.1304274232
/workspace/coverage/default/8.sram_ctrl_bijection.321157751
/workspace/coverage/default/8.sram_ctrl_executable.3103310792
/workspace/coverage/default/8.sram_ctrl_lc_escalation.38215436
/workspace/coverage/default/8.sram_ctrl_max_throughput.2909510164
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.4140955422
/workspace/coverage/default/8.sram_ctrl_mem_walk.1116761327
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1202458287
/workspace/coverage/default/8.sram_ctrl_partial_access.106741377
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3486247559
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2820958296
/workspace/coverage/default/8.sram_ctrl_regwen.1657499899
/workspace/coverage/default/8.sram_ctrl_smoke.1518188372
/workspace/coverage/default/8.sram_ctrl_stress_all.3953876274
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.798912608
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3754408375
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1247087458
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.556320007
/workspace/coverage/default/9.sram_ctrl_alert_test.396878386
/workspace/coverage/default/9.sram_ctrl_bijection.4194528135
/workspace/coverage/default/9.sram_ctrl_executable.2252012155
/workspace/coverage/default/9.sram_ctrl_lc_escalation.479843083
/workspace/coverage/default/9.sram_ctrl_max_throughput.2762740765
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2264657233
/workspace/coverage/default/9.sram_ctrl_mem_walk.4293259510
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3569791479
/workspace/coverage/default/9.sram_ctrl_partial_access.2689327593
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3641534055
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1976740831
/workspace/coverage/default/9.sram_ctrl_regwen.1809848300
/workspace/coverage/default/9.sram_ctrl_smoke.950792266
/workspace/coverage/default/9.sram_ctrl_stress_all.590509654
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3288513270
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3304012404
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4137737592



Total test records in report: 1033
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/19.sram_ctrl_regwen.1983614593 Jun 28 04:34:27 PM PDT 24 Jun 28 04:44:46 PM PDT 24 16794360168 ps
T2 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2259358705 Jun 28 04:34:15 PM PDT 24 Jun 28 04:34:21 PM PDT 24 31322975 ps
T3 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1848877105 Jun 28 04:33:44 PM PDT 24 Jun 28 04:36:46 PM PDT 24 2963387739 ps
T4 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1109637871 Jun 28 04:35:30 PM PDT 24 Jun 28 04:36:00 PM PDT 24 105711648 ps
T5 /workspace/coverage/default/28.sram_ctrl_regwen.1690941658 Jun 28 04:35:00 PM PDT 24 Jun 28 04:39:05 PM PDT 24 7005288833 ps
T9 /workspace/coverage/default/5.sram_ctrl_max_throughput.2821482224 Jun 28 04:33:51 PM PDT 24 Jun 28 04:33:54 PM PDT 24 36180661 ps
T10 /workspace/coverage/default/44.sram_ctrl_ram_cfg.959494599 Jun 28 04:36:08 PM PDT 24 Jun 28 04:36:10 PM PDT 24 26495975 ps
T11 /workspace/coverage/default/38.sram_ctrl_regwen.2450039695 Jun 28 04:35:29 PM PDT 24 Jun 28 04:57:53 PM PDT 24 38811774327 ps
T12 /workspace/coverage/default/40.sram_ctrl_multiple_keys.2824511293 Jun 28 04:35:39 PM PDT 24 Jun 28 04:48:40 PM PDT 24 17013411696 ps
T13 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2902557131 Jun 28 04:33:33 PM PDT 24 Jun 28 04:40:10 PM PDT 24 21543637501 ps
T40 /workspace/coverage/default/7.sram_ctrl_mem_walk.2010958853 Jun 28 04:33:59 PM PDT 24 Jun 28 04:34:17 PM PDT 24 463593175 ps
T41 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3420586536 Jun 28 04:36:05 PM PDT 24 Jun 28 04:38:58 PM PDT 24 1824069086 ps
T62 /workspace/coverage/default/29.sram_ctrl_max_throughput.159224610 Jun 28 04:35:04 PM PDT 24 Jun 28 04:36:51 PM PDT 24 477688541 ps
T42 /workspace/coverage/default/23.sram_ctrl_regwen.3217723180 Jun 28 04:34:48 PM PDT 24 Jun 28 04:42:04 PM PDT 24 13849175170 ps
T14 /workspace/coverage/default/32.sram_ctrl_alert_test.2018207654 Jun 28 04:35:09 PM PDT 24 Jun 28 04:35:12 PM PDT 24 25414828 ps
T45 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1911961353 Jun 28 04:34:04 PM PDT 24 Jun 28 04:34:16 PM PDT 24 315034721 ps
T25 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2468997952 Jun 28 04:34:17 PM PDT 24 Jun 28 04:56:10 PM PDT 24 4046376835 ps
T74 /workspace/coverage/default/5.sram_ctrl_multiple_keys.1789715286 Jun 28 04:33:51 PM PDT 24 Jun 28 04:46:46 PM PDT 24 11513206704 ps
T77 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1161098229 Jun 28 04:36:16 PM PDT 24 Jun 28 04:40:23 PM PDT 24 5480282397 ps
T75 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.127995587 Jun 28 04:34:31 PM PDT 24 Jun 28 04:37:22 PM PDT 24 1794187696 ps
T6 /workspace/coverage/default/0.sram_ctrl_lc_escalation.796653103 Jun 28 04:33:34 PM PDT 24 Jun 28 04:33:37 PM PDT 24 983648394 ps
T50 /workspace/coverage/default/8.sram_ctrl_mem_walk.1116761327 Jun 28 04:34:09 PM PDT 24 Jun 28 04:34:21 PM PDT 24 100492055 ps
T76 /workspace/coverage/default/26.sram_ctrl_multiple_keys.980079842 Jun 28 04:34:48 PM PDT 24 Jun 28 04:45:03 PM PDT 24 1845393425 ps
T26 /workspace/coverage/default/46.sram_ctrl_partial_access.1078196268 Jun 28 04:36:06 PM PDT 24 Jun 28 04:36:08 PM PDT 24 145621187 ps
T24 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.961863759 Jun 28 04:34:56 PM PDT 24 Jun 28 04:35:02 PM PDT 24 372849343 ps
T130 /workspace/coverage/default/49.sram_ctrl_executable.1850746499 Jun 28 04:36:17 PM PDT 24 Jun 28 04:45:29 PM PDT 24 2884311857 ps
T20 /workspace/coverage/default/10.sram_ctrl_bijection.1092901802 Jun 28 04:34:03 PM PDT 24 Jun 28 04:34:35 PM PDT 24 16389971920 ps
T7 /workspace/coverage/default/48.sram_ctrl_stress_all.2342278322 Jun 28 04:36:30 PM PDT 24 Jun 28 04:52:53 PM PDT 24 66960414285 ps
T147 /workspace/coverage/default/4.sram_ctrl_smoke.3086093095 Jun 28 04:33:51 PM PDT 24 Jun 28 04:34:12 PM PDT 24 290969323 ps
T142 /workspace/coverage/default/26.sram_ctrl_smoke.2469211544 Jun 28 04:34:55 PM PDT 24 Jun 28 04:35:56 PM PDT 24 500153195 ps
T8 /workspace/coverage/default/45.sram_ctrl_lc_escalation.762363577 Jun 28 04:36:05 PM PDT 24 Jun 28 04:36:13 PM PDT 24 478337242 ps
T148 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1598932465 Jun 28 04:35:06 PM PDT 24 Jun 28 04:35:52 PM PDT 24 220515461 ps
T143 /workspace/coverage/default/30.sram_ctrl_max_throughput.2663340582 Jun 28 04:35:09 PM PDT 24 Jun 28 04:35:14 PM PDT 24 46612463 ps
T145 /workspace/coverage/default/36.sram_ctrl_bijection.1984311662 Jun 28 04:35:21 PM PDT 24 Jun 28 04:35:37 PM PDT 24 247288361 ps
T102 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2694829571 Jun 28 04:35:09 PM PDT 24 Jun 28 04:39:32 PM PDT 24 2703718109 ps
T149 /workspace/coverage/default/41.sram_ctrl_bijection.2305056033 Jun 28 04:35:40 PM PDT 24 Jun 28 04:36:02 PM PDT 24 620103662 ps
T85 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2067188240 Jun 28 04:34:39 PM PDT 24 Jun 28 04:34:43 PM PDT 24 173581251 ps
T27 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2182484269 Jun 28 04:34:55 PM PDT 24 Jun 28 04:36:12 PM PDT 24 2996559326 ps
T49 /workspace/coverage/default/40.sram_ctrl_mem_walk.2467181678 Jun 28 04:35:38 PM PDT 24 Jun 28 04:35:45 PM PDT 24 347530198 ps
T129 /workspace/coverage/default/37.sram_ctrl_mem_walk.1735822392 Jun 28 04:35:30 PM PDT 24 Jun 28 04:35:40 PM PDT 24 273333136 ps
T15 /workspace/coverage/default/22.sram_ctrl_alert_test.1580375247 Jun 28 04:34:35 PM PDT 24 Jun 28 04:34:37 PM PDT 24 27889056 ps
T103 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1661114163 Jun 28 04:34:58 PM PDT 24 Jun 28 04:41:29 PM PDT 24 62134530911 ps
T63 /workspace/coverage/default/12.sram_ctrl_regwen.2028452131 Jun 28 04:34:15 PM PDT 24 Jun 28 04:45:48 PM PDT 24 42562578364 ps
T146 /workspace/coverage/default/15.sram_ctrl_bijection.786092327 Jun 28 04:34:20 PM PDT 24 Jun 28 04:35:20 PM PDT 24 4532981391 ps
T104 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2383064171 Jun 28 04:34:02 PM PDT 24 Jun 28 04:37:28 PM PDT 24 10697138941 ps
T21 /workspace/coverage/default/33.sram_ctrl_regwen.1535851280 Jun 28 04:35:13 PM PDT 24 Jun 28 04:53:15 PM PDT 24 14634230565 ps
T150 /workspace/coverage/default/20.sram_ctrl_smoke.2307109607 Jun 28 04:34:33 PM PDT 24 Jun 28 04:34:46 PM PDT 24 703069920 ps
T64 /workspace/coverage/default/8.sram_ctrl_stress_all.3953876274 Jun 28 04:34:06 PM PDT 24 Jun 28 05:55:16 PM PDT 24 399349263708 ps
T151 /workspace/coverage/default/31.sram_ctrl_max_throughput.181651638 Jun 28 04:35:14 PM PDT 24 Jun 28 04:37:15 PM PDT 24 242808377 ps
T152 /workspace/coverage/default/6.sram_ctrl_bijection.406013810 Jun 28 04:33:54 PM PDT 24 Jun 28 04:34:26 PM PDT 24 5610210331 ps
T141 /workspace/coverage/default/44.sram_ctrl_lc_escalation.4062069782 Jun 28 04:36:04 PM PDT 24 Jun 28 04:36:10 PM PDT 24 487289928 ps
T153 /workspace/coverage/default/46.sram_ctrl_max_throughput.2401310177 Jun 28 04:36:13 PM PDT 24 Jun 28 04:37:57 PM PDT 24 167479022 ps
T154 /workspace/coverage/default/49.sram_ctrl_max_throughput.3334469707 Jun 28 04:36:17 PM PDT 24 Jun 28 04:36:40 PM PDT 24 367108074 ps
T105 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2817248434 Jun 28 04:34:46 PM PDT 24 Jun 28 04:37:19 PM PDT 24 3143705703 ps
T133 /workspace/coverage/default/37.sram_ctrl_regwen.1355133698 Jun 28 04:35:33 PM PDT 24 Jun 28 04:46:20 PM PDT 24 12317162855 ps
T144 /workspace/coverage/default/20.sram_ctrl_partial_access.2403043342 Jun 28 04:34:39 PM PDT 24 Jun 28 04:35:01 PM PDT 24 2486074224 ps
T155 /workspace/coverage/default/39.sram_ctrl_max_throughput.41482392 Jun 28 04:35:31 PM PDT 24 Jun 28 04:35:34 PM PDT 24 41699971 ps
T46 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1659551618 Jun 28 04:33:51 PM PDT 24 Jun 28 04:35:10 PM PDT 24 1707293343 ps
T106 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1494920244 Jun 28 04:33:31 PM PDT 24 Jun 28 04:37:50 PM PDT 24 5992619832 ps
T47 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.325665081 Jun 28 04:34:28 PM PDT 24 Jun 28 04:35:41 PM PDT 24 5322891275 ps
T16 /workspace/coverage/default/10.sram_ctrl_alert_test.4188429512 Jun 28 04:34:16 PM PDT 24 Jun 28 04:34:22 PM PDT 24 21677567 ps
T107 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1222116900 Jun 28 04:35:34 PM PDT 24 Jun 28 04:44:18 PM PDT 24 31085583549 ps
T117 /workspace/coverage/default/44.sram_ctrl_bijection.2956753506 Jun 28 04:36:05 PM PDT 24 Jun 28 04:36:28 PM PDT 24 1230807560 ps
T118 /workspace/coverage/default/20.sram_ctrl_regwen.923229220 Jun 28 04:34:35 PM PDT 24 Jun 28 04:55:39 PM PDT 24 6441118095 ps
T119 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2342561154 Jun 28 04:34:43 PM PDT 24 Jun 28 04:39:06 PM PDT 24 17261773027 ps
T22 /workspace/coverage/default/7.sram_ctrl_stress_all.1253571183 Jun 28 04:33:55 PM PDT 24 Jun 28 05:04:40 PM PDT 24 24643669998 ps
T120 /workspace/coverage/default/44.sram_ctrl_executable.2386515540 Jun 28 04:36:10 PM PDT 24 Jun 28 04:50:51 PM PDT 24 32283437182 ps
T51 /workspace/coverage/default/27.sram_ctrl_mem_walk.2911645229 Jun 28 04:34:59 PM PDT 24 Jun 28 04:35:12 PM PDT 24 693112377 ps
T156 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.378463493 Jun 28 04:36:06 PM PDT 24 Jun 28 04:36:37 PM PDT 24 94393794 ps
T157 /workspace/coverage/default/7.sram_ctrl_partial_access.1387997752 Jun 28 04:33:57 PM PDT 24 Jun 28 04:34:07 PM PDT 24 896670581 ps
T52 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.592079622 Jun 28 04:34:25 PM PDT 24 Jun 28 04:34:52 PM PDT 24 737358352 ps
T28 /workspace/coverage/default/48.sram_ctrl_ram_cfg.790696382 Jun 28 04:36:31 PM PDT 24 Jun 28 04:36:33 PM PDT 24 87186224 ps
T158 /workspace/coverage/default/17.sram_ctrl_ram_cfg.2713463284 Jun 28 04:34:23 PM PDT 24 Jun 28 04:34:25 PM PDT 24 41809978 ps
T137 /workspace/coverage/default/26.sram_ctrl_regwen.20292611 Jun 28 04:34:47 PM PDT 24 Jun 28 04:46:37 PM PDT 24 11194092453 ps
T159 /workspace/coverage/default/33.sram_ctrl_ram_cfg.2898194076 Jun 28 04:35:10 PM PDT 24 Jun 28 04:35:13 PM PDT 24 62022934 ps
T134 /workspace/coverage/default/20.sram_ctrl_executable.1352274336 Jun 28 04:34:36 PM PDT 24 Jun 28 04:53:54 PM PDT 24 78234306756 ps
T43 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.625708502 Jun 28 04:33:39 PM PDT 24 Jun 28 04:44:26 PM PDT 24 3693560357 ps
T160 /workspace/coverage/default/26.sram_ctrl_max_throughput.1097311508 Jun 28 04:34:53 PM PDT 24 Jun 28 04:37:16 PM PDT 24 134622614 ps
T161 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2074729739 Jun 28 04:35:39 PM PDT 24 Jun 28 04:38:44 PM PDT 24 3785319044 ps
T162 /workspace/coverage/default/15.sram_ctrl_ram_cfg.920370967 Jun 28 04:34:17 PM PDT 24 Jun 28 04:34:22 PM PDT 24 72928769 ps
T138 /workspace/coverage/default/28.sram_ctrl_smoke.54658108 Jun 28 04:35:09 PM PDT 24 Jun 28 04:36:43 PM PDT 24 640537650 ps
T163 /workspace/coverage/default/10.sram_ctrl_stress_all.468375454 Jun 28 04:34:04 PM PDT 24 Jun 28 06:05:52 PM PDT 24 561927155807 ps
T164 /workspace/coverage/default/43.sram_ctrl_regwen.3356176757 Jun 28 04:36:05 PM PDT 24 Jun 28 04:39:38 PM PDT 24 1211053316 ps
T23 /workspace/coverage/default/2.sram_ctrl_stress_all.1166701486 Jun 28 04:33:48 PM PDT 24 Jun 28 04:52:07 PM PDT 24 4285166065 ps
T165 /workspace/coverage/default/4.sram_ctrl_executable.2511962553 Jun 28 04:33:39 PM PDT 24 Jun 28 04:35:18 PM PDT 24 1346097414 ps
T166 /workspace/coverage/default/31.sram_ctrl_lc_escalation.756461662 Jun 28 04:35:13 PM PDT 24 Jun 28 04:35:18 PM PDT 24 1020899030 ps
T44 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3945316980 Jun 28 04:34:57 PM PDT 24 Jun 28 04:51:27 PM PDT 24 2587808351 ps
T167 /workspace/coverage/default/12.sram_ctrl_smoke.61559810 Jun 28 04:34:09 PM PDT 24 Jun 28 04:36:03 PM PDT 24 129682158 ps
T168 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.3900328558 Jun 28 04:35:31 PM PDT 24 Jun 28 04:40:35 PM PDT 24 5885978525 ps
T139 /workspace/coverage/default/3.sram_ctrl_partial_access.2170734830 Jun 28 04:33:41 PM PDT 24 Jun 28 04:35:43 PM PDT 24 681650384 ps
T53 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1850835588 Jun 28 04:35:28 PM PDT 24 Jun 28 04:40:04 PM PDT 24 4466018625 ps
T169 /workspace/coverage/default/46.sram_ctrl_smoke.1246674793 Jun 28 04:36:05 PM PDT 24 Jun 28 04:36:19 PM PDT 24 3140681531 ps
T86 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3614752045 Jun 28 04:34:20 PM PDT 24 Jun 28 04:45:42 PM PDT 24 18484661871 ps
T54 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.4084354613 Jun 28 04:35:58 PM PDT 24 Jun 28 04:46:20 PM PDT 24 8179514516 ps
T17 /workspace/coverage/default/0.sram_ctrl_sec_cm.1062592114 Jun 28 04:33:36 PM PDT 24 Jun 28 04:33:39 PM PDT 24 1202399756 ps
T31 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.787522194 Jun 28 04:35:13 PM PDT 24 Jun 28 04:40:20 PM PDT 24 12309290268 ps
T32 /workspace/coverage/default/25.sram_ctrl_multiple_keys.2727125457 Jun 28 04:34:48 PM PDT 24 Jun 28 05:01:06 PM PDT 24 16735410291 ps
T33 /workspace/coverage/default/25.sram_ctrl_bijection.2385125945 Jun 28 04:34:55 PM PDT 24 Jun 28 04:35:43 PM PDT 24 8474532097 ps
T34 /workspace/coverage/default/42.sram_ctrl_smoke.2695250699 Jun 28 04:35:51 PM PDT 24 Jun 28 04:35:54 PM PDT 24 58357804 ps
T35 /workspace/coverage/default/45.sram_ctrl_bijection.2287023687 Jun 28 04:36:04 PM PDT 24 Jun 28 04:37:18 PM PDT 24 13294703181 ps
T36 /workspace/coverage/default/26.sram_ctrl_partial_access.2150676987 Jun 28 04:34:46 PM PDT 24 Jun 28 04:35:07 PM PDT 24 4003220102 ps
T37 /workspace/coverage/default/40.sram_ctrl_alert_test.2645456010 Jun 28 04:35:40 PM PDT 24 Jun 28 04:35:42 PM PDT 24 50758225 ps
T38 /workspace/coverage/default/46.sram_ctrl_alert_test.2890600013 Jun 28 04:36:16 PM PDT 24 Jun 28 04:36:17 PM PDT 24 15174320 ps
T39 /workspace/coverage/default/31.sram_ctrl_multiple_keys.3481456850 Jun 28 04:35:11 PM PDT 24 Jun 28 04:49:37 PM PDT 24 193570608915 ps
T170 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3656613044 Jun 28 04:35:21 PM PDT 24 Jun 28 04:37:27 PM PDT 24 608706054 ps
T171 /workspace/coverage/default/2.sram_ctrl_lc_escalation.1235110193 Jun 28 04:33:29 PM PDT 24 Jun 28 04:33:34 PM PDT 24 2110101016 ps
T172 /workspace/coverage/default/30.sram_ctrl_stress_all.2286137979 Jun 28 04:35:08 PM PDT 24 Jun 28 05:41:05 PM PDT 24 61507068306 ps
T87 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1450227196 Jun 28 04:34:13 PM PDT 24 Jun 28 04:45:23 PM PDT 24 14133550272 ps
T173 /workspace/coverage/default/38.sram_ctrl_executable.1282620126 Jun 28 04:35:31 PM PDT 24 Jun 28 04:48:11 PM PDT 24 7933569598 ps
T174 /workspace/coverage/default/32.sram_ctrl_partial_access.1390559275 Jun 28 04:35:10 PM PDT 24 Jun 28 04:35:17 PM PDT 24 395049990 ps
T175 /workspace/coverage/default/39.sram_ctrl_executable.2842791100 Jun 28 04:35:49 PM PDT 24 Jun 28 04:55:55 PM PDT 24 33901198145 ps
T176 /workspace/coverage/default/28.sram_ctrl_multiple_keys.3073918022 Jun 28 04:34:58 PM PDT 24 Jun 28 04:43:52 PM PDT 24 1513312743 ps
T177 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.4023403172 Jun 28 04:34:35 PM PDT 24 Jun 28 04:40:34 PM PDT 24 39838052204 ps
T178 /workspace/coverage/default/39.sram_ctrl_bijection.4008463995 Jun 28 04:35:34 PM PDT 24 Jun 28 04:35:58 PM PDT 24 7346234750 ps
T179 /workspace/coverage/default/49.sram_ctrl_regwen.1612721638 Jun 28 04:36:18 PM PDT 24 Jun 28 04:49:41 PM PDT 24 10638522525 ps
T55 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1044124253 Jun 28 04:34:26 PM PDT 24 Jun 28 04:34:34 PM PDT 24 179729589 ps
T140 /workspace/coverage/default/1.sram_ctrl_multiple_keys.2916197051 Jun 28 04:33:29 PM PDT 24 Jun 28 04:47:51 PM PDT 24 36951808677 ps
T180 /workspace/coverage/default/30.sram_ctrl_executable.3093671688 Jun 28 04:35:08 PM PDT 24 Jun 28 04:54:04 PM PDT 24 8531707251 ps
T181 /workspace/coverage/default/27.sram_ctrl_ram_cfg.1947570277 Jun 28 04:35:11 PM PDT 24 Jun 28 04:35:14 PM PDT 24 31884877 ps
T182 /workspace/coverage/default/15.sram_ctrl_lc_escalation.4279395992 Jun 28 04:34:18 PM PDT 24 Jun 28 04:34:29 PM PDT 24 909607107 ps
T183 /workspace/coverage/default/13.sram_ctrl_regwen.3093550113 Jun 28 04:34:16 PM PDT 24 Jun 28 04:38:38 PM PDT 24 353299558 ps
T184 /workspace/coverage/default/48.sram_ctrl_smoke.1344748205 Jun 28 04:36:17 PM PDT 24 Jun 28 04:36:31 PM PDT 24 210752598 ps
T185 /workspace/coverage/default/0.sram_ctrl_executable.946103918 Jun 28 04:33:38 PM PDT 24 Jun 28 04:49:25 PM PDT 24 2983984870 ps
T88 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3203085798 Jun 28 04:35:07 PM PDT 24 Jun 28 04:35:13 PM PDT 24 121600336 ps
T186 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.666339127 Jun 28 04:34:16 PM PDT 24 Jun 28 04:34:31 PM PDT 24 71721685 ps
T187 /workspace/coverage/default/49.sram_ctrl_smoke.2619814969 Jun 28 04:36:30 PM PDT 24 Jun 28 04:38:29 PM PDT 24 1085639792 ps
T188 /workspace/coverage/default/18.sram_ctrl_ram_cfg.1123445246 Jun 28 04:34:24 PM PDT 24 Jun 28 04:34:27 PM PDT 24 28471672 ps
T89 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.311209122 Jun 28 04:35:08 PM PDT 24 Jun 28 04:37:34 PM PDT 24 2666155823 ps
T189 /workspace/coverage/default/48.sram_ctrl_partial_access.1847318534 Jun 28 04:36:18 PM PDT 24 Jun 28 04:37:47 PM PDT 24 2104758140 ps
T190 /workspace/coverage/default/25.sram_ctrl_partial_access.3096898549 Jun 28 04:34:46 PM PDT 24 Jun 28 04:35:03 PM PDT 24 244766567 ps
T18 /workspace/coverage/default/1.sram_ctrl_sec_cm.2849465133 Jun 28 04:33:37 PM PDT 24 Jun 28 04:33:40 PM PDT 24 169437415 ps
T191 /workspace/coverage/default/6.sram_ctrl_alert_test.1809221155 Jun 28 04:33:54 PM PDT 24 Jun 28 04:34:00 PM PDT 24 38633691 ps
T192 /workspace/coverage/default/12.sram_ctrl_mem_walk.4013023925 Jun 28 04:34:19 PM PDT 24 Jun 28 04:34:36 PM PDT 24 6356441180 ps
T193 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1747806071 Jun 28 04:36:19 PM PDT 24 Jun 28 04:39:19 PM PDT 24 1878812772 ps
T194 /workspace/coverage/default/10.sram_ctrl_partial_access.4042241230 Jun 28 04:34:09 PM PDT 24 Jun 28 04:34:20 PM PDT 24 889806206 ps
T195 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2774340976 Jun 28 04:33:36 PM PDT 24 Jun 28 04:53:18 PM PDT 24 3660822375 ps
T48 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.361699033 Jun 28 04:34:35 PM PDT 24 Jun 28 04:34:56 PM PDT 24 718927576 ps
T196 /workspace/coverage/default/38.sram_ctrl_bijection.453453389 Jun 28 04:35:29 PM PDT 24 Jun 28 04:36:08 PM PDT 24 15814005437 ps
T197 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3288271006 Jun 28 04:34:36 PM PDT 24 Jun 28 04:38:48 PM PDT 24 952578683 ps
T198 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.1021041925 Jun 28 04:35:50 PM PDT 24 Jun 28 04:59:54 PM PDT 24 10297972228 ps
T199 /workspace/coverage/default/16.sram_ctrl_bijection.2547969771 Jun 28 04:34:23 PM PDT 24 Jun 28 04:35:07 PM PDT 24 3542727156 ps
T200 /workspace/coverage/default/30.sram_ctrl_bijection.155836290 Jun 28 04:35:09 PM PDT 24 Jun 28 04:35:43 PM PDT 24 1599194348 ps
T61 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2303605224 Jun 28 04:33:56 PM PDT 24 Jun 28 04:34:19 PM PDT 24 3069631705 ps
T201 /workspace/coverage/default/8.sram_ctrl_executable.3103310792 Jun 28 04:34:11 PM PDT 24 Jun 28 04:54:22 PM PDT 24 60194828657 ps
T202 /workspace/coverage/default/7.sram_ctrl_smoke.125723248 Jun 28 04:33:54 PM PDT 24 Jun 28 04:34:06 PM PDT 24 94162395 ps
T203 /workspace/coverage/default/7.sram_ctrl_alert_test.322088120 Jun 28 04:33:54 PM PDT 24 Jun 28 04:33:59 PM PDT 24 12709181 ps
T204 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2174606600 Jun 28 04:34:49 PM PDT 24 Jun 28 04:34:56 PM PDT 24 669602673 ps
T205 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1570756461 Jun 28 04:35:23 PM PDT 24 Jun 28 04:50:58 PM PDT 24 10408719015 ps
T206 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2534016656 Jun 28 04:35:40 PM PDT 24 Jun 28 04:36:25 PM PDT 24 447264232 ps
T207 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1562366507 Jun 28 04:35:12 PM PDT 24 Jun 28 04:35:15 PM PDT 24 43212107 ps
T135 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3486247559 Jun 28 04:34:05 PM PDT 24 Jun 28 04:40:14 PM PDT 24 208581320026 ps
T208 /workspace/coverage/default/43.sram_ctrl_stress_all.2386381451 Jun 28 04:36:07 PM PDT 24 Jun 28 05:18:28 PM PDT 24 130456466823 ps
T209 /workspace/coverage/default/3.sram_ctrl_multiple_keys.1801215418 Jun 28 04:33:45 PM PDT 24 Jun 28 04:51:04 PM PDT 24 63755244888 ps
T210 /workspace/coverage/default/17.sram_ctrl_max_throughput.89171925 Jun 28 04:34:26 PM PDT 24 Jun 28 04:34:44 PM PDT 24 284068009 ps
T211 /workspace/coverage/default/38.sram_ctrl_smoke.1572797067 Jun 28 04:35:27 PM PDT 24 Jun 28 04:35:47 PM PDT 24 1164261756 ps
T212 /workspace/coverage/default/9.sram_ctrl_bijection.4194528135 Jun 28 04:34:07 PM PDT 24 Jun 28 04:35:29 PM PDT 24 17284768664 ps
T213 /workspace/coverage/default/16.sram_ctrl_smoke.2205343341 Jun 28 04:34:24 PM PDT 24 Jun 28 04:34:29 PM PDT 24 258815447 ps
T214 /workspace/coverage/default/18.sram_ctrl_regwen.146349929 Jun 28 04:34:30 PM PDT 24 Jun 28 04:44:45 PM PDT 24 11336628575 ps
T215 /workspace/coverage/default/7.sram_ctrl_ram_cfg.74938859 Jun 28 04:33:54 PM PDT 24 Jun 28 04:34:00 PM PDT 24 27300283 ps
T216 /workspace/coverage/default/29.sram_ctrl_regwen.2823943009 Jun 28 04:34:56 PM PDT 24 Jun 28 04:42:01 PM PDT 24 9744272720 ps
T217 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2911844961 Jun 28 04:34:57 PM PDT 24 Jun 28 04:35:04 PM PDT 24 153042160 ps
T218 /workspace/coverage/default/15.sram_ctrl_smoke.2501918286 Jun 28 04:34:16 PM PDT 24 Jun 28 04:34:34 PM PDT 24 2590884990 ps
T219 /workspace/coverage/default/0.sram_ctrl_multiple_keys.2446231446 Jun 28 04:33:24 PM PDT 24 Jun 28 04:33:54 PM PDT 24 729700385 ps
T131 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2439831370 Jun 28 04:33:27 PM PDT 24 Jun 28 04:34:24 PM PDT 24 36880752468 ps
T132 /workspace/coverage/default/3.sram_ctrl_stress_all.3279428247 Jun 28 04:33:40 PM PDT 24 Jun 28 05:18:58 PM PDT 24 33392215591 ps
T220 /workspace/coverage/default/5.sram_ctrl_ram_cfg.2262847560 Jun 28 04:33:54 PM PDT 24 Jun 28 04:34:00 PM PDT 24 104750387 ps
T221 /workspace/coverage/default/45.sram_ctrl_ram_cfg.1659744456 Jun 28 04:36:10 PM PDT 24 Jun 28 04:36:12 PM PDT 24 88754383 ps
T222 /workspace/coverage/default/24.sram_ctrl_mem_walk.3257487476 Jun 28 04:34:55 PM PDT 24 Jun 28 04:35:07 PM PDT 24 2307967358 ps
T223 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3253240083 Jun 28 04:35:11 PM PDT 24 Jun 28 04:35:18 PM PDT 24 180863557 ps
T224 /workspace/coverage/default/34.sram_ctrl_regwen.3343282343 Jun 28 04:35:31 PM PDT 24 Jun 28 04:43:17 PM PDT 24 2638214425 ps
T225 /workspace/coverage/default/19.sram_ctrl_bijection.2863578080 Jun 28 04:34:28 PM PDT 24 Jun 28 04:34:46 PM PDT 24 770528561 ps
T226 /workspace/coverage/default/21.sram_ctrl_ram_cfg.1508050482 Jun 28 04:34:37 PM PDT 24 Jun 28 04:34:39 PM PDT 24 78801581 ps
T19 /workspace/coverage/default/4.sram_ctrl_sec_cm.1214218234 Jun 28 04:33:46 PM PDT 24 Jun 28 04:33:50 PM PDT 24 218562030 ps
T227 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.29541754 Jun 28 04:35:53 PM PDT 24 Jun 28 04:38:51 PM PDT 24 1868511523 ps
T228 /workspace/coverage/default/41.sram_ctrl_regwen.3113286626 Jun 28 04:35:54 PM PDT 24 Jun 28 05:03:08 PM PDT 24 228149441021 ps
T229 /workspace/coverage/default/23.sram_ctrl_smoke.583404148 Jun 28 04:34:42 PM PDT 24 Jun 28 04:34:48 PM PDT 24 160425126 ps
T230 /workspace/coverage/default/48.sram_ctrl_mem_walk.1924980299 Jun 28 04:36:18 PM PDT 24 Jun 28 04:36:30 PM PDT 24 1227797762 ps
T231 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1158327837 Jun 28 04:34:58 PM PDT 24 Jun 28 04:44:17 PM PDT 24 4851732952 ps
T232 /workspace/coverage/default/15.sram_ctrl_executable.1686602557 Jun 28 04:34:20 PM PDT 24 Jun 28 04:45:39 PM PDT 24 3469788871 ps
T233 /workspace/coverage/default/26.sram_ctrl_alert_test.4225786386 Jun 28 04:34:53 PM PDT 24 Jun 28 04:34:54 PM PDT 24 23131415 ps
T234 /workspace/coverage/default/20.sram_ctrl_bijection.777951773 Jun 28 04:34:39 PM PDT 24 Jun 28 04:35:51 PM PDT 24 3988884235 ps
T235 /workspace/coverage/default/8.sram_ctrl_max_throughput.2909510164 Jun 28 04:34:09 PM PDT 24 Jun 28 04:34:16 PM PDT 24 59559962 ps
T236 /workspace/coverage/default/46.sram_ctrl_regwen.2187507224 Jun 28 04:36:19 PM PDT 24 Jun 28 04:51:13 PM PDT 24 2176715613 ps
T237 /workspace/coverage/default/24.sram_ctrl_multiple_keys.1809429479 Jun 28 04:34:52 PM PDT 24 Jun 28 04:37:06 PM PDT 24 49377565013 ps
T238 /workspace/coverage/default/0.sram_ctrl_bijection.3008759341 Jun 28 04:33:30 PM PDT 24 Jun 28 04:34:38 PM PDT 24 5098411889 ps
T239 /workspace/coverage/default/31.sram_ctrl_mem_walk.2788137513 Jun 28 04:35:10 PM PDT 24 Jun 28 04:35:17 PM PDT 24 179364144 ps
T136 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1566829399 Jun 28 04:34:31 PM PDT 24 Jun 28 04:43:06 PM PDT 24 23981287227 ps
T240 /workspace/coverage/default/35.sram_ctrl_executable.691713493 Jun 28 04:35:22 PM PDT 24 Jun 28 04:47:02 PM PDT 24 8957619029 ps
T241 /workspace/coverage/default/24.sram_ctrl_bijection.79954965 Jun 28 04:34:54 PM PDT 24 Jun 28 04:35:49 PM PDT 24 845099244 ps
T242 /workspace/coverage/default/37.sram_ctrl_smoke.503429138 Jun 28 04:35:20 PM PDT 24 Jun 28 04:35:24 PM PDT 24 53692302 ps
T243 /workspace/coverage/default/19.sram_ctrl_multiple_keys.2599608775 Jun 28 04:34:25 PM PDT 24 Jun 28 04:52:13 PM PDT 24 16626853064 ps
T244 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3965661011 Jun 28 04:35:08 PM PDT 24 Jun 28 04:40:22 PM PDT 24 4240112169 ps
T245 /workspace/coverage/default/36.sram_ctrl_executable.890195066 Jun 28 04:35:23 PM PDT 24 Jun 28 04:53:11 PM PDT 24 24492429836 ps
T246 /workspace/coverage/default/41.sram_ctrl_max_throughput.219425874 Jun 28 04:35:40 PM PDT 24 Jun 28 04:36:02 PM PDT 24 175389535 ps
T247 /workspace/coverage/default/19.sram_ctrl_stress_all.2834927324 Jun 28 04:34:26 PM PDT 24 Jun 28 05:14:16 PM PDT 24 69224387007 ps
T248 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2125389746 Jun 28 04:33:41 PM PDT 24 Jun 28 04:33:52 PM PDT 24 214719051 ps
T249 /workspace/coverage/default/11.sram_ctrl_multiple_keys.3205469763 Jun 28 04:34:16 PM PDT 24 Jun 28 04:45:58 PM PDT 24 8942814353 ps
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T251 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3915740482 Jun 28 04:33:54 PM PDT 24 Jun 28 04:42:42 PM PDT 24 39451698600 ps
T252 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1041359753 Jun 28 04:35:23 PM PDT 24 Jun 28 04:36:31 PM PDT 24 949438960 ps
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T254 /workspace/coverage/default/27.sram_ctrl_regwen.4215747893 Jun 28 04:35:08 PM PDT 24 Jun 28 04:47:58 PM PDT 24 3698602021 ps
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T258 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3189917536 Jun 28 04:34:47 PM PDT 24 Jun 28 04:40:27 PM PDT 24 22125614271 ps
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T261 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1285852881 Jun 28 04:35:30 PM PDT 24 Jun 28 04:41:27 PM PDT 24 61163016695 ps
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T267 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1247087458 Jun 28 04:34:06 PM PDT 24 Jun 28 04:35:59 PM PDT 24 496576246 ps
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T270 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3860881524 Jun 28 04:34:37 PM PDT 24 Jun 28 04:35:58 PM PDT 24 288376555 ps
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T277 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.586846281 Jun 28 04:35:23 PM PDT 24 Jun 28 04:48:42 PM PDT 24 3069701887 ps
T278 /workspace/coverage/default/42.sram_ctrl_partial_access.992924681 Jun 28 04:35:50 PM PDT 24 Jun 28 04:36:07 PM PDT 24 1878152583 ps
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T280 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3054554834 Jun 28 04:34:17 PM PDT 24 Jun 28 04:41:27 PM PDT 24 25314283343 ps
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T282 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2619977582 Jun 28 04:35:13 PM PDT 24 Jun 28 04:40:25 PM PDT 24 13507811206 ps
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T284 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3887369992 Jun 28 04:36:18 PM PDT 24 Jun 28 04:36:28 PM PDT 24 1456198755 ps
T285 /workspace/coverage/default/28.sram_ctrl_stress_all.1834222399 Jun 28 04:35:12 PM PDT 24 Jun 28 05:16:48 PM PDT 24 27906261802 ps
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T287 /workspace/coverage/default/43.sram_ctrl_bijection.690417640 Jun 28 04:35:52 PM PDT 24 Jun 28 04:36:57 PM PDT 24 9949739541 ps
T288 /workspace/coverage/default/4.sram_ctrl_ram_cfg.1985979042 Jun 28 04:33:39 PM PDT 24 Jun 28 04:33:42 PM PDT 24 28869424 ps
T289 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.507668777 Jun 28 04:33:51 PM PDT 24 Jun 28 04:34:20 PM PDT 24 87708984 ps
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T291 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2457284240 Jun 28 04:34:39 PM PDT 24 Jun 28 04:42:05 PM PDT 24 2940562687 ps
T110 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2555289704 Jun 28 04:34:53 PM PDT 24 Jun 28 04:38:34 PM PDT 24 7067995665 ps
T292 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1470190741 Jun 28 04:33:39 PM PDT 24 Jun 28 04:40:38 PM PDT 24 23499724828 ps
T293 /workspace/coverage/default/17.sram_ctrl_multiple_keys.2564547388 Jun 28 04:34:31 PM PDT 24 Jun 28 04:44:36 PM PDT 24 21876326729 ps
T294 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1489385258 Jun 28 04:34:57 PM PDT 24 Jun 28 04:54:07 PM PDT 24 3796026738 ps
T295 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.475303574 Jun 28 04:35:23 PM PDT 24 Jun 28 04:38:10 PM PDT 24 3441810730 ps
T296 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.971048166 Jun 28 04:35:07 PM PDT 24 Jun 28 04:37:58 PM PDT 24 19882581183 ps
T297 /workspace/coverage/default/10.sram_ctrl_mem_walk.2727087803 Jun 28 04:34:04 PM PDT 24 Jun 28 04:34:21 PM PDT 24 185117772 ps
T298 /workspace/coverage/default/6.sram_ctrl_mem_walk.2092436963 Jun 28 04:33:52 PM PDT 24 Jun 28 04:34:06 PM PDT 24 184988618 ps
T299 /workspace/coverage/default/15.sram_ctrl_multiple_keys.2268899976 Jun 28 04:34:17 PM PDT 24 Jun 28 04:36:06 PM PDT 24 364481147 ps
T300 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.648956531 Jun 28 04:34:53 PM PDT 24 Jun 28 04:40:28 PM PDT 24 22375324299 ps
T301 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1802583211 Jun 28 04:34:50 PM PDT 24 Jun 28 04:34:57 PM PDT 24 355930789 ps
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