Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45783237	1			T1	46674		T3	6130		T4	4303
triple_byte_access	2635540	1			T1	942		T3	110		T4	191
halfword_access	3950789	1			T1	1462		T3	151		T4	296
byte_access	5276790	1			T1	1877		T3	212		T4	402
zero_access	1328372	1			T1	462		T3	50		T4	94

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29426702

1

T1

25708

T3

3108

T4

2683

auto[1]

29548026

1

T1

25709

T3

3545

T4

2603

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22837670	1			T1	23335		T3	2840		T4	2191
auto[0]	triple_byte_access	1313715	1			T1	485		T3	57		T4	98
auto[0]	halfword_access	1971161	1			T1	716		T3	72		T4	136
auto[0]	byte_access	2635916	1			T1	934		T3	108		T4	206
auto[0]	zero_access	668240	1			T1	238		T3	31		T4	52
auto[1]	word_access	22945567	1			T1	23339		T3	3290		T4	2112
auto[1]	triple_byte_access	1321825	1			T1	457		T3	53		T4	93
auto[1]	halfword_access	1979628	1			T1	746		T3	79		T4	160
auto[1]	byte_access	2640874	1			T1	943		T3	104		T4	196
auto[1]	zero_access	660132	1			T1	224		T3	19		T4	42