SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 9 | 0 | 9 | 100.00 |
Crosses | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
csr_exec_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
en_sram_ifetch_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
lc_hw_debug_en_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
executable_cross | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
instr_invalid_dis | 148390428 | 1 | T1 | 3474 | T2 | 9942 | T3 | 7966 | ||||
instr_valid_dis | 115523314 | 1 | T1 | 3474 | T2 | 9942 | T3 | 7966 | ||||
instr_en | 21133935 | 1 | T6 | 265230 | T18 | 1072 | T44 | 309640 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
sram_ifetch_invalid_disable | 10600546 | 1 | T6 | 315692 | T19 | 112708 | T44 | 143460 | ||||
sram_ifetch_valid_disable | 115195854 | 1 | T1 | 3474 | T2 | 9942 | T3 | 7966 | ||||
sram_ifetch_enable | 22594028 | 1 | T6 | 407604 | T19 | 72024 | T44 | 75190 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | 148390428 | 1 | T1 | 3474 | T2 | 9942 | T3 | 7966 | ||||
hw_debug_en_valid_off | 115366613 | 1 | T1 | 3474 | T2 | 9942 | T3 | 7966 | ||||
hw_debug_en_on | 21659866 | 1 | T6 | 390770 | T19 | 87186 | T44 | 117476 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 16 | 0 | 16 | 100.00 | |
Automatically Generated Cross Bins | 12 | 0 | 12 | 100.00 | |
User Defined Cross Bins | 4 | 0 | 4 | 100.00 |
lc_hw_debug_en_cp | en_sram_ifetch_cp | csr_exec_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_invalid_dis | 115195854 | 1 | T1 | 3474 | T2 | 9942 | T3 | 7966 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_valid_dis | 101465283 | 1 | T1 | 3474 | T2 | 9942 | T3 | 7966 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_en | 8785141 | 1 | T6 | 31840 | T18 | 1072 | T44 | 90990 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_invalid_dis | 4430982 | 1 | T6 | 63828 | T19 | 94824 | T44 | 85250 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_valid_dis | 1679876 | 1 | T6 | 34404 | T19 | 94824 | T62 | 7906 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_en | 1666934 | 1 | T6 | 9550 | T44 | 85250 | T20 | 17240 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_invalid_dis | 4254862 | 1 | T6 | 134458 | T19 | 17884 | T44 | 58210 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_valid_dis | 1876346 | 1 | T6 | 73354 | T19 | 17884 | T149 | 14648 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_en | 1708584 | 1 | T44 | 58210 | T20 | 54170 | T62 | 14254 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_invalid_dis | 9287005 | 1 | T6 | 158448 | T19 | 38386 | T44 | 17778 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_valid_dis | 3746805 | 1 | T6 | 59044 | T19 | 38386 | T141 | 11818 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_en | 3650076 | 1 | T6 | 20000 | T44 | 17778 | T96 | 7068 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
csr_exec_en | 8316754 | 1 | T6 | 171428 | T44 | 75190 | T20 | 187734 | ||||
lc_exec_en | 8117999 | 1 | T6 | 97864 | T19 | 30916 | T44 | 41488 | ||||
valid_exec_dis | 110709052 | 1 | T1 | 3474 | T2 | 9942 | T3 | 7966 | ||||
invalid_exec_dis | 33194574 | 1 | T6 | 723296 | T19 | 184732 | T44 | 218650 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |