Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148390428	1			T1	3474		T2	9942		T3	7966
instr_valid_dis	115523314	1			T1	3474		T2	9942		T3	7966
instr_en	21133935	1			T6	265230		T18	1072		T44	309640

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10600546	1			T6	315692		T19	112708		T44	143460
sram_ifetch_valid_disable	115195854	1			T1	3474		T2	9942		T3	7966
sram_ifetch_enable	22594028	1			T6	407604		T19	72024		T44	75190

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148390428	1			T1	3474		T2	9942		T3	7966
hw_debug_en_valid_off	115366613	1			T1	3474		T2	9942		T3	7966
hw_debug_en_on	21659866	1			T6	390770		T19	87186		T44	117476

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115195854	1			T1	3474		T2	9942		T3	7966
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101465283	1			T1	3474		T2	9942		T3	7966
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8785141	1			T6	31840		T18	1072		T44	90990
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4430982	1			T6	63828		T19	94824		T44	85250
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1679876	1			T6	34404		T19	94824		T62	7906
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1666934	1			T6	9550		T44	85250		T20	17240
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4254862	1			T6	134458		T19	17884		T44	58210
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1876346	1			T6	73354		T19	17884		T149	14648
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1708584	1			T44	58210		T20	54170		T62	14254
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9287005	1			T6	158448		T19	38386		T44	17778
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3746805	1			T6	59044		T19	38386		T141	11818
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3650076	1			T6	20000		T44	17778		T96	7068

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8316754	1			T6	171428		T44	75190		T20	187734
lc_exec_en	8117999	1			T6	97864		T19	30916		T44	41488
valid_exec_dis	110709052	1			T1	3474		T2	9942		T3	7966
invalid_exec_dis	33194574	1			T6	723296		T19	184732		T44	218650