Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44424340	1			T1	1407		T2	4971		T3	3983
triple_byte_access	2523803	1			T1	62		T4	3959		T5	105
halfword_access	3791547	1			T1	105		T4	5934		T5	219
byte_access	5059245	1			T1	133		T4	8002		T5	362
zero_access	1271350	1			T1	30		T4	1898		T5	187

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28475642

1

T1

846

T2

2489

T3

1989

auto[1]

28594643

1

T1

891

T2

2482

T3

1994

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22157804	1			T1	690		T2	2489		T3	1989
auto[0]	triple_byte_access	1257250	1			T1	31		T4	1980		T5	11
auto[0]	halfword_access	1893810	1			T1	44		T4	3017		T5	62
auto[0]	byte_access	2528443	1			T1	69		T4	3939		T5	165
auto[0]	zero_access	638335	1			T1	12		T4	946		T5	138
auto[1]	word_access	22266536	1			T1	717		T2	2482		T3	1994
auto[1]	triple_byte_access	1266553	1			T1	31		T4	1979		T5	94
auto[1]	halfword_access	1897737	1			T1	61		T4	2917		T5	157
auto[1]	byte_access	2530802	1			T1	64		T4	4063		T5	197
auto[1]	zero_access	633015	1			T1	18		T4	952		T5	49