Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151921364	1			T1	113114		T3	607622		T5	28672
instr_valid_dis	120421190	1			T1	851390		T3	607622		T5	28672
instr_en	22630541	1			T1	229616		T18	580528		T25	299928

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12951504	1			T1	171554		T18	221736		T25	60596
sram_ifetch_valid_disable	115415602	1			T1	805440		T3	607622		T5	28672
sram_ifetch_enable	23554258	1			T1	154146		T18	152954		T26	16062

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151921364	1			T1	113114		T3	607622		T5	28672
hw_debug_en_valid_off	116858773	1			T1	879270		T3	607622		T5	28672
hw_debug_en_on	22918054	1			T1	143848		T18	322702		T25	59968

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115415602	1			T1	805440		T3	607622		T5	28672
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102629082	1			T1	699626		T3	607622		T5	28672
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9760359	1			T1	105814		T18	205838		T25	103682
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5130102	1			T1	102574		T18	39774		T25	46140
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2712164	1			T1	4330		T144	2070		T139	74
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1655682	1			T1	98244		T18	39774		T25	46140
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4472916	1			T1	43422		T18	153848		T23	18220
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1934998	1			T145	26160		T141	19694		T146	27712
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1941198	1			T18	153848		T23	18220		T20	9828
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9437938	1			T1	73082		T18	79386		T25	59968
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4388828	1			T1	30824		T144	75376		T145	86138
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3771166	1			T1	42258		T18	79386		T25	59968

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8020404	1			T18	152954		T25	135650		T23	51446
lc_exec_en	9007200	1			T1	27344		T18	89468		T23	256
valid_exec_dis	113091231	1			T1	858978		T3	607622		T5	28672
invalid_exec_dis	36505762	1			T1	325700		T18	374690		T26	16062