Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45429381	1			T1	356100		T3	276375		T5	14336
triple_byte_access	2476344	1			T1	6964		T3	5472		T4	215
halfword_access	3716576	1			T1	10606		T3	8276		T4	333
byte_access	4960476	1			T1	14155		T3	10944		T4	403
zero_access	1248317	1			T1	3587		T3	2744		T4	111

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28858008

1

T1

195551

T3

151952

T5

7168

auto[1]

28973086

1

T1

195861

T3

151859

T5

7168

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22661949	1			T1	177845		T3	138333		T5	7168
auto[0]	triple_byte_access	1234635	1			T1	3483		T3	2754		T4	106
auto[0]	halfword_access	1853414	1			T1	5311		T3	4154		T4	181
auto[0]	byte_access	2479438	1			T1	7135		T3	5370		T4	198
auto[0]	zero_access	628572	1			T1	1777		T3	1341		T4	53
auto[1]	word_access	22767432	1			T1	178255		T3	138042		T5	7168
auto[1]	triple_byte_access	1241709	1			T1	3481		T3	2718		T4	109
auto[1]	halfword_access	1863162	1			T1	5295		T3	4122		T4	152
auto[1]	byte_access	2481038	1			T1	7020		T3	5574		T4	205
auto[1]	zero_access	619745	1			T1	1810		T3	1403		T4	58