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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1028
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T793 /workspace/coverage/default/20.sram_ctrl_ram_cfg.1814770854 Jun 30 04:58:55 PM PDT 24 Jun 30 04:58:56 PM PDT 24 43381893 ps
T794 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1151851038 Jun 30 05:00:43 PM PDT 24 Jun 30 05:00:47 PM PDT 24 69498035 ps
T795 /workspace/coverage/default/8.sram_ctrl_executable.2777614712 Jun 30 04:57:49 PM PDT 24 Jun 30 05:32:36 PM PDT 24 26788743716 ps
T796 /workspace/coverage/default/46.sram_ctrl_lc_escalation.574022414 Jun 30 05:02:25 PM PDT 24 Jun 30 05:02:33 PM PDT 24 1326322557 ps
T797 /workspace/coverage/default/44.sram_ctrl_regwen.669316108 Jun 30 05:02:07 PM PDT 24 Jun 30 05:10:15 PM PDT 24 37319995661 ps
T798 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3877913047 Jun 30 04:57:31 PM PDT 24 Jun 30 04:59:38 PM PDT 24 22047674411 ps
T799 /workspace/coverage/default/11.sram_ctrl_bijection.3274423597 Jun 30 04:58:01 PM PDT 24 Jun 30 04:58:53 PM PDT 24 847965413 ps
T800 /workspace/coverage/default/30.sram_ctrl_mem_walk.3849323901 Jun 30 05:00:02 PM PDT 24 Jun 30 05:00:07 PM PDT 24 345058644 ps
T801 /workspace/coverage/default/4.sram_ctrl_multiple_keys.2569560596 Jun 30 04:57:36 PM PDT 24 Jun 30 05:04:17 PM PDT 24 1869432778 ps
T802 /workspace/coverage/default/1.sram_ctrl_partial_access.2239248840 Jun 30 04:57:22 PM PDT 24 Jun 30 04:57:55 PM PDT 24 566644473 ps
T803 /workspace/coverage/default/42.sram_ctrl_bijection.3546612502 Jun 30 05:01:42 PM PDT 24 Jun 30 05:02:24 PM PDT 24 16435448324 ps
T804 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1638436108 Jun 30 05:00:56 PM PDT 24 Jun 30 05:08:45 PM PDT 24 80857337573 ps
T805 /workspace/coverage/default/25.sram_ctrl_alert_test.4079681130 Jun 30 04:59:31 PM PDT 24 Jun 30 04:59:32 PM PDT 24 15596832 ps
T806 /workspace/coverage/default/18.sram_ctrl_alert_test.486497071 Jun 30 04:58:40 PM PDT 24 Jun 30 04:58:42 PM PDT 24 14244401 ps
T807 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1316659665 Jun 30 04:59:03 PM PDT 24 Jun 30 05:04:20 PM PDT 24 8680437105 ps
T808 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3147420381 Jun 30 04:59:17 PM PDT 24 Jun 30 05:03:28 PM PDT 24 2397762655 ps
T809 /workspace/coverage/default/17.sram_ctrl_bijection.443343508 Jun 30 04:58:34 PM PDT 24 Jun 30 04:58:51 PM PDT 24 565754161 ps
T810 /workspace/coverage/default/41.sram_ctrl_max_throughput.3103321070 Jun 30 05:01:34 PM PDT 24 Jun 30 05:02:17 PM PDT 24 118912587 ps
T811 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3573473015 Jun 30 04:58:57 PM PDT 24 Jun 30 05:04:01 PM PDT 24 11454691672 ps
T812 /workspace/coverage/default/32.sram_ctrl_bijection.836846592 Jun 30 05:00:14 PM PDT 24 Jun 30 05:01:00 PM PDT 24 2992642418 ps
T813 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3073910246 Jun 30 04:59:38 PM PDT 24 Jun 30 05:05:12 PM PDT 24 13058216917 ps
T814 /workspace/coverage/default/5.sram_ctrl_ram_cfg.4147048498 Jun 30 04:57:42 PM PDT 24 Jun 30 04:57:43 PM PDT 24 83212840 ps
T815 /workspace/coverage/default/14.sram_ctrl_lc_escalation.1404453266 Jun 30 04:58:16 PM PDT 24 Jun 30 04:58:21 PM PDT 24 292768801 ps
T816 /workspace/coverage/default/29.sram_ctrl_lc_escalation.582018116 Jun 30 04:59:51 PM PDT 24 Jun 30 04:59:53 PM PDT 24 212880767 ps
T817 /workspace/coverage/default/16.sram_ctrl_alert_test.3209896102 Jun 30 04:58:31 PM PDT 24 Jun 30 04:58:32 PM PDT 24 13039506 ps
T818 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2137810800 Jun 30 05:00:47 PM PDT 24 Jun 30 05:09:54 PM PDT 24 8711965338 ps
T819 /workspace/coverage/default/47.sram_ctrl_bijection.2477842556 Jun 30 05:02:30 PM PDT 24 Jun 30 05:03:01 PM PDT 24 480348486 ps
T820 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.363601843 Jun 30 04:57:59 PM PDT 24 Jun 30 05:26:41 PM PDT 24 20951038830 ps
T821 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3947718808 Jun 30 05:01:25 PM PDT 24 Jun 30 05:01:55 PM PDT 24 453765391 ps
T822 /workspace/coverage/default/35.sram_ctrl_mem_walk.3343651141 Jun 30 05:00:43 PM PDT 24 Jun 30 05:00:54 PM PDT 24 2740006715 ps
T823 /workspace/coverage/default/6.sram_ctrl_stress_all.1746290984 Jun 30 04:57:42 PM PDT 24 Jun 30 05:38:57 PM PDT 24 39687085665 ps
T824 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3449488848 Jun 30 04:57:33 PM PDT 24 Jun 30 05:01:29 PM PDT 24 7137399417 ps
T825 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2896638467 Jun 30 04:57:43 PM PDT 24 Jun 30 04:57:50 PM PDT 24 306163597 ps
T826 /workspace/coverage/default/34.sram_ctrl_executable.485508679 Jun 30 05:00:33 PM PDT 24 Jun 30 05:22:59 PM PDT 24 16458591910 ps
T827 /workspace/coverage/default/36.sram_ctrl_bijection.1881340116 Jun 30 05:00:53 PM PDT 24 Jun 30 05:01:47 PM PDT 24 2599672356 ps
T828 /workspace/coverage/default/12.sram_ctrl_regwen.3036343915 Jun 30 04:58:06 PM PDT 24 Jun 30 05:07:08 PM PDT 24 2792680257 ps
T829 /workspace/coverage/default/49.sram_ctrl_bijection.910549626 Jun 30 05:02:44 PM PDT 24 Jun 30 05:03:29 PM PDT 24 7524200677 ps
T830 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2315237106 Jun 30 04:58:33 PM PDT 24 Jun 30 05:09:07 PM PDT 24 10036877608 ps
T831 /workspace/coverage/default/6.sram_ctrl_partial_access.1418404637 Jun 30 04:57:45 PM PDT 24 Jun 30 04:58:48 PM PDT 24 674168497 ps
T832 /workspace/coverage/default/22.sram_ctrl_partial_access.626707574 Jun 30 04:59:02 PM PDT 24 Jun 30 04:59:06 PM PDT 24 117285596 ps
T833 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3570186243 Jun 30 05:00:56 PM PDT 24 Jun 30 05:06:48 PM PDT 24 14691071289 ps
T834 /workspace/coverage/default/2.sram_ctrl_ram_cfg.1136141724 Jun 30 04:57:35 PM PDT 24 Jun 30 04:57:37 PM PDT 24 30188925 ps
T835 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.4106374285 Jun 30 04:58:47 PM PDT 24 Jun 30 05:01:08 PM PDT 24 5958489691 ps
T836 /workspace/coverage/default/26.sram_ctrl_regwen.3099243630 Jun 30 04:59:33 PM PDT 24 Jun 30 05:13:50 PM PDT 24 9006949926 ps
T837 /workspace/coverage/default/33.sram_ctrl_multiple_keys.1746047265 Jun 30 05:00:25 PM PDT 24 Jun 30 05:05:28 PM PDT 24 9147683915 ps
T838 /workspace/coverage/default/23.sram_ctrl_regwen.2104127331 Jun 30 04:59:10 PM PDT 24 Jun 30 05:21:38 PM PDT 24 2208137909 ps
T839 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3776559650 Jun 30 04:59:47 PM PDT 24 Jun 30 04:59:50 PM PDT 24 249025916 ps
T840 /workspace/coverage/default/3.sram_ctrl_smoke.1037106270 Jun 30 04:57:34 PM PDT 24 Jun 30 04:57:45 PM PDT 24 1269018725 ps
T841 /workspace/coverage/default/14.sram_ctrl_smoke.3952685255 Jun 30 04:58:16 PM PDT 24 Jun 30 04:58:17 PM PDT 24 284591369 ps
T842 /workspace/coverage/default/4.sram_ctrl_mem_walk.2090277862 Jun 30 04:57:40 PM PDT 24 Jun 30 04:57:50 PM PDT 24 202187090 ps
T843 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2066281977 Jun 30 04:57:29 PM PDT 24 Jun 30 04:58:15 PM PDT 24 376438702 ps
T844 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.3396817264 Jun 30 04:59:05 PM PDT 24 Jun 30 05:04:50 PM PDT 24 3579389357 ps
T845 /workspace/coverage/default/20.sram_ctrl_regwen.1868608692 Jun 30 04:59:00 PM PDT 24 Jun 30 05:21:07 PM PDT 24 85064791651 ps
T115 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.480378867 Jun 30 04:57:31 PM PDT 24 Jun 30 05:00:00 PM PDT 24 8898622801 ps
T846 /workspace/coverage/default/30.sram_ctrl_smoke.468432818 Jun 30 04:59:53 PM PDT 24 Jun 30 05:00:04 PM PDT 24 1887949360 ps
T847 /workspace/coverage/default/29.sram_ctrl_smoke.3356860719 Jun 30 04:59:52 PM PDT 24 Jun 30 05:02:21 PM PDT 24 2836133225 ps
T848 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.214559211 Jun 30 05:02:04 PM PDT 24 Jun 30 05:06:44 PM PDT 24 5904988339 ps
T849 /workspace/coverage/default/6.sram_ctrl_lc_escalation.545824968 Jun 30 04:57:50 PM PDT 24 Jun 30 04:57:53 PM PDT 24 161240484 ps
T850 /workspace/coverage/default/45.sram_ctrl_lc_escalation.2446380951 Jun 30 05:02:04 PM PDT 24 Jun 30 05:02:11 PM PDT 24 2399842017 ps
T851 /workspace/coverage/default/35.sram_ctrl_partial_access.3679264073 Jun 30 05:00:50 PM PDT 24 Jun 30 05:00:52 PM PDT 24 677257116 ps
T852 /workspace/coverage/default/20.sram_ctrl_mem_walk.443642953 Jun 30 04:58:56 PM PDT 24 Jun 30 04:59:02 PM PDT 24 1500595259 ps
T853 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1340362605 Jun 30 04:57:15 PM PDT 24 Jun 30 05:01:49 PM PDT 24 10843743025 ps
T854 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.877747600 Jun 30 04:57:42 PM PDT 24 Jun 30 04:57:48 PM PDT 24 946121961 ps
T855 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1778951751 Jun 30 05:02:14 PM PDT 24 Jun 30 05:07:15 PM PDT 24 12495968321 ps
T856 /workspace/coverage/default/40.sram_ctrl_smoke.2237466884 Jun 30 05:01:20 PM PDT 24 Jun 30 05:01:38 PM PDT 24 975676560 ps
T857 /workspace/coverage/default/26.sram_ctrl_partial_access.3459939970 Jun 30 04:59:33 PM PDT 24 Jun 30 05:00:31 PM PDT 24 672883123 ps
T116 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2432164557 Jun 30 04:58:02 PM PDT 24 Jun 30 04:58:12 PM PDT 24 320430041 ps
T858 /workspace/coverage/default/42.sram_ctrl_ram_cfg.1729149912 Jun 30 05:01:42 PM PDT 24 Jun 30 05:01:43 PM PDT 24 131370420 ps
T859 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.4090426628 Jun 30 05:02:13 PM PDT 24 Jun 30 05:07:51 PM PDT 24 6872350052 ps
T860 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1329214564 Jun 30 04:59:41 PM PDT 24 Jun 30 05:04:23 PM PDT 24 10826200603 ps
T861 /workspace/coverage/default/34.sram_ctrl_bijection.1611474761 Jun 30 05:00:33 PM PDT 24 Jun 30 05:01:26 PM PDT 24 2570244423 ps
T862 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.659309400 Jun 30 04:57:48 PM PDT 24 Jun 30 04:57:52 PM PDT 24 332461151 ps
T863 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2525510362 Jun 30 04:58:02 PM PDT 24 Jun 30 05:03:46 PM PDT 24 9438395706 ps
T117 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2536742434 Jun 30 04:57:58 PM PDT 24 Jun 30 04:59:52 PM PDT 24 6322073998 ps
T864 /workspace/coverage/default/46.sram_ctrl_multiple_keys.1226600702 Jun 30 05:02:13 PM PDT 24 Jun 30 05:05:44 PM PDT 24 2712681523 ps
T865 /workspace/coverage/default/30.sram_ctrl_max_throughput.2569203701 Jun 30 05:00:00 PM PDT 24 Jun 30 05:00:07 PM PDT 24 222274456 ps
T866 /workspace/coverage/default/2.sram_ctrl_smoke.2366003559 Jun 30 04:57:35 PM PDT 24 Jun 30 04:57:48 PM PDT 24 1257946868 ps
T867 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2542301999 Jun 30 04:57:21 PM PDT 24 Jun 30 04:57:31 PM PDT 24 66480512 ps
T868 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.100937719 Jun 30 05:01:18 PM PDT 24 Jun 30 05:02:15 PM PDT 24 3494352541 ps
T869 /workspace/coverage/default/0.sram_ctrl_stress_all.1578729532 Jun 30 04:57:24 PM PDT 24 Jun 30 05:34:58 PM PDT 24 40449556071 ps
T870 /workspace/coverage/default/4.sram_ctrl_alert_test.3512939605 Jun 30 04:57:41 PM PDT 24 Jun 30 04:57:42 PM PDT 24 29205705 ps
T871 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3948097476 Jun 30 04:57:42 PM PDT 24 Jun 30 05:14:27 PM PDT 24 9318701692 ps
T872 /workspace/coverage/default/37.sram_ctrl_bijection.2453862178 Jun 30 05:00:58 PM PDT 24 Jun 30 05:02:09 PM PDT 24 39558097048 ps
T873 /workspace/coverage/default/17.sram_ctrl_max_throughput.1280016525 Jun 30 04:58:35 PM PDT 24 Jun 30 04:58:44 PM PDT 24 352414205 ps
T874 /workspace/coverage/default/43.sram_ctrl_regwen.392262895 Jun 30 05:01:52 PM PDT 24 Jun 30 05:04:32 PM PDT 24 6429612621 ps
T875 /workspace/coverage/default/43.sram_ctrl_alert_test.3599444411 Jun 30 05:01:59 PM PDT 24 Jun 30 05:02:00 PM PDT 24 23233315 ps
T876 /workspace/coverage/default/23.sram_ctrl_bijection.121859229 Jun 30 04:59:13 PM PDT 24 Jun 30 05:00:18 PM PDT 24 3183771225 ps
T877 /workspace/coverage/default/42.sram_ctrl_multiple_keys.2882958255 Jun 30 05:01:42 PM PDT 24 Jun 30 05:19:43 PM PDT 24 68368386925 ps
T878 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.125609830 Jun 30 04:57:23 PM PDT 24 Jun 30 05:01:37 PM PDT 24 2788570207 ps
T879 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2361559024 Jun 30 05:02:20 PM PDT 24 Jun 30 05:02:24 PM PDT 24 425488412 ps
T880 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3142364244 Jun 30 04:59:53 PM PDT 24 Jun 30 05:02:27 PM PDT 24 2297225829 ps
T881 /workspace/coverage/default/28.sram_ctrl_lc_escalation.1131756863 Jun 30 04:59:47 PM PDT 24 Jun 30 04:59:56 PM PDT 24 828457507 ps
T882 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1939724941 Jun 30 05:01:57 PM PDT 24 Jun 30 05:04:24 PM PDT 24 598758467 ps
T883 /workspace/coverage/default/37.sram_ctrl_partial_access.4003680790 Jun 30 05:00:55 PM PDT 24 Jun 30 05:01:11 PM PDT 24 356276870 ps
T884 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1855522364 Jun 30 04:58:02 PM PDT 24 Jun 30 04:58:08 PM PDT 24 124276157 ps
T885 /workspace/coverage/default/31.sram_ctrl_partial_access.1599831246 Jun 30 05:00:07 PM PDT 24 Jun 30 05:00:09 PM PDT 24 105959700 ps
T886 /workspace/coverage/default/9.sram_ctrl_multiple_keys.3302493147 Jun 30 04:57:50 PM PDT 24 Jun 30 05:03:50 PM PDT 24 5406634939 ps
T887 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3218698528 Jun 30 04:57:49 PM PDT 24 Jun 30 05:01:15 PM PDT 24 5028842413 ps
T888 /workspace/coverage/default/7.sram_ctrl_partial_access.2848129791 Jun 30 04:57:51 PM PDT 24 Jun 30 04:58:18 PM PDT 24 118037288 ps
T889 /workspace/coverage/default/39.sram_ctrl_regwen.1292735809 Jun 30 05:01:19 PM PDT 24 Jun 30 05:17:54 PM PDT 24 46464030147 ps
T890 /workspace/coverage/default/36.sram_ctrl_max_throughput.9512877 Jun 30 05:00:50 PM PDT 24 Jun 30 05:01:58 PM PDT 24 507582095 ps
T891 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.4088619378 Jun 30 05:02:40 PM PDT 24 Jun 30 05:07:50 PM PDT 24 12699462157 ps
T892 /workspace/coverage/default/9.sram_ctrl_executable.1400187538 Jun 30 04:57:59 PM PDT 24 Jun 30 05:09:23 PM PDT 24 2466236552 ps
T893 /workspace/coverage/default/40.sram_ctrl_regwen.4016321949 Jun 30 05:01:27 PM PDT 24 Jun 30 05:12:44 PM PDT 24 28833848050 ps
T894 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.203169893 Jun 30 04:58:33 PM PDT 24 Jun 30 04:58:37 PM PDT 24 165692186 ps
T895 /workspace/coverage/default/4.sram_ctrl_ram_cfg.993247063 Jun 30 04:57:44 PM PDT 24 Jun 30 04:57:45 PM PDT 24 127485683 ps
T896 /workspace/coverage/default/15.sram_ctrl_max_throughput.765881857 Jun 30 04:58:25 PM PDT 24 Jun 30 04:58:56 PM PDT 24 229390304 ps
T897 /workspace/coverage/default/40.sram_ctrl_mem_walk.647029702 Jun 30 05:01:26 PM PDT 24 Jun 30 05:01:37 PM PDT 24 1821544986 ps
T898 /workspace/coverage/default/5.sram_ctrl_lc_escalation.3184730054 Jun 30 04:57:42 PM PDT 24 Jun 30 04:57:50 PM PDT 24 2526665158 ps
T899 /workspace/coverage/default/31.sram_ctrl_mem_walk.384970433 Jun 30 05:00:20 PM PDT 24 Jun 30 05:00:27 PM PDT 24 1337034642 ps
T900 /workspace/coverage/default/29.sram_ctrl_executable.2751371400 Jun 30 04:59:54 PM PDT 24 Jun 30 05:23:04 PM PDT 24 14067144181 ps
T901 /workspace/coverage/default/20.sram_ctrl_executable.3444027666 Jun 30 04:59:03 PM PDT 24 Jun 30 05:19:20 PM PDT 24 101087804622 ps
T902 /workspace/coverage/default/0.sram_ctrl_multiple_keys.560808571 Jun 30 04:57:16 PM PDT 24 Jun 30 05:09:25 PM PDT 24 3977560898 ps
T903 /workspace/coverage/default/24.sram_ctrl_smoke.1514627720 Jun 30 04:59:17 PM PDT 24 Jun 30 04:59:22 PM PDT 24 905832240 ps
T904 /workspace/coverage/default/10.sram_ctrl_max_throughput.2166574659 Jun 30 04:57:54 PM PDT 24 Jun 30 04:57:56 PM PDT 24 39334334 ps
T905 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1793573884 Jun 30 04:57:49 PM PDT 24 Jun 30 05:01:00 PM PDT 24 6065072417 ps
T906 /workspace/coverage/default/37.sram_ctrl_stress_all.1594043492 Jun 30 05:01:04 PM PDT 24 Jun 30 07:25:56 PM PDT 24 73885323396 ps
T907 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.382642895 Jun 30 05:02:57 PM PDT 24 Jun 30 05:03:01 PM PDT 24 244761954 ps
T908 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3283184917 Jun 30 04:58:10 PM PDT 24 Jun 30 05:10:56 PM PDT 24 6392179087 ps
T909 /workspace/coverage/default/42.sram_ctrl_stress_all.849777267 Jun 30 05:01:44 PM PDT 24 Jun 30 06:07:48 PM PDT 24 234993831804 ps
T910 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2335074479 Jun 30 04:59:10 PM PDT 24 Jun 30 04:59:14 PM PDT 24 99668246 ps
T911 /workspace/coverage/default/36.sram_ctrl_partial_access.3411102008 Jun 30 05:00:53 PM PDT 24 Jun 30 05:01:11 PM PDT 24 861174154 ps
T912 /workspace/coverage/default/46.sram_ctrl_bijection.1892450964 Jun 30 05:02:13 PM PDT 24 Jun 30 05:03:27 PM PDT 24 4313968946 ps
T913 /workspace/coverage/default/49.sram_ctrl_regwen.4072774043 Jun 30 05:02:53 PM PDT 24 Jun 30 05:36:33 PM PDT 24 3186167331 ps
T914 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3342183982 Jun 30 04:58:47 PM PDT 24 Jun 30 04:58:55 PM PDT 24 1237774569 ps
T915 /workspace/coverage/default/17.sram_ctrl_alert_test.141181403 Jun 30 04:58:40 PM PDT 24 Jun 30 04:58:41 PM PDT 24 19034928 ps
T916 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3867630494 Jun 30 05:00:23 PM PDT 24 Jun 30 05:03:44 PM PDT 24 4237561968 ps
T917 /workspace/coverage/default/23.sram_ctrl_multiple_keys.4116112554 Jun 30 04:59:11 PM PDT 24 Jun 30 05:09:04 PM PDT 24 7351216826 ps
T918 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4002754911 Jun 30 05:00:33 PM PDT 24 Jun 30 05:05:59 PM PDT 24 10032077491 ps
T919 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3256417611 Jun 30 05:01:04 PM PDT 24 Jun 30 05:07:30 PM PDT 24 10406092298 ps
T920 /workspace/coverage/default/27.sram_ctrl_max_throughput.850346948 Jun 30 04:59:36 PM PDT 24 Jun 30 04:59:53 PM PDT 24 75524524 ps
T921 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3476871874 Jun 30 04:59:59 PM PDT 24 Jun 30 05:00:47 PM PDT 24 763159834 ps
T922 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.4158536729 Jun 30 04:57:34 PM PDT 24 Jun 30 04:57:41 PM PDT 24 896200924 ps
T923 /workspace/coverage/default/20.sram_ctrl_alert_test.3841527066 Jun 30 04:58:58 PM PDT 24 Jun 30 04:58:59 PM PDT 24 34415286 ps
T924 /workspace/coverage/default/6.sram_ctrl_bijection.2068673930 Jun 30 04:57:42 PM PDT 24 Jun 30 04:57:58 PM PDT 24 2232639355 ps
T925 /workspace/coverage/default/4.sram_ctrl_regwen.2655355425 Jun 30 04:57:43 PM PDT 24 Jun 30 04:57:59 PM PDT 24 1219168607 ps
T926 /workspace/coverage/default/7.sram_ctrl_bijection.1576926145 Jun 30 04:57:48 PM PDT 24 Jun 30 04:58:38 PM PDT 24 1624293614 ps
T927 /workspace/coverage/default/41.sram_ctrl_lc_escalation.73229688 Jun 30 05:01:34 PM PDT 24 Jun 30 05:01:36 PM PDT 24 144300212 ps
T928 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3988400968 Jun 30 04:58:16 PM PDT 24 Jun 30 04:58:30 PM PDT 24 1810280507 ps
T929 /workspace/coverage/default/37.sram_ctrl_max_throughput.110655559 Jun 30 05:00:58 PM PDT 24 Jun 30 05:02:12 PM PDT 24 456262942 ps
T930 /workspace/coverage/default/13.sram_ctrl_regwen.2696314569 Jun 30 04:58:10 PM PDT 24 Jun 30 05:11:48 PM PDT 24 33694324851 ps
T931 /workspace/coverage/default/28.sram_ctrl_stress_all.4268813642 Jun 30 04:59:53 PM PDT 24 Jun 30 05:28:41 PM PDT 24 84273118743 ps
T932 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1696561360 Jun 30 04:58:44 PM PDT 24 Jun 30 04:58:47 PM PDT 24 336296580 ps
T933 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1330716980 Jun 30 04:55:53 PM PDT 24 Jun 30 04:55:58 PM PDT 24 681951505 ps
T63 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2298928723 Jun 30 04:55:03 PM PDT 24 Jun 30 04:55:05 PM PDT 24 121787778 ps
T66 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2513898951 Jun 30 04:55:53 PM PDT 24 Jun 30 04:55:54 PM PDT 24 70377600 ps
T64 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3140750039 Jun 30 04:54:47 PM PDT 24 Jun 30 04:54:50 PM PDT 24 195103855 ps
T108 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.892816581 Jun 30 04:55:51 PM PDT 24 Jun 30 04:55:52 PM PDT 24 85360879 ps
T65 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2683356428 Jun 30 04:55:18 PM PDT 24 Jun 30 04:55:20 PM PDT 24 337593756 ps
T934 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2487594868 Jun 30 04:55:30 PM PDT 24 Jun 30 04:55:33 PM PDT 24 88275370 ps
T79 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.623891726 Jun 30 04:55:17 PM PDT 24 Jun 30 04:55:19 PM PDT 24 1429985510 ps
T80 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.83983712 Jun 30 04:55:18 PM PDT 24 Jun 30 04:55:19 PM PDT 24 263570797 ps
T935 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2162678321 Jun 30 04:55:43 PM PDT 24 Jun 30 04:55:49 PM PDT 24 216442399 ps
T936 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4098038309 Jun 30 04:55:44 PM PDT 24 Jun 30 04:55:46 PM PDT 24 134456343 ps
T81 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2459819938 Jun 30 04:55:17 PM PDT 24 Jun 30 04:55:18 PM PDT 24 67876592 ps
T937 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.471914986 Jun 30 04:55:04 PM PDT 24 Jun 30 04:55:08 PM PDT 24 424409909 ps
T101 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1608223872 Jun 30 04:55:40 PM PDT 24 Jun 30 04:55:41 PM PDT 24 18067235 ps
T102 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1114410306 Jun 30 04:55:41 PM PDT 24 Jun 30 04:55:42 PM PDT 24 99702255 ps
T82 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2812656822 Jun 30 04:55:02 PM PDT 24 Jun 30 04:55:05 PM PDT 24 347111874 ps
T938 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.931703603 Jun 30 04:55:31 PM PDT 24 Jun 30 04:55:33 PM PDT 24 62871713 ps
T939 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1643229271 Jun 30 04:55:38 PM PDT 24 Jun 30 04:55:40 PM PDT 24 102762157 ps
T83 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.428173043 Jun 30 04:54:54 PM PDT 24 Jun 30 04:54:55 PM PDT 24 16472025 ps
T134 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2288256599 Jun 30 04:54:55 PM PDT 24 Jun 30 04:54:57 PM PDT 24 143036087 ps
T940 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1898410368 Jun 30 04:55:40 PM PDT 24 Jun 30 04:55:41 PM PDT 24 29578282 ps
T84 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1640092857 Jun 30 04:54:55 PM PDT 24 Jun 30 04:54:56 PM PDT 24 20033779 ps
T127 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.356656414 Jun 30 04:55:41 PM PDT 24 Jun 30 04:55:43 PM PDT 24 202117557 ps
T85 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.365644636 Jun 30 04:55:19 PM PDT 24 Jun 30 04:55:20 PM PDT 24 16566645 ps
T86 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4036369874 Jun 30 04:55:11 PM PDT 24 Jun 30 04:55:13 PM PDT 24 50391752 ps
T87 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1599139542 Jun 30 04:55:02 PM PDT 24 Jun 30 04:55:03 PM PDT 24 21371845 ps
T88 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.499300763 Jun 30 04:55:46 PM PDT 24 Jun 30 04:55:47 PM PDT 24 116291750 ps
T128 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1424602046 Jun 30 04:55:24 PM PDT 24 Jun 30 04:55:28 PM PDT 24 663655276 ps
T89 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3145420446 Jun 30 04:55:24 PM PDT 24 Jun 30 04:55:27 PM PDT 24 827166617 ps
T941 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.505263371 Jun 30 04:55:46 PM PDT 24 Jun 30 04:55:50 PM PDT 24 1762594955 ps
T131 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3182637709 Jun 30 04:55:18 PM PDT 24 Jun 30 04:55:20 PM PDT 24 588235453 ps
T942 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1499019265 Jun 30 04:54:54 PM PDT 24 Jun 30 04:54:55 PM PDT 24 67095085 ps
T943 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2250619919 Jun 30 04:55:10 PM PDT 24 Jun 30 04:55:11 PM PDT 24 109367891 ps
T944 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3486642000 Jun 30 04:55:48 PM PDT 24 Jun 30 04:55:49 PM PDT 24 16538008 ps
T945 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2225582285 Jun 30 04:55:17 PM PDT 24 Jun 30 04:55:20 PM PDT 24 480864863 ps
T946 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3020907799 Jun 30 04:55:52 PM PDT 24 Jun 30 04:55:53 PM PDT 24 37455129 ps
T947 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2628205021 Jun 30 04:55:24 PM PDT 24 Jun 30 04:55:25 PM PDT 24 71729378 ps
T948 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4003705170 Jun 30 04:55:45 PM PDT 24 Jun 30 04:55:45 PM PDT 24 22591719 ps
T103 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1001152237 Jun 30 04:54:54 PM PDT 24 Jun 30 04:54:55 PM PDT 24 36576101 ps
T949 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4277699891 Jun 30 04:55:17 PM PDT 24 Jun 30 04:55:20 PM PDT 24 1903343939 ps
T950 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1566009274 Jun 30 04:55:53 PM PDT 24 Jun 30 04:55:55 PM PDT 24 63576843 ps
T133 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4071548732 Jun 30 04:55:25 PM PDT 24 Jun 30 04:55:27 PM PDT 24 210692524 ps
T90 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3327561142 Jun 30 04:55:38 PM PDT 24 Jun 30 04:55:41 PM PDT 24 275331399 ps
T951 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.979550546 Jun 30 04:55:39 PM PDT 24 Jun 30 04:55:40 PM PDT 24 24908840 ps
T104 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2730191891 Jun 30 04:55:24 PM PDT 24 Jun 30 04:55:26 PM PDT 24 86053091 ps
T952 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3923814548 Jun 30 04:55:32 PM PDT 24 Jun 30 04:55:35 PM PDT 24 27985569 ps
T953 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2556242010 Jun 30 04:55:40 PM PDT 24 Jun 30 04:55:42 PM PDT 24 177521331 ps
T954 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.277159112 Jun 30 04:55:52 PM PDT 24 Jun 30 04:55:55 PM PDT 24 71657568 ps
T955 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.229021087 Jun 30 04:55:17 PM PDT 24 Jun 30 04:55:20 PM PDT 24 36278353 ps
T956 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.27526977 Jun 30 04:55:23 PM PDT 24 Jun 30 04:55:28 PM PDT 24 737369850 ps
T957 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3947707982 Jun 30 04:54:56 PM PDT 24 Jun 30 04:54:57 PM PDT 24 64224482 ps
T132 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.673296726 Jun 30 04:55:52 PM PDT 24 Jun 30 04:55:55 PM PDT 24 205802020 ps
T137 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.299056947 Jun 30 04:55:33 PM PDT 24 Jun 30 04:55:36 PM PDT 24 638430104 ps
T91 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2205168376 Jun 30 04:54:54 PM PDT 24 Jun 30 04:54:56 PM PDT 24 848486062 ps
T958 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.825898836 Jun 30 04:55:47 PM PDT 24 Jun 30 04:55:50 PM PDT 24 121860899 ps
T959 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3240772736 Jun 30 04:55:33 PM PDT 24 Jun 30 04:55:34 PM PDT 24 29758166 ps
T129 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3813770588 Jun 30 04:55:09 PM PDT 24 Jun 30 04:55:13 PM PDT 24 213496297 ps
T92 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.229283971 Jun 30 04:55:33 PM PDT 24 Jun 30 04:55:36 PM PDT 24 381746811 ps
T960 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3202373015 Jun 30 04:55:45 PM PDT 24 Jun 30 04:55:46 PM PDT 24 50085860 ps
T961 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2203273325 Jun 30 04:55:11 PM PDT 24 Jun 30 04:55:12 PM PDT 24 35445014 ps
T962 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2451335704 Jun 30 04:55:45 PM PDT 24 Jun 30 04:55:47 PM PDT 24 133611678 ps
T97 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3103778603 Jun 30 04:55:43 PM PDT 24 Jun 30 04:55:47 PM PDT 24 421468066 ps
T963 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3132001541 Jun 30 04:55:18 PM PDT 24 Jun 30 04:55:19 PM PDT 24 46095128 ps
T964 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3882591168 Jun 30 04:55:25 PM PDT 24 Jun 30 04:55:26 PM PDT 24 22233528 ps
T965 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1064644224 Jun 30 04:55:03 PM PDT 24 Jun 30 04:55:05 PM PDT 24 101906990 ps
T966 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4163464018 Jun 30 04:54:54 PM PDT 24 Jun 30 04:54:55 PM PDT 24 13703072 ps
T967 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2542591685 Jun 30 04:54:54 PM PDT 24 Jun 30 04:54:56 PM PDT 24 65885124 ps
T968 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1889242759 Jun 30 04:55:04 PM PDT 24 Jun 30 04:55:05 PM PDT 24 15764091 ps
T969 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2034001373 Jun 30 04:54:55 PM PDT 24 Jun 30 04:54:57 PM PDT 24 254293962 ps
T970 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3279362173 Jun 30 04:55:33 PM PDT 24 Jun 30 04:55:35 PM PDT 24 218129304 ps
T971 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1613540292 Jun 30 04:55:54 PM PDT 24 Jun 30 04:55:56 PM PDT 24 80778238 ps
T130 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1727845289 Jun 30 04:55:32 PM PDT 24 Jun 30 04:55:35 PM PDT 24 524078557 ps
T98 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2494411953 Jun 30 04:55:31 PM PDT 24 Jun 30 04:55:34 PM PDT 24 462842249 ps
T972 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4152503976 Jun 30 04:55:18 PM PDT 24 Jun 30 04:55:22 PM PDT 24 84958160 ps
T973 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3386660046 Jun 30 04:55:42 PM PDT 24 Jun 30 04:55:44 PM PDT 24 17990283 ps
T974 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2908136032 Jun 30 04:55:10 PM PDT 24 Jun 30 04:55:15 PM PDT 24 2853900584 ps
T135 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3181133146 Jun 30 04:55:39 PM PDT 24 Jun 30 04:55:42 PM PDT 24 2388018616 ps
T975 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3914118592 Jun 30 04:55:38 PM PDT 24 Jun 30 04:55:42 PM PDT 24 40782930 ps
T976 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.381195272 Jun 30 04:55:18 PM PDT 24 Jun 30 04:55:19 PM PDT 24 51590786 ps
T977 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3671062193 Jun 30 04:55:38 PM PDT 24 Jun 30 04:55:41 PM PDT 24 187022609 ps
T99 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.839192781 Jun 30 04:55:46 PM PDT 24 Jun 30 04:55:50 PM PDT 24 521674194 ps
T978 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.759029229 Jun 30 04:55:03 PM PDT 24 Jun 30 04:55:05 PM PDT 24 126268408 ps
T100 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1833152393 Jun 30 04:55:02 PM PDT 24 Jun 30 04:55:07 PM PDT 24 3014974903 ps
T979 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1446012092 Jun 30 04:55:33 PM PDT 24 Jun 30 04:55:35 PM PDT 24 233840846 ps
T980 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2917678281 Jun 30 04:55:39 PM PDT 24 Jun 30 04:55:42 PM PDT 24 716928152 ps
T981 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.837841240 Jun 30 04:55:39 PM PDT 24 Jun 30 04:55:40 PM PDT 24 35902333 ps
T982 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1622113991 Jun 30 04:55:51 PM PDT 24 Jun 30 04:55:54 PM PDT 24 390581169 ps
T983 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1800338469 Jun 30 04:55:39 PM PDT 24 Jun 30 04:55:40 PM PDT 24 42748160 ps
T984 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.831946557 Jun 30 04:55:39 PM PDT 24 Jun 30 04:55:43 PM PDT 24 1951577991 ps
T985 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3168603166 Jun 30 04:55:12 PM PDT 24 Jun 30 04:55:13 PM PDT 24 14934657 ps
T986 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.557086218 Jun 30 04:55:02 PM PDT 24 Jun 30 04:55:03 PM PDT 24 73923983 ps
T987 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1983664091 Jun 30 04:55:51 PM PDT 24 Jun 30 04:55:52 PM PDT 24 137831909 ps
T138 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2497520947 Jun 30 04:55:47 PM PDT 24 Jun 30 04:55:49 PM PDT 24 251918081 ps
T988 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1463444687 Jun 30 04:55:31 PM PDT 24 Jun 30 04:55:34 PM PDT 24 654148875 ps
T989 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1677664844 Jun 30 04:55:43 PM PDT 24 Jun 30 04:55:44 PM PDT 24 14397861 ps
T990 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4228934129 Jun 30 04:55:24 PM PDT 24 Jun 30 04:55:25 PM PDT 24 51872961 ps
T991 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2137694493 Jun 30 04:55:18 PM PDT 24 Jun 30 04:55:19 PM PDT 24 18307715 ps
T992 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2913497995 Jun 30 04:55:10 PM PDT 24 Jun 30 04:55:11 PM PDT 24 15656498 ps
T993 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.998067530 Jun 30 04:54:55 PM PDT 24 Jun 30 04:55:01 PM PDT 24 311044000 ps
T994 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2513550095 Jun 30 04:55:24 PM PDT 24 Jun 30 04:55:27 PM PDT 24 48149468 ps
T995 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1395564013 Jun 30 04:55:19 PM PDT 24 Jun 30 04:55:24 PM PDT 24 260357395 ps
T996 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2507478606 Jun 30 04:55:23 PM PDT 24 Jun 30 04:55:24 PM PDT 24 15141735 ps
T997 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3668503024 Jun 30 04:55:31 PM PDT 24 Jun 30 04:55:32 PM PDT 24 44946265 ps
T998 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1116649554 Jun 30 04:55:52 PM PDT 24 Jun 30 04:55:57 PM PDT 24 1506144858 ps
T999 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.639168162 Jun 30 04:55:32 PM PDT 24 Jun 30 04:55:33 PM PDT 24 45664012 ps
T1000 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1053012613 Jun 30 04:55:38 PM PDT 24 Jun 30 04:55:39 PM PDT 24 112512846 ps
T1001 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4293440395 Jun 30 04:55:03 PM PDT 24 Jun 30 04:55:04 PM PDT 24 96291263 ps
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