Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	138280754	1			T1	21104		T2	292058		T3	436190
instr_valid_dis	110669975	1			T1	21104		T2	292058		T3	436190
instr_en	18040910	1			T34	94470		T71	201892		T24	364212

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10259274	1			T22	11160		T34	90484		T23	144086
sram_ifetch_valid_disable	108861823	1			T1	21104		T2	292058		T3	436190
sram_ifetch_enable	19159657	1			T22	56426		T34	114874		T23	171556

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	138280754	1			T1	21104		T2	292058		T3	436190
hw_debug_en_valid_off	108917114	1			T1	21104		T2	292058		T3	436190
hw_debug_en_on	19788182	1			T22	22744		T34	189172		T23	92694

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	108861823	1			T1	21104		T2	292058		T3	436190
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97408083	1			T1	21104		T2	292058		T3	436190
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7568237	1			T34	22316		T71	29870		T24	147982
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3700124	1			T22	11160		T34	15360		T23	122954
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1822178	1			T22	11160		T34	15360		T23	107952
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1300578	1			T24	20000		T143	60658		T148	13354
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4655184	1			T34	75124		T23	21132		T35	29946
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2046654	1			T23	11478		T35	29946		T71	63592
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1864446	1			T34	55908		T24	4016		T143	4756
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7492430	1			T34	11412		T23	31188		T35	25304
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3257802	1			T34	11412		T23	31188		T35	25304
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3147842	1			T24	20088		T79	55850		T143	8888

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	6869357	1			T34	16246		T71	121614		T24	189828
lc_exec_en	7640568	1			T22	22744		T34	102636		T23	40374
valid_exec_dis	105312447	1			T1	21104		T2	292058		T3	436190
invalid_exec_dis	29418931	1			T22	67586		T34	205358		T23	315642