Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	41337400	1			T1	9588		T2	132689		T3	39889
triple_byte_access	2503254	1			T1	191		T2	2656		T3	35558
halfword_access	3753123	1			T1	283		T2	3989		T3	53397
byte_access	5016733	1			T1	390		T2	5351		T3	71455
zero_access	1259669	1			T1	100		T2	1344		T3	17796

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26886398

1

T1

5313

T2

73022

T3

108659

auto[1]

26983781

1

T1

5239

T2

73007

T3

109436

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	20623663	1			T1	4802		T2	66424		T3	20029
auto[0]	triple_byte_access	1247749	1			T1	100		T2	1253		T3	17682
auto[0]	halfword_access	1872541	1			T1	153		T2	1967		T3	26447
auto[0]	byte_access	2508825	1			T1	205		T2	2699		T3	35624
auto[0]	zero_access	633620	1			T1	53		T2	679		T3	8877
auto[1]	word_access	20713737	1			T1	4786		T2	66265		T3	19860
auto[1]	triple_byte_access	1255505	1			T1	91		T2	1403		T3	17876
auto[1]	halfword_access	1880582	1			T1	130		T2	2022		T3	26950
auto[1]	byte_access	2507908	1			T1	185		T2	2652		T3	35831
auto[1]	zero_access	626049	1			T1	47		T2	665		T3	8919