| T794 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1301016395 |
|
|
Jul 01 11:46:41 AM PDT 24 |
Jul 01 11:50:15 AM PDT 24 |
2167161969 ps |
| T795 |
/workspace/coverage/default/9.sram_ctrl_executable.2429046800 |
|
|
Jul 01 11:39:11 AM PDT 24 |
Jul 01 11:54:15 AM PDT 24 |
14728371712 ps |
| T796 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1467443218 |
|
|
Jul 01 11:43:07 AM PDT 24 |
Jul 01 11:46:50 AM PDT 24 |
13001173533 ps |
| T797 |
/workspace/coverage/default/1.sram_ctrl_executable.1962500560 |
|
|
Jul 01 11:37:12 AM PDT 24 |
Jul 01 11:39:33 AM PDT 24 |
2630319704 ps |
| T798 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.772013995 |
|
|
Jul 01 11:41:35 AM PDT 24 |
Jul 01 12:07:34 PM PDT 24 |
9020586073 ps |
| T799 |
/workspace/coverage/default/10.sram_ctrl_regwen.2681417522 |
|
|
Jul 01 11:39:26 AM PDT 24 |
Jul 01 11:52:35 AM PDT 24 |
2497473789 ps |
| T800 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1733149830 |
|
|
Jul 01 11:46:31 AM PDT 24 |
Jul 01 11:46:33 AM PDT 24 |
87630045 ps |
| T801 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2947944943 |
|
|
Jul 01 11:46:16 AM PDT 24 |
Jul 01 11:46:21 AM PDT 24 |
192501044 ps |
| T802 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1225541172 |
|
|
Jul 01 11:45:04 AM PDT 24 |
Jul 01 11:48:20 AM PDT 24 |
11637557574 ps |
| T803 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3970129270 |
|
|
Jul 01 11:37:08 AM PDT 24 |
Jul 01 11:37:10 AM PDT 24 |
37004021 ps |
| T804 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1579803713 |
|
|
Jul 01 11:41:57 AM PDT 24 |
Jul 01 11:42:17 AM PDT 24 |
11289836589 ps |
| T805 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2699100278 |
|
|
Jul 01 11:46:10 AM PDT 24 |
Jul 01 11:48:14 AM PDT 24 |
131961930 ps |
| T806 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3004857113 |
|
|
Jul 01 11:46:27 AM PDT 24 |
Jul 01 11:49:16 AM PDT 24 |
1739412052 ps |
| T807 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2093459726 |
|
|
Jul 01 11:40:13 AM PDT 24 |
Jul 01 11:40:17 AM PDT 24 |
865180759 ps |
| T808 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2389709890 |
|
|
Jul 01 11:43:38 AM PDT 24 |
Jul 01 11:43:45 AM PDT 24 |
760773250 ps |
| T809 |
/workspace/coverage/default/11.sram_ctrl_regwen.1859410525 |
|
|
Jul 01 11:39:32 AM PDT 24 |
Jul 01 11:43:49 AM PDT 24 |
11375203935 ps |
| T810 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3428999230 |
|
|
Jul 01 11:37:24 AM PDT 24 |
Jul 01 11:42:00 AM PDT 24 |
3000800712 ps |
| T811 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1772930098 |
|
|
Jul 01 11:45:49 AM PDT 24 |
Jul 01 12:02:38 PM PDT 24 |
3335830332 ps |
| T812 |
/workspace/coverage/default/42.sram_ctrl_smoke.3152090708 |
|
|
Jul 01 11:46:22 AM PDT 24 |
Jul 01 11:46:33 AM PDT 24 |
379238274 ps |
| T813 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.252933996 |
|
|
Jul 01 11:45:33 AM PDT 24 |
Jul 01 11:45:39 AM PDT 24 |
376598524 ps |
| T814 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1240683197 |
|
|
Jul 01 11:41:29 AM PDT 24 |
Jul 01 11:42:36 AM PDT 24 |
116443036 ps |
| T815 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2865137819 |
|
|
Jul 01 11:42:22 AM PDT 24 |
Jul 01 11:42:25 AM PDT 24 |
66311939 ps |
| T52 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1249577867 |
|
|
Jul 01 11:44:23 AM PDT 24 |
Jul 01 11:44:52 AM PDT 24 |
990664799 ps |
| T816 |
/workspace/coverage/default/29.sram_ctrl_executable.3049257477 |
|
|
Jul 01 11:43:29 AM PDT 24 |
Jul 01 11:58:10 AM PDT 24 |
200897626596 ps |
| T817 |
/workspace/coverage/default/5.sram_ctrl_stress_all.3528500040 |
|
|
Jul 01 11:38:19 AM PDT 24 |
Jul 01 12:17:07 PM PDT 24 |
23881745272 ps |
| T818 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.2327355137 |
|
|
Jul 01 11:41:15 AM PDT 24 |
Jul 01 11:57:14 AM PDT 24 |
89263327289 ps |
| T819 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3618318425 |
|
|
Jul 01 11:44:04 AM PDT 24 |
Jul 01 11:44:08 AM PDT 24 |
301143926 ps |
| T820 |
/workspace/coverage/default/26.sram_ctrl_partial_access.1660128591 |
|
|
Jul 01 11:42:47 AM PDT 24 |
Jul 01 11:42:50 AM PDT 24 |
101480317 ps |
| T821 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2153220811 |
|
|
Jul 01 11:43:31 AM PDT 24 |
Jul 01 11:43:42 AM PDT 24 |
913777383 ps |
| T822 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3917554422 |
|
|
Jul 01 11:43:11 AM PDT 24 |
Jul 01 11:52:29 AM PDT 24 |
2491885338 ps |
| T823 |
/workspace/coverage/default/19.sram_ctrl_smoke.1924064862 |
|
|
Jul 01 11:41:14 AM PDT 24 |
Jul 01 11:41:30 AM PDT 24 |
690124404 ps |
| T824 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2228263414 |
|
|
Jul 01 11:46:21 AM PDT 24 |
Jul 01 11:46:26 AM PDT 24 |
391123117 ps |
| T825 |
/workspace/coverage/default/20.sram_ctrl_bijection.254880635 |
|
|
Jul 01 11:41:23 AM PDT 24 |
Jul 01 11:41:47 AM PDT 24 |
1082633453 ps |
| T826 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3335961543 |
|
|
Jul 01 11:38:07 AM PDT 24 |
Jul 01 11:39:02 AM PDT 24 |
488042555 ps |
| T827 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3604490815 |
|
|
Jul 01 11:38:48 AM PDT 24 |
Jul 01 12:50:16 PM PDT 24 |
144093438976 ps |
| T828 |
/workspace/coverage/default/35.sram_ctrl_smoke.3022897020 |
|
|
Jul 01 11:44:55 AM PDT 24 |
Jul 01 11:45:40 AM PDT 24 |
165135893 ps |
| T829 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.651130312 |
|
|
Jul 01 11:46:41 AM PDT 24 |
Jul 01 11:46:48 AM PDT 24 |
941904312 ps |
| T830 |
/workspace/coverage/default/42.sram_ctrl_executable.1236538225 |
|
|
Jul 01 11:46:24 AM PDT 24 |
Jul 01 12:10:37 PM PDT 24 |
3033344107 ps |
| T831 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2127534117 |
|
|
Jul 01 11:45:49 AM PDT 24 |
Jul 01 11:49:15 AM PDT 24 |
1972782823 ps |
| T832 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1080128153 |
|
|
Jul 01 11:43:30 AM PDT 24 |
Jul 01 11:43:39 AM PDT 24 |
61163527 ps |
| T833 |
/workspace/coverage/default/4.sram_ctrl_smoke.3524568839 |
|
|
Jul 01 11:37:52 AM PDT 24 |
Jul 01 11:38:15 AM PDT 24 |
263046566 ps |
| T834 |
/workspace/coverage/default/7.sram_ctrl_alert_test.1227696970 |
|
|
Jul 01 11:38:49 AM PDT 24 |
Jul 01 11:38:50 AM PDT 24 |
22180178 ps |
| T835 |
/workspace/coverage/default/28.sram_ctrl_partial_access.421474179 |
|
|
Jul 01 11:43:06 AM PDT 24 |
Jul 01 11:45:31 AM PDT 24 |
709797936 ps |
| T836 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2890793512 |
|
|
Jul 01 11:46:57 AM PDT 24 |
Jul 01 11:47:05 AM PDT 24 |
258733437 ps |
| T837 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1771492293 |
|
|
Jul 01 11:39:11 AM PDT 24 |
Jul 01 12:10:56 PM PDT 24 |
87462225502 ps |
| T838 |
/workspace/coverage/default/27.sram_ctrl_stress_all.1855376046 |
|
|
Jul 01 11:43:01 AM PDT 24 |
Jul 01 12:25:59 PM PDT 24 |
51587094012 ps |
| T839 |
/workspace/coverage/default/27.sram_ctrl_executable.896493866 |
|
|
Jul 01 11:43:02 AM PDT 24 |
Jul 01 12:09:26 PM PDT 24 |
13258396449 ps |
| T840 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.4001378848 |
|
|
Jul 01 11:42:06 AM PDT 24 |
Jul 01 11:42:11 AM PDT 24 |
55475897 ps |
| T841 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2253966736 |
|
|
Jul 01 11:44:23 AM PDT 24 |
Jul 01 11:44:25 AM PDT 24 |
100462839 ps |
| T842 |
/workspace/coverage/default/47.sram_ctrl_executable.3473189403 |
|
|
Jul 01 11:47:29 AM PDT 24 |
Jul 01 11:50:44 AM PDT 24 |
13945276265 ps |
| T843 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.745464134 |
|
|
Jul 01 11:47:08 AM PDT 24 |
Jul 01 11:50:25 AM PDT 24 |
15098999560 ps |
| T844 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3588068267 |
|
|
Jul 01 11:47:25 AM PDT 24 |
Jul 01 11:47:28 AM PDT 24 |
46657110 ps |
| T845 |
/workspace/coverage/default/0.sram_ctrl_regwen.2153467780 |
|
|
Jul 01 11:37:03 AM PDT 24 |
Jul 01 11:40:52 AM PDT 24 |
2708042150 ps |
| T846 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.891697818 |
|
|
Jul 01 11:44:10 AM PDT 24 |
Jul 01 11:45:37 AM PDT 24 |
3990973992 ps |
| T847 |
/workspace/coverage/default/24.sram_ctrl_executable.1515628597 |
|
|
Jul 01 11:42:22 AM PDT 24 |
Jul 01 11:58:46 AM PDT 24 |
46535849053 ps |
| T848 |
/workspace/coverage/default/1.sram_ctrl_smoke.883828128 |
|
|
Jul 01 11:37:09 AM PDT 24 |
Jul 01 11:37:14 AM PDT 24 |
219095176 ps |
| T849 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1535584211 |
|
|
Jul 01 11:47:29 AM PDT 24 |
Jul 01 11:47:30 AM PDT 24 |
82542665 ps |
| T850 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1679247214 |
|
|
Jul 01 11:36:58 AM PDT 24 |
Jul 01 11:37:05 AM PDT 24 |
1311393366 ps |
| T851 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1586768392 |
|
|
Jul 01 11:41:40 AM PDT 24 |
Jul 01 11:54:57 AM PDT 24 |
58497490588 ps |
| T852 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2092939767 |
|
|
Jul 01 11:39:02 AM PDT 24 |
Jul 01 11:39:04 AM PDT 24 |
55686547 ps |
| T853 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2775060935 |
|
|
Jul 01 11:40:11 AM PDT 24 |
Jul 01 11:44:29 AM PDT 24 |
14094167749 ps |
| T854 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1201027712 |
|
|
Jul 01 11:38:57 AM PDT 24 |
Jul 01 11:39:00 AM PDT 24 |
28699855 ps |
| T855 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2456520144 |
|
|
Jul 01 11:41:20 AM PDT 24 |
Jul 01 11:47:50 AM PDT 24 |
21706869021 ps |
| T856 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.4260527481 |
|
|
Jul 01 11:44:41 AM PDT 24 |
Jul 01 11:44:43 AM PDT 24 |
183680652 ps |
| T857 |
/workspace/coverage/default/41.sram_ctrl_executable.2879158900 |
|
|
Jul 01 11:46:09 AM PDT 24 |
Jul 01 11:53:40 AM PDT 24 |
9966794060 ps |
| T858 |
/workspace/coverage/default/24.sram_ctrl_smoke.4229954612 |
|
|
Jul 01 11:42:11 AM PDT 24 |
Jul 01 11:42:23 AM PDT 24 |
956211881 ps |
| T859 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.1222623445 |
|
|
Jul 01 11:45:28 AM PDT 24 |
Jul 01 11:45:50 AM PDT 24 |
73149029 ps |
| T860 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1773175075 |
|
|
Jul 01 11:41:57 AM PDT 24 |
Jul 01 11:42:23 AM PDT 24 |
1247514973 ps |
| T861 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3310303991 |
|
|
Jul 01 11:41:16 AM PDT 24 |
Jul 01 11:41:27 AM PDT 24 |
381262620 ps |
| T862 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.1586086138 |
|
|
Jul 01 11:44:28 AM PDT 24 |
Jul 01 11:44:34 AM PDT 24 |
235763350 ps |
| T863 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.222384868 |
|
|
Jul 01 11:45:48 AM PDT 24 |
Jul 01 11:49:46 AM PDT 24 |
3228328533 ps |
| T864 |
/workspace/coverage/default/1.sram_ctrl_regwen.3480375594 |
|
|
Jul 01 11:37:18 AM PDT 24 |
Jul 01 11:56:47 AM PDT 24 |
10573374927 ps |
| T865 |
/workspace/coverage/default/14.sram_ctrl_bijection.136349665 |
|
|
Jul 01 11:40:06 AM PDT 24 |
Jul 01 11:40:37 AM PDT 24 |
439882697 ps |
| T866 |
/workspace/coverage/default/27.sram_ctrl_alert_test.774584992 |
|
|
Jul 01 11:43:05 AM PDT 24 |
Jul 01 11:43:06 AM PDT 24 |
14861728 ps |
| T867 |
/workspace/coverage/default/18.sram_ctrl_alert_test.1485395065 |
|
|
Jul 01 11:41:14 AM PDT 24 |
Jul 01 11:41:16 AM PDT 24 |
15275352 ps |
| T868 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2179764769 |
|
|
Jul 01 11:39:25 AM PDT 24 |
Jul 01 11:39:26 AM PDT 24 |
15830865 ps |
| T869 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2979617547 |
|
|
Jul 01 11:40:27 AM PDT 24 |
Jul 01 11:42:34 AM PDT 24 |
1194478030 ps |
| T870 |
/workspace/coverage/default/45.sram_ctrl_executable.1694117582 |
|
|
Jul 01 11:47:06 AM PDT 24 |
Jul 01 12:05:27 PM PDT 24 |
20078515315 ps |
| T871 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3807900024 |
|
|
Jul 01 11:41:40 AM PDT 24 |
Jul 01 11:45:03 AM PDT 24 |
7879612897 ps |
| T872 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2825930195 |
|
|
Jul 01 11:47:23 AM PDT 24 |
Jul 01 11:47:24 AM PDT 24 |
24488308 ps |
| T873 |
/workspace/coverage/default/21.sram_ctrl_alert_test.2792018843 |
|
|
Jul 01 11:41:57 AM PDT 24 |
Jul 01 11:42:00 AM PDT 24 |
26629285 ps |
| T874 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2034221072 |
|
|
Jul 01 11:39:23 AM PDT 24 |
Jul 01 11:45:33 AM PDT 24 |
1752401160 ps |
| T875 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1812845101 |
|
|
Jul 01 11:45:56 AM PDT 24 |
Jul 01 11:51:47 AM PDT 24 |
14283150470 ps |
| T876 |
/workspace/coverage/default/25.sram_ctrl_alert_test.1390366775 |
|
|
Jul 01 11:42:47 AM PDT 24 |
Jul 01 11:42:48 AM PDT 24 |
57081875 ps |
| T877 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2317490961 |
|
|
Jul 01 11:44:41 AM PDT 24 |
Jul 01 11:44:43 AM PDT 24 |
36444360 ps |
| T878 |
/workspace/coverage/default/39.sram_ctrl_executable.82033611 |
|
|
Jul 01 11:45:50 AM PDT 24 |
Jul 01 12:14:53 PM PDT 24 |
75592708237 ps |
| T879 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.233818970 |
|
|
Jul 01 11:45:19 AM PDT 24 |
Jul 01 11:45:29 AM PDT 24 |
183278109 ps |
| T880 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2174527728 |
|
|
Jul 01 11:44:52 AM PDT 24 |
Jul 01 11:52:28 AM PDT 24 |
17809220985 ps |
| T881 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.946088520 |
|
|
Jul 01 11:44:56 AM PDT 24 |
Jul 01 11:47:11 AM PDT 24 |
508790950 ps |
| T882 |
/workspace/coverage/default/9.sram_ctrl_smoke.3969838406 |
|
|
Jul 01 11:39:06 AM PDT 24 |
Jul 01 11:39:19 AM PDT 24 |
3311180276 ps |
| T883 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1439545846 |
|
|
Jul 01 11:40:25 AM PDT 24 |
Jul 01 11:44:09 AM PDT 24 |
11922618677 ps |
| T884 |
/workspace/coverage/default/9.sram_ctrl_alert_test.2650457917 |
|
|
Jul 01 11:39:13 AM PDT 24 |
Jul 01 11:39:15 AM PDT 24 |
56416084 ps |
| T885 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.528337647 |
|
|
Jul 01 11:42:00 AM PDT 24 |
Jul 01 11:57:21 AM PDT 24 |
9972549337 ps |
| T886 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.2645307985 |
|
|
Jul 01 11:46:35 AM PDT 24 |
Jul 01 11:46:45 AM PDT 24 |
187074132 ps |
| T887 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3923036797 |
|
|
Jul 01 11:43:49 AM PDT 24 |
Jul 01 11:43:52 AM PDT 24 |
177655304 ps |
| T888 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2913683780 |
|
|
Jul 01 11:47:45 AM PDT 24 |
Jul 01 11:58:44 AM PDT 24 |
1812479430 ps |
| T889 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.942960582 |
|
|
Jul 01 11:38:07 AM PDT 24 |
Jul 01 11:44:30 AM PDT 24 |
7690008277 ps |
| T890 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2992159660 |
|
|
Jul 01 11:45:14 AM PDT 24 |
Jul 01 11:46:13 AM PDT 24 |
529128257 ps |
| T891 |
/workspace/coverage/default/29.sram_ctrl_stress_all.1618720009 |
|
|
Jul 01 11:43:32 AM PDT 24 |
Jul 01 12:00:39 PM PDT 24 |
67327836094 ps |
| T892 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1248496045 |
|
|
Jul 01 11:41:14 AM PDT 24 |
Jul 01 11:41:21 AM PDT 24 |
108174964 ps |
| T893 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.351349576 |
|
|
Jul 01 11:37:13 AM PDT 24 |
Jul 01 11:45:29 AM PDT 24 |
20961490207 ps |
| T894 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.2366742808 |
|
|
Jul 01 11:40:19 AM PDT 24 |
Jul 01 11:40:25 AM PDT 24 |
344382974 ps |
| T895 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2238600196 |
|
|
Jul 01 11:40:57 AM PDT 24 |
Jul 01 11:41:01 AM PDT 24 |
98670609 ps |
| T896 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.177021162 |
|
|
Jul 01 11:37:08 AM PDT 24 |
Jul 01 11:58:13 AM PDT 24 |
13285956986 ps |
| T897 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.2256209891 |
|
|
Jul 01 11:45:24 AM PDT 24 |
Jul 01 11:58:33 AM PDT 24 |
11743836348 ps |
| T898 |
/workspace/coverage/default/43.sram_ctrl_partial_access.107317119 |
|
|
Jul 01 11:46:32 AM PDT 24 |
Jul 01 11:48:12 AM PDT 24 |
166388057 ps |
| T899 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1620225518 |
|
|
Jul 01 11:42:16 AM PDT 24 |
Jul 01 11:42:30 AM PDT 24 |
235551425 ps |
| T900 |
/workspace/coverage/default/27.sram_ctrl_regwen.2112756882 |
|
|
Jul 01 11:43:05 AM PDT 24 |
Jul 01 11:49:17 AM PDT 24 |
2475098408 ps |
| T901 |
/workspace/coverage/default/22.sram_ctrl_stress_all.429717362 |
|
|
Jul 01 11:42:04 AM PDT 24 |
Jul 01 12:02:35 PM PDT 24 |
9458378663 ps |
| T902 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1138910391 |
|
|
Jul 01 11:39:28 AM PDT 24 |
Jul 01 11:39:50 AM PDT 24 |
79432021 ps |
| T903 |
/workspace/coverage/default/28.sram_ctrl_bijection.3228696764 |
|
|
Jul 01 11:43:10 AM PDT 24 |
Jul 01 11:43:58 AM PDT 24 |
798970208 ps |
| T904 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1959065972 |
|
|
Jul 01 11:46:19 AM PDT 24 |
Jul 01 11:46:20 AM PDT 24 |
109541563 ps |
| T905 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1637869324 |
|
|
Jul 01 11:47:18 AM PDT 24 |
Jul 01 11:47:29 AM PDT 24 |
223176039 ps |
| T906 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1939320871 |
|
|
Jul 01 11:42:50 AM PDT 24 |
Jul 01 11:45:07 AM PDT 24 |
416678547 ps |
| T907 |
/workspace/coverage/default/13.sram_ctrl_partial_access.522586485 |
|
|
Jul 01 11:39:57 AM PDT 24 |
Jul 01 11:40:10 AM PDT 24 |
230107730 ps |
| T908 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3785661214 |
|
|
Jul 01 11:42:15 AM PDT 24 |
Jul 01 11:45:40 AM PDT 24 |
3981487715 ps |
| T909 |
/workspace/coverage/default/12.sram_ctrl_smoke.1562952611 |
|
|
Jul 01 11:39:37 AM PDT 24 |
Jul 01 11:40:11 AM PDT 24 |
676178220 ps |
| T910 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1791878516 |
|
|
Jul 01 11:47:18 AM PDT 24 |
Jul 01 11:59:45 AM PDT 24 |
3160406656 ps |
| T911 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.560622051 |
|
|
Jul 01 11:40:29 AM PDT 24 |
Jul 01 11:40:41 AM PDT 24 |
581394650 ps |
| T912 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3296148584 |
|
|
Jul 01 11:41:09 AM PDT 24 |
Jul 01 11:41:14 AM PDT 24 |
51658043 ps |
| T913 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.2078610151 |
|
|
Jul 01 11:38:54 AM PDT 24 |
Jul 01 11:41:15 AM PDT 24 |
165296424 ps |
| T914 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.2351635703 |
|
|
Jul 01 11:40:12 AM PDT 24 |
Jul 01 11:40:35 AM PDT 24 |
1759116450 ps |
| T915 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1256740800 |
|
|
Jul 01 11:37:55 AM PDT 24 |
Jul 01 11:41:02 AM PDT 24 |
7499218271 ps |
| T916 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2663851096 |
|
|
Jul 01 11:44:06 AM PDT 24 |
Jul 01 11:44:22 AM PDT 24 |
927919630 ps |
| T39 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.1179248664 |
|
|
Jul 01 11:37:49 AM PDT 24 |
Jul 01 11:37:53 AM PDT 24 |
309540543 ps |
| T917 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2528517661 |
|
|
Jul 01 11:40:18 AM PDT 24 |
Jul 01 11:40:24 AM PDT 24 |
578035093 ps |
| T119 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1573145179 |
|
|
Jul 01 11:42:09 AM PDT 24 |
Jul 01 11:42:57 AM PDT 24 |
7724474069 ps |
| T918 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3685560291 |
|
|
Jul 01 11:41:15 AM PDT 24 |
Jul 01 11:41:24 AM PDT 24 |
2770380399 ps |
| T919 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.149069614 |
|
|
Jul 01 11:46:05 AM PDT 24 |
Jul 01 11:49:16 AM PDT 24 |
7734600499 ps |
| T920 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.921779620 |
|
|
Jul 01 11:46:41 AM PDT 24 |
Jul 01 11:46:43 AM PDT 24 |
88235999 ps |
| T921 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.174489160 |
|
|
Jul 01 11:47:44 AM PDT 24 |
Jul 01 11:47:48 AM PDT 24 |
177961585 ps |
| T922 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2780305059 |
|
|
Jul 01 11:43:22 AM PDT 24 |
Jul 01 11:52:22 AM PDT 24 |
20824223023 ps |
| T923 |
/workspace/coverage/default/25.sram_ctrl_stress_all.1421692236 |
|
|
Jul 01 11:42:47 AM PDT 24 |
Jul 01 12:42:21 PM PDT 24 |
46128050499 ps |
| T924 |
/workspace/coverage/default/9.sram_ctrl_regwen.1829921647 |
|
|
Jul 01 11:39:09 AM PDT 24 |
Jul 01 12:07:04 PM PDT 24 |
14808804601 ps |
| T925 |
/workspace/coverage/default/45.sram_ctrl_alert_test.977337240 |
|
|
Jul 01 11:47:07 AM PDT 24 |
Jul 01 11:47:09 AM PDT 24 |
14655294 ps |
| T926 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1719402026 |
|
|
Jul 01 11:44:22 AM PDT 24 |
Jul 01 11:58:30 AM PDT 24 |
70360831982 ps |
| T927 |
/workspace/coverage/default/35.sram_ctrl_alert_test.3529158310 |
|
|
Jul 01 11:45:02 AM PDT 24 |
Jul 01 11:45:04 AM PDT 24 |
17796559 ps |
| T69 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2135847663 |
|
|
Jul 01 10:40:04 AM PDT 24 |
Jul 01 10:40:07 AM PDT 24 |
3083772156 ps |
| T66 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3902642653 |
|
|
Jul 01 10:39:53 AM PDT 24 |
Jul 01 10:39:56 AM PDT 24 |
94391673 ps |
| T70 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4011650615 |
|
|
Jul 01 10:39:51 AM PDT 24 |
Jul 01 10:39:55 AM PDT 24 |
228319895 ps |
| T84 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3797864793 |
|
|
Jul 01 10:39:59 AM PDT 24 |
Jul 01 10:40:01 AM PDT 24 |
16520598 ps |
| T110 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.513884307 |
|
|
Jul 01 10:39:54 AM PDT 24 |
Jul 01 10:39:55 AM PDT 24 |
34553979 ps |
| T115 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.809090905 |
|
|
Jul 01 10:39:37 AM PDT 24 |
Jul 01 10:39:48 AM PDT 24 |
479507527 ps |
| T85 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3535479119 |
|
|
Jul 01 10:39:59 AM PDT 24 |
Jul 01 10:40:03 AM PDT 24 |
1603794471 ps |
| T116 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3876885095 |
|
|
Jul 01 10:39:56 AM PDT 24 |
Jul 01 10:39:58 AM PDT 24 |
42933568 ps |
| T67 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2611923791 |
|
|
Jul 01 10:40:14 AM PDT 24 |
Jul 01 10:40:18 AM PDT 24 |
169564390 ps |
| T86 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2954093777 |
|
|
Jul 01 10:40:08 AM PDT 24 |
Jul 01 10:40:09 AM PDT 24 |
56720184 ps |
| T68 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.220045625 |
|
|
Jul 01 10:40:15 AM PDT 24 |
Jul 01 10:40:19 AM PDT 24 |
258329302 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.845048440 |
|
|
Jul 01 10:40:00 AM PDT 24 |
Jul 01 10:40:02 AM PDT 24 |
79723438 ps |
| T88 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.318390750 |
|
|
Jul 01 10:39:55 AM PDT 24 |
Jul 01 10:39:56 AM PDT 24 |
14333327 ps |
| T928 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3349237636 |
|
|
Jul 01 10:40:03 AM PDT 24 |
Jul 01 10:40:05 AM PDT 24 |
34844851 ps |
| T929 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1130430073 |
|
|
Jul 01 10:40:22 AM PDT 24 |
Jul 01 10:40:28 AM PDT 24 |
151661524 ps |
| T930 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1784731692 |
|
|
Jul 01 10:40:33 AM PDT 24 |
Jul 01 10:40:39 AM PDT 24 |
222333328 ps |
| T89 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4024221991 |
|
|
Jul 01 10:40:35 AM PDT 24 |
Jul 01 10:40:37 AM PDT 24 |
40448188 ps |
| T931 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3178492706 |
|
|
Jul 01 10:39:54 AM PDT 24 |
Jul 01 10:39:57 AM PDT 24 |
338491619 ps |
| T131 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2430934370 |
|
|
Jul 01 10:40:09 AM PDT 24 |
Jul 01 10:40:13 AM PDT 24 |
95428164 ps |
| T126 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2683076541 |
|
|
Jul 01 10:40:20 AM PDT 24 |
Jul 01 10:40:30 AM PDT 24 |
235632490 ps |
| T133 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3797923421 |
|
|
Jul 01 10:40:23 AM PDT 24 |
Jul 01 10:40:30 AM PDT 24 |
219681064 ps |
| T90 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1033575313 |
|
|
Jul 01 10:40:13 AM PDT 24 |
Jul 01 10:40:18 AM PDT 24 |
375867038 ps |
| T932 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3516267649 |
|
|
Jul 01 10:40:12 AM PDT 24 |
Jul 01 10:40:16 AM PDT 24 |
75684735 ps |
| T91 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3265828072 |
|
|
Jul 01 10:40:18 AM PDT 24 |
Jul 01 10:40:25 AM PDT 24 |
1562481243 ps |
| T93 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.673056468 |
|
|
Jul 01 10:40:03 AM PDT 24 |
Jul 01 10:40:05 AM PDT 24 |
43341274 ps |
| T135 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.500076532 |
|
|
Jul 01 10:39:51 AM PDT 24 |
Jul 01 10:39:54 AM PDT 24 |
498330381 ps |
| T933 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4208554288 |
|
|
Jul 01 10:39:56 AM PDT 24 |
Jul 01 10:39:58 AM PDT 24 |
37453975 ps |
| T934 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2786452446 |
|
|
Jul 01 10:39:43 AM PDT 24 |
Jul 01 10:39:47 AM PDT 24 |
43963404 ps |
| T128 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1201799920 |
|
|
Jul 01 10:40:32 AM PDT 24 |
Jul 01 10:40:35 AM PDT 24 |
38847221 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2649222237 |
|
|
Jul 01 10:39:57 AM PDT 24 |
Jul 01 10:40:03 AM PDT 24 |
21121139 ps |
| T95 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1612207650 |
|
|
Jul 01 10:40:21 AM PDT 24 |
Jul 01 10:40:28 AM PDT 24 |
1699562605 ps |
| T127 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2155094126 |
|
|
Jul 01 10:39:44 AM PDT 24 |
Jul 01 10:39:49 AM PDT 24 |
33919583 ps |
| T129 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3096336282 |
|
|
Jul 01 10:40:15 AM PDT 24 |
Jul 01 10:40:19 AM PDT 24 |
84878191 ps |
| T130 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3399319181 |
|
|
Jul 01 10:40:27 AM PDT 24 |
Jul 01 10:40:32 AM PDT 24 |
716175480 ps |
| T935 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3382726746 |
|
|
Jul 01 10:39:43 AM PDT 24 |
Jul 01 10:39:48 AM PDT 24 |
17941716 ps |
| T936 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2564228297 |
|
|
Jul 01 10:40:16 AM PDT 24 |
Jul 01 10:40:19 AM PDT 24 |
54242951 ps |
| T937 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1525696314 |
|
|
Jul 01 10:40:12 AM PDT 24 |
Jul 01 10:40:16 AM PDT 24 |
410438294 ps |
| T938 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2557323647 |
|
|
Jul 01 10:39:49 AM PDT 24 |
Jul 01 10:39:52 AM PDT 24 |
49732674 ps |
| T939 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1219909156 |
|
|
Jul 01 10:39:41 AM PDT 24 |
Jul 01 10:39:47 AM PDT 24 |
75674702 ps |
| T940 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2756458614 |
|
|
Jul 01 10:40:08 AM PDT 24 |
Jul 01 10:40:09 AM PDT 24 |
27341647 ps |
| T941 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.554704608 |
|
|
Jul 01 10:39:49 AM PDT 24 |
Jul 01 10:39:52 AM PDT 24 |
14622034 ps |
| T942 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1185119894 |
|
|
Jul 01 10:40:11 AM PDT 24 |
Jul 01 10:40:14 AM PDT 24 |
44071780 ps |
| T943 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.5876038 |
|
|
Jul 01 10:40:12 AM PDT 24 |
Jul 01 10:40:16 AM PDT 24 |
85497652 ps |
| T134 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2032003722 |
|
|
Jul 01 10:39:55 AM PDT 24 |
Jul 01 10:39:57 AM PDT 24 |
81655853 ps |
| T944 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4155679263 |
|
|
Jul 01 10:40:08 AM PDT 24 |
Jul 01 10:40:10 AM PDT 24 |
21259763 ps |
| T945 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2665237056 |
|
|
Jul 01 10:40:09 AM PDT 24 |
Jul 01 10:40:13 AM PDT 24 |
96897594 ps |
| T946 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2463796067 |
|
|
Jul 01 10:40:28 AM PDT 24 |
Jul 01 10:40:31 AM PDT 24 |
44841017 ps |
| T947 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2304294030 |
|
|
Jul 01 10:40:07 AM PDT 24 |
Jul 01 10:40:09 AM PDT 24 |
93620325 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3399487053 |
|
|
Jul 01 10:40:10 AM PDT 24 |
Jul 01 10:40:13 AM PDT 24 |
169192541 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3371457204 |
|
|
Jul 01 10:40:02 AM PDT 24 |
Jul 01 10:40:04 AM PDT 24 |
33719659 ps |
| T103 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1874280902 |
|
|
Jul 01 10:40:22 AM PDT 24 |
Jul 01 10:40:27 AM PDT 24 |
1049184713 ps |
| T949 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.871306673 |
|
|
Jul 01 10:39:43 AM PDT 24 |
Jul 01 10:39:50 AM PDT 24 |
82744571 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4177619306 |
|
|
Jul 01 10:40:16 AM PDT 24 |
Jul 01 10:40:20 AM PDT 24 |
105465460 ps |
| T951 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1470285297 |
|
|
Jul 01 10:39:49 AM PDT 24 |
Jul 01 10:39:52 AM PDT 24 |
40916456 ps |
| T104 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2419322961 |
|
|
Jul 01 10:39:52 AM PDT 24 |
Jul 01 10:39:54 AM PDT 24 |
13518846 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.484836097 |
|
|
Jul 01 10:40:15 AM PDT 24 |
Jul 01 10:40:18 AM PDT 24 |
101575716 ps |
| T953 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3454443077 |
|
|
Jul 01 10:39:48 AM PDT 24 |
Jul 01 10:39:51 AM PDT 24 |
98538077 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.197807048 |
|
|
Jul 01 10:39:36 AM PDT 24 |
Jul 01 10:39:42 AM PDT 24 |
32301402 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4188967318 |
|
|
Jul 01 10:39:57 AM PDT 24 |
Jul 01 10:39:59 AM PDT 24 |
12635670 ps |
| T105 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2700447318 |
|
|
Jul 01 10:39:57 AM PDT 24 |
Jul 01 10:40:01 AM PDT 24 |
760121425 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3172882424 |
|
|
Jul 01 10:39:49 AM PDT 24 |
Jul 01 10:39:53 AM PDT 24 |
252289013 ps |
| T957 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3050442463 |
|
|
Jul 01 10:39:50 AM PDT 24 |
Jul 01 10:39:53 AM PDT 24 |
25183089 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.398954738 |
|
|
Jul 01 10:39:49 AM PDT 24 |
Jul 01 10:39:54 AM PDT 24 |
424997132 ps |
| T959 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3315876513 |
|
|
Jul 01 10:39:52 AM PDT 24 |
Jul 01 10:39:54 AM PDT 24 |
38007255 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2697764337 |
|
|
Jul 01 10:39:55 AM PDT 24 |
Jul 01 10:39:57 AM PDT 24 |
35520920 ps |
| T961 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4088201178 |
|
|
Jul 01 10:39:55 AM PDT 24 |
Jul 01 10:39:57 AM PDT 24 |
19463919 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3387735476 |
|
|
Jul 01 10:40:07 AM PDT 24 |
Jul 01 10:40:10 AM PDT 24 |
216657633 ps |
| T962 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1302467670 |
|
|
Jul 01 10:39:50 AM PDT 24 |
Jul 01 10:39:53 AM PDT 24 |
97596599 ps |
| T963 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1132585551 |
|
|
Jul 01 10:40:30 AM PDT 24 |
Jul 01 10:40:33 AM PDT 24 |
138466503 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1243730490 |
|
|
Jul 01 10:39:53 AM PDT 24 |
Jul 01 10:39:55 AM PDT 24 |
11936973 ps |
| T965 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2013098149 |
|
|
Jul 01 10:40:20 AM PDT 24 |
Jul 01 10:40:24 AM PDT 24 |
25192149 ps |
| T132 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1995890107 |
|
|
Jul 01 10:39:54 AM PDT 24 |
Jul 01 10:39:56 AM PDT 24 |
314356547 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1641436887 |
|
|
Jul 01 10:39:49 AM PDT 24 |
Jul 01 10:39:51 AM PDT 24 |
14354231 ps |
| T967 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1959619918 |
|
|
Jul 01 10:40:29 AM PDT 24 |
Jul 01 10:40:32 AM PDT 24 |
14175957 ps |
| T137 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1612479711 |
|
|
Jul 01 10:40:12 AM PDT 24 |
Jul 01 10:40:16 AM PDT 24 |
493680379 ps |
| T968 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1793613641 |
|
|
Jul 01 10:39:55 AM PDT 24 |
Jul 01 10:39:56 AM PDT 24 |
37312747 ps |
| T109 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3076602685 |
|
|
Jul 01 10:39:46 AM PDT 24 |
Jul 01 10:39:49 AM PDT 24 |
57713320 ps |
| T969 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.748998122 |
|
|
Jul 01 10:40:02 AM PDT 24 |
Jul 01 10:40:06 AM PDT 24 |
205036826 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3971538453 |
|
|
Jul 01 10:40:21 AM PDT 24 |
Jul 01 10:40:25 AM PDT 24 |
111420491 ps |
| T107 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2679404984 |
|
|
Jul 01 10:40:29 AM PDT 24 |
Jul 01 10:40:34 AM PDT 24 |
463824320 ps |
| T971 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1477563577 |
|
|
Jul 01 10:40:05 AM PDT 24 |
Jul 01 10:40:07 AM PDT 24 |
11618017 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3602355172 |
|
|
Jul 01 10:40:15 AM PDT 24 |
Jul 01 10:40:18 AM PDT 24 |
67641016 ps |
| T108 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3513927402 |
|
|
Jul 01 10:39:54 AM PDT 24 |
Jul 01 10:39:57 AM PDT 24 |
243898886 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1471901177 |
|
|
Jul 01 10:39:47 AM PDT 24 |
Jul 01 10:39:50 AM PDT 24 |
63885213 ps |
| T974 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.980258779 |
|
|
Jul 01 10:40:07 AM PDT 24 |
Jul 01 10:40:09 AM PDT 24 |
124861387 ps |
| T975 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1780008525 |
|
|
Jul 01 10:39:47 AM PDT 24 |
Jul 01 10:39:52 AM PDT 24 |
459664761 ps |
| T136 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1587789867 |
|
|
Jul 01 10:39:46 AM PDT 24 |
Jul 01 10:39:51 AM PDT 24 |
1384017138 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3085032569 |
|
|
Jul 01 10:40:21 AM PDT 24 |
Jul 01 10:40:25 AM PDT 24 |
45058697 ps |
| T977 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2969592037 |
|
|
Jul 01 10:39:58 AM PDT 24 |
Jul 01 10:40:01 AM PDT 24 |
107974040 ps |
| T978 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.735152986 |
|
|
Jul 01 10:40:15 AM PDT 24 |
Jul 01 10:40:19 AM PDT 24 |
45272914 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2682797812 |
|
|
Jul 01 10:39:57 AM PDT 24 |
Jul 01 10:40:01 AM PDT 24 |
459032419 ps |
| T980 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1658246971 |
|
|
Jul 01 10:40:54 AM PDT 24 |
Jul 01 10:40:57 AM PDT 24 |
525906374 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2952170922 |
|
|
Jul 01 10:39:44 AM PDT 24 |
Jul 01 10:39:48 AM PDT 24 |
24931343 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2491176482 |
|
|
Jul 01 10:39:59 AM PDT 24 |
Jul 01 10:40:02 AM PDT 24 |
1003061891 ps |
| T983 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2699291535 |
|
|
Jul 01 10:40:19 AM PDT 24 |
Jul 01 10:40:24 AM PDT 24 |
123936396 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2423430407 |
|
|
Jul 01 10:40:12 AM PDT 24 |
Jul 01 10:40:14 AM PDT 24 |
16497544 ps |
| T985 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1148660678 |
|
|
Jul 01 10:39:59 AM PDT 24 |
Jul 01 10:40:01 AM PDT 24 |
20214994 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3028319385 |
|
|
Jul 01 10:40:13 AM PDT 24 |
Jul 01 10:40:16 AM PDT 24 |
128069910 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.905637074 |
|
|
Jul 01 10:40:03 AM PDT 24 |
Jul 01 10:40:08 AM PDT 24 |
122768209 ps |
| T988 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1631913908 |
|
|
Jul 01 10:40:06 AM PDT 24 |
Jul 01 10:40:08 AM PDT 24 |
29550720 ps |
| T989 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2542551781 |
|
|
Jul 01 10:40:25 AM PDT 24 |
Jul 01 10:40:36 AM PDT 24 |
878583325 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4287480264 |
|
|
Jul 01 10:39:47 AM PDT 24 |
Jul 01 10:39:51 AM PDT 24 |
317725866 ps |
| T991 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.584737424 |
|
|
Jul 01 10:39:53 AM PDT 24 |
Jul 01 10:39:56 AM PDT 24 |
194332311 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2496712392 |
|
|
Jul 01 10:39:51 AM PDT 24 |
Jul 01 10:39:53 AM PDT 24 |
48905530 ps |
| T993 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.91926069 |
|
|
Jul 01 10:40:21 AM PDT 24 |
Jul 01 10:40:25 AM PDT 24 |
103219536 ps |
| T994 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3964284640 |
|
|
Jul 01 10:40:21 AM PDT 24 |
Jul 01 10:40:25 AM PDT 24 |
19179327 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3593059355 |
|
|
Jul 01 10:40:05 AM PDT 24 |
Jul 01 10:40:08 AM PDT 24 |
171496339 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1360533773 |
|
|
Jul 01 10:40:22 AM PDT 24 |
Jul 01 10:40:27 AM PDT 24 |
112250981 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.329173793 |
|
|
Jul 01 10:40:08 AM PDT 24 |
Jul 01 10:40:10 AM PDT 24 |
104861446 ps |
| T138 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2899418092 |
|
|
Jul 01 10:40:09 AM PDT 24 |
Jul 01 10:40:12 AM PDT 24 |
340087489 ps |
| T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3054782538 |
|
|
Jul 01 10:40:57 AM PDT 24 |
Jul 01 10:41:00 AM PDT 24 |
153451909 ps |
| T999 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2340128480 |
|
|
Jul 01 10:39:52 AM PDT 24 |
Jul 01 10:39:57 AM PDT 24 |
96914245 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3271753894 |
|
|
Jul 01 10:40:09 AM PDT 24 |
Jul 01 10:40:13 AM PDT 24 |
265405032 ps |