Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13571540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57587508

1

T1

1358

T2

153585

T3

31349

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35476448	1			T1	756		T2	84919		T3	17044
values[0x0]	16479625	1			T1	367		T2	40319		T3	8354
values[0x1]	19202975	1			T1	367		T2	43814		T3	8941

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6764778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64394270

1

T1

1422

T2

161306

T3

32839

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	261600	1			T1	5		T2	668		T3	143
valid_sources[0x01]	285413	1			T1	5		T2	690		T3	131
valid_sources[0x02]	264657	1			T1	1		T2	657		T3	103
valid_sources[0x03]	277592	1			T1	6		T2	587		T3	136
valid_sources[0x04]	297441	1			T1	10		T2	648		T3	134
valid_sources[0x05]	265502	1			T1	3		T2	674		T3	153
valid_sources[0x06]	254666	1			T1	6		T2	636		T3	162
valid_sources[0x07]	300200	1			T1	3		T2	695		T3	124
valid_sources[0x08]	262705	1			T1	14		T2	687		T3	104
valid_sources[0x09]	314073	1			T1	7		T2	710		T3	152
valid_sources[0x0a]	248133	1			T2	656		T3	143		T4	25
valid_sources[0x0b]	263578	1			T1	8		T2	702		T3	171
valid_sources[0x0c]	308622	1			T1	6		T2	627		T3	116
valid_sources[0x0d]	345028	1			T1	12		T2	737		T3	139
valid_sources[0x0e]	264769	1			T2	589		T3	171		T5	35
valid_sources[0x0f]	263480	1			T2	700		T3	116		T4	45
valid_sources[0x10]	299086	1			T1	4		T2	624		T3	153
valid_sources[0x11]	252989	1			T1	14		T2	625		T3	161
valid_sources[0x12]	311759	1			T1	3		T2	723		T3	152
valid_sources[0x13]	249694	1			T1	8		T2	644		T3	138
valid_sources[0x14]	257781	1			T1	9		T2	627		T3	139
valid_sources[0x15]	286465	1			T1	3		T2	663		T3	169
valid_sources[0x16]	266037	1			T1	6		T2	669		T3	157
valid_sources[0x17]	283299	1			T1	4		T2	676		T3	123
valid_sources[0x18]	297498	1			T1	4		T2	721		T3	135
valid_sources[0x19]	260887	1			T1	6		T2	670		T3	167
valid_sources[0x1a]	246563	1			T2	631		T3	124		T5	20
valid_sources[0x1b]	309382	1			T1	5		T2	649		T3	129
valid_sources[0x1c]	255505	1			T1	4		T2	695		T3	159
valid_sources[0x1d]	285171	1			T1	9		T2	707		T3	104
valid_sources[0x1e]	284244	1			T1	7		T2	671		T3	108
valid_sources[0x1f]	273366	1			T1	5		T2	642		T3	132
valid_sources[0x20]	272293	1			T1	4		T2	650		T3	128
valid_sources[0x21]	250822	1			T1	16		T2	714		T3	122
valid_sources[0x22]	257441	1			T1	7		T2	604		T3	138
valid_sources[0x23]	265853	1			T1	9		T2	632		T3	110
valid_sources[0x24]	290754	1			T1	6		T2	638		T3	104
valid_sources[0x25]	284372	1			T1	10		T2	633		T3	128
valid_sources[0x26]	260089	1			T1	7		T2	693		T3	129
valid_sources[0x27]	272037	1			T1	15		T2	663		T3	128
valid_sources[0x28]	264184	1			T1	6		T2	698		T3	140
valid_sources[0x29]	300532	1			T1	7		T2	633		T3	105
valid_sources[0x2a]	256698	1			T1	2		T2	649		T3	105
valid_sources[0x2b]	245845	1			T1	7		T2	689		T3	113
valid_sources[0x2c]	301637	1			T1	7		T2	699		T3	123
valid_sources[0x2d]	267127	1			T1	4		T2	696		T3	145
valid_sources[0x2e]	333798	1			T1	6		T2	668		T3	117
valid_sources[0x2f]	280984	1			T1	5		T2	672		T3	148
valid_sources[0x30]	262365	1			T1	3		T2	629		T3	131
valid_sources[0x31]	262101	1			T1	7		T2	704		T3	125
valid_sources[0x32]	253769	1			T1	9		T2	624		T3	127
valid_sources[0x33]	259749	1			T1	3		T2	616		T3	137
valid_sources[0x34]	330595	1			T1	2		T2	619		T3	136
valid_sources[0x35]	266740	1			T1	4		T2	666		T3	124
valid_sources[0x36]	309921	1			T1	3		T2	646		T3	126
valid_sources[0x37]	282192	1			T1	10		T2	614		T3	141
valid_sources[0x38]	286721	1			T1	2		T2	694		T3	154
valid_sources[0x39]	248597	1			T1	9		T2	644		T3	127
valid_sources[0x3a]	300406	1			T1	11		T2	725		T3	122
valid_sources[0x3b]	258148	1			T1	11		T2	617		T3	120
valid_sources[0x3c]	291861	1			T1	7		T2	695		T3	169
valid_sources[0x3d]	248278	1			T1	3		T2	628		T3	103
valid_sources[0x3e]	298240	1			T1	15		T2	701		T3	105
valid_sources[0x3f]	260676	1			T1	7		T2	656		T3	103
valid_sources[0x40]	265620	1			T1	11		T2	685		T3	147
valid_sources[0x41]	292071	1			T1	12		T2	643		T3	113
valid_sources[0x42]	256081	1			T1	2		T2	653		T3	141
valid_sources[0x43]	283982	1			T1	7		T2	625		T3	117
valid_sources[0x44]	286051	1			T1	6		T2	701		T3	151
valid_sources[0x45]	294163	1			T1	5		T2	674		T3	156
valid_sources[0x46]	272064	1			T1	8		T2	660		T3	132
valid_sources[0x47]	279537	1			T1	8		T2	645		T3	130
valid_sources[0x48]	258279	1			T1	1		T2	670		T3	172
valid_sources[0x49]	267038	1			T1	10		T2	634		T3	128
valid_sources[0x4a]	270549	1			T1	3		T2	693		T3	127
valid_sources[0x4b]	306646	1			T1	4		T2	712		T3	125
valid_sources[0x4c]	265780	1			T1	7		T2	679		T3	133
valid_sources[0x4d]	368382	1			T1	5		T2	639		T3	120
valid_sources[0x4e]	297472	1			T1	11		T2	654		T3	147
valid_sources[0x4f]	267202	1			T1	7		T2	734		T3	156
valid_sources[0x50]	270494	1			T1	9		T2	682		T3	157
valid_sources[0x51]	317979	1			T1	5		T2	660		T3	93
valid_sources[0x52]	273543	1			T1	11		T2	674		T3	125
valid_sources[0x53]	324249	1			T1	3		T2	661		T3	152
valid_sources[0x54]	296373	1			T1	14		T2	639		T3	140
valid_sources[0x55]	255699	1			T1	5		T2	692		T3	133
valid_sources[0x56]	284922	1			T1	7		T2	738		T3	151
valid_sources[0x57]	282939	1			T1	9		T2	650		T3	129
valid_sources[0x58]	302359	1			T1	9		T2	647		T3	90
valid_sources[0x59]	245979	1			T1	5		T2	630		T3	138
valid_sources[0x5a]	261504	1			T1	9		T2	674		T3	106
valid_sources[0x5b]	252246	1			T1	6		T2	634		T3	99
valid_sources[0x5c]	259310	1			T1	3		T2	665		T3	115
valid_sources[0x5d]	279572	1			T1	16		T2	688		T3	114
valid_sources[0x5e]	257593	1			T1	4		T2	671		T3	142
valid_sources[0x5f]	262991	1			T1	13		T2	692		T3	133
valid_sources[0x60]	304588	1			T1	3		T2	673		T3	137
valid_sources[0x61]	270866	1			T1	1		T2	640		T3	127
valid_sources[0x62]	274055	1			T1	6		T2	676		T3	129
valid_sources[0x63]	338393	1			T1	12		T2	642		T3	142
valid_sources[0x64]	251611	1			T1	8		T2	660		T3	153
valid_sources[0x65]	365024	1			T1	5		T2	649		T3	131
valid_sources[0x66]	291822	1			T1	10		T2	654		T3	140
valid_sources[0x67]	276332	1			T1	14		T2	613		T3	135
valid_sources[0x68]	273564	1			T1	8		T2	649		T3	113
valid_sources[0x69]	253447	1			T1	5		T2	625		T3	125
valid_sources[0x6a]	298694	1			T1	3		T2	749		T3	144
valid_sources[0x6b]	259702	1			T1	8		T2	664		T3	150
valid_sources[0x6c]	267755	1			T1	8		T2	642		T3	145
valid_sources[0x6d]	303636	1			T1	13		T2	609		T3	119
valid_sources[0x6e]	284617	1			T1	3		T2	681		T3	116
valid_sources[0x6f]	272502	1			T1	5		T2	592		T3	132
valid_sources[0x70]	246917	1			T1	11		T2	706		T3	141
valid_sources[0x71]	297136	1			T1	2		T2	672		T3	153
valid_sources[0x72]	258325	1			T1	5		T2	696		T3	138
valid_sources[0x73]	265105	1			T1	1		T2	690		T3	118
valid_sources[0x74]	266927	1			T1	7		T2	677		T3	123
valid_sources[0x75]	381715	1			T1	6		T2	620		T3	112
valid_sources[0x76]	268299	1			T1	3		T2	679		T3	100
valid_sources[0x77]	258841	1			T1	6		T2	639		T3	124
valid_sources[0x78]	277518	1			T1	4		T2	666		T3	145
valid_sources[0x79]	262164	1			T1	5		T2	692		T3	124
valid_sources[0x7a]	387159	1			T1	7		T2	703		T3	112
valid_sources[0x7b]	321025	1			T1	3		T2	641		T3	165
valid_sources[0x7c]	289918	1			T1	3		T2	673		T3	104
valid_sources[0x7d]	277982	1			T1	5		T2	633		T3	137
valid_sources[0x7e]	266481	1			T1	6		T2	681		T3	127
valid_sources[0x7f]	303894	1			T1	2		T2	577		T3	158
valid_sources[0x80]	251932	1			T1	14		T2	660		T3	116

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28695451

1

T1

690

T2

77160

T3

15564

values[0x0]

all_enables

biggest_size

14441654

1

T1

344

T2

37975

T3

7901

values[0x1]

all_enables

biggest_size

14450403

1

T1

324

T2

38450

T3

7884

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35747	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

134426

1

T2

3

T4

3

T9

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49265	1			T12	954		T13	156		T25	17
values[0x0]	58130	1			T1	2		T2	12		T3	1
values[0x1]	62778	1			T2	12		T3	3		T4	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143141

1

T2

6

T4

5

T9

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	483	1			T12	31		T13	2		T41	1
valid_sources[0x01]	459	1			T1	1		T12	11		T13	5
valid_sources[0x02]	686	1			T12	15		T21	27		T51	6
valid_sources[0x03]	852	1			T12	1		T13	2		T21	28
valid_sources[0x04]	588	1			T12	14		T13	4		T21	17
valid_sources[0x05]	543	1			T12	4		T13	5		T21	21
valid_sources[0x06]	1115	1			T12	26		T13	5		T21	13
valid_sources[0x07]	869	1			T12	1		T13	3		T21	33
valid_sources[0x08]	500	1			T12	2		T21	15		T51	21
valid_sources[0x09]	511	1			T12	23		T13	1		T21	18
valid_sources[0x0a]	706	1			T12	35		T13	4		T21	25
valid_sources[0x0b]	495	1			T12	13		T21	32		T74	1
valid_sources[0x0c]	803	1			T12	9		T13	1		T21	21
valid_sources[0x0d]	573	1			T12	22		T13	2		T25	2
valid_sources[0x0e]	532	1			T12	21		T25	1		T21	18
valid_sources[0x0f]	511	1			T12	21		T13	1		T21	14
valid_sources[0x10]	1114	1			T12	6		T13	1		T21	22
valid_sources[0x11]	627	1			T12	2		T13	2		T20	1
valid_sources[0x12]	712	1			T12	16		T21	18		T62	1
valid_sources[0x13]	752	1			T12	9		T13	7		T14	3
valid_sources[0x14]	501	1			T12	24		T21	28		T6	1
valid_sources[0x15]	733	1			T12	1		T13	2		T25	6
valid_sources[0x16]	723	1			T12	20		T21	12		T62	1
valid_sources[0x17]	758	1			T12	25		T21	20		T51	17
valid_sources[0x18]	1052	1			T12	6		T13	1		T20	1
valid_sources[0x19]	850	1			T12	11		T13	1		T21	29
valid_sources[0x1a]	851	1			T12	3		T13	6		T21	16
valid_sources[0x1b]	737	1			T12	10		T13	2		T21	22
valid_sources[0x1c]	479	1			T12	3		T13	3		T21	16
valid_sources[0x1d]	697	1			T12	19		T13	2		T21	27
valid_sources[0x1e]	495	1			T12	16		T13	2		T21	16
valid_sources[0x1f]	590	1			T12	7		T13	2		T21	22
valid_sources[0x20]	600	1			T12	15		T13	3		T21	23
valid_sources[0x21]	583	1			T12	24		T13	2		T21	22
valid_sources[0x22]	614	1			T12	6		T13	1		T25	1
valid_sources[0x23]	684	1			T12	11		T13	1		T21	17
valid_sources[0x24]	610	1			T12	28		T13	2		T21	18
valid_sources[0x25]	957	1			T12	11		T13	4		T21	23
valid_sources[0x26]	811	1			T12	22		T21	25		T49	2
valid_sources[0x27]	651	1			T12	37		T21	25		T51	11
valid_sources[0x28]	819	1			T12	15		T13	3		T21	24
valid_sources[0x29]	703	1			T12	16		T13	6		T21	21
valid_sources[0x2a]	607	1			T2	2		T12	10		T13	4
valid_sources[0x2b]	664	1			T12	19		T13	5		T21	20
valid_sources[0x2c]	447	1			T12	16		T13	5		T54	1
valid_sources[0x2d]	836	1			T12	16		T13	1		T47	2
valid_sources[0x2e]	704	1			T12	6		T13	2		T21	24
valid_sources[0x2f]	500	1			T12	7		T13	1		T21	18
valid_sources[0x30]	521	1			T12	24		T13	2		T25	1
valid_sources[0x31]	569	1			T12	6		T13	2		T21	14
valid_sources[0x32]	487	1			T12	8		T13	1		T21	21
valid_sources[0x33]	586	1			T12	7		T13	4		T21	21
valid_sources[0x34]	901	1			T12	8		T21	17		T150	1
valid_sources[0x35]	878	1			T12	19		T13	7		T21	27
valid_sources[0x36]	722	1			T12	10		T13	2		T21	23
valid_sources[0x37]	534	1			T12	19		T13	1		T21	21
valid_sources[0x38]	1113	1			T12	4		T13	1		T26	2
valid_sources[0x39]	600	1			T12	12		T13	4		T21	21
valid_sources[0x3a]	842	1			T12	4		T13	4		T21	21
valid_sources[0x3b]	763	1			T12	10		T13	4		T25	3
valid_sources[0x3c]	500	1			T11	1		T12	36		T13	1
valid_sources[0x3d]	580	1			T12	31		T13	1		T40	1
valid_sources[0x3e]	579	1			T12	18		T21	18		T64	4
valid_sources[0x3f]	563	1			T12	26		T25	1		T21	14
valid_sources[0x40]	487	1			T12	2		T21	34		T71	2
valid_sources[0x41]	675	1			T10	2		T12	20		T13	4
valid_sources[0x42]	951	1			T12	33		T13	3		T21	15
valid_sources[0x43]	560	1			T12	7		T13	2		T21	21
valid_sources[0x44]	657	1			T12	22		T13	4		T20	2
valid_sources[0x45]	687	1			T12	13		T13	4		T25	5
valid_sources[0x46]	893	1			T12	22		T13	2		T21	25
valid_sources[0x47]	581	1			T12	9		T13	3		T20	1
valid_sources[0x48]	731	1			T12	14		T13	1		T21	14
valid_sources[0x49]	774	1			T12	14		T13	6		T21	31
valid_sources[0x4a]	747	1			T12	12		T13	1		T21	18
valid_sources[0x4b]	1031	1			T12	1		T21	24		T109	1
valid_sources[0x4c]	915	1			T12	7		T13	3		T20	1
valid_sources[0x4d]	804	1			T12	3		T13	5		T21	24
valid_sources[0x4e]	734	1			T12	11		T13	2		T25	1
valid_sources[0x4f]	576	1			T12	12		T13	4		T21	29
valid_sources[0x50]	727	1			T12	23		T13	3		T21	14
valid_sources[0x51]	690	1			T12	5		T13	2		T21	25
valid_sources[0x52]	528	1			T12	12		T13	3		T25	1
valid_sources[0x53]	462	1			T12	19		T13	1		T21	22
valid_sources[0x54]	605	1			T12	14		T13	4		T21	17
valid_sources[0x55]	663	1			T12	26		T13	3		T20	1
valid_sources[0x56]	801	1			T12	29		T13	3		T25	3
valid_sources[0x57]	604	1			T12	15		T13	4		T21	34
valid_sources[0x58]	550	1			T12	11		T13	1		T21	30
valid_sources[0x59]	594	1			T12	23		T13	2		T21	26
valid_sources[0x5a]	557	1			T12	1		T13	2		T14	2
valid_sources[0x5b]	979	1			T12	4		T13	2		T20	1
valid_sources[0x5c]	557	1			T12	4		T13	2		T21	21
valid_sources[0x5d]	461	1			T13	1		T21	31		T62	2
valid_sources[0x5e]	725	1			T12	11		T13	4		T21	20
valid_sources[0x5f]	615	1			T12	14		T25	1		T21	17
valid_sources[0x60]	577	1			T12	9		T21	21		T62	1
valid_sources[0x61]	599	1			T12	15		T20	1		T21	27
valid_sources[0x62]	756	1			T12	13		T13	1		T21	26
valid_sources[0x63]	491	1			T12	27		T13	3		T21	28
valid_sources[0x64]	451	1			T12	16		T13	2		T21	20
valid_sources[0x65]	600	1			T2	1		T12	19		T13	1
valid_sources[0x66]	503	1			T12	32		T13	2		T21	18
valid_sources[0x67]	434	1			T13	5		T25	3		T21	22
valid_sources[0x68]	685	1			T2	1		T12	11		T20	1
valid_sources[0x69]	605	1			T12	16		T13	1		T21	20
valid_sources[0x6a]	518	1			T12	24		T13	4		T21	28
valid_sources[0x6b]	632	1			T12	19		T13	2		T40	1
valid_sources[0x6c]	626	1			T12	7		T13	3		T21	26
valid_sources[0x6d]	644	1			T12	33		T21	27		T51	23
valid_sources[0x6e]	513	1			T12	14		T13	2		T21	27
valid_sources[0x6f]	545	1			T12	6		T13	6		T21	21
valid_sources[0x70]	683	1			T12	7		T13	1		T25	2
valid_sources[0x71]	719	1			T2	1		T12	11		T13	3
valid_sources[0x72]	589	1			T12	16		T13	7		T21	22
valid_sources[0x73]	536	1			T12	7		T13	2		T21	22
valid_sources[0x74]	509	1			T12	14		T13	4		T21	28
valid_sources[0x75]	714	1			T12	4		T13	3		T21	23
valid_sources[0x76]	815	1			T12	18		T13	4		T21	28
valid_sources[0x77]	551	1			T12	10		T20	2		T21	22
valid_sources[0x78]	528	1			T12	10		T13	3		T21	24
valid_sources[0x79]	869	1			T2	1		T12	23		T13	5
valid_sources[0x7a]	596	1			T12	10		T13	5		T20	1
valid_sources[0x7b]	766	1			T12	14		T25	1		T21	27
valid_sources[0x7c]	467	1			T12	6		T13	6		T25	5
valid_sources[0x7d]	456	1			T12	2		T21	32		T151	1
valid_sources[0x7e]	823	1			T12	8		T21	24		T62	2
valid_sources[0x7f]	801	1			T12	16		T13	3		T25	2
valid_sources[0x80]	889	1			T12	13		T13	5		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36770

1

T12

863

T13

135

T25

9

values[0x0]

all_enables

biggest_size

49667

1

T2

2

T4

1

T12

1130

values[0x1]

all_enables

biggest_size

47989

1

T2

1

T4

2

T9

1