Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13298582

1

T1

132

T2

12366

T3

2990

full_word

52980466

1

T1

1358

T2

122686

T3

31349

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66278778	1			T1	1490		T2	135052		T3	34339
auto[TlIntgErrCmd]	77	1			T55	7		T56	5		T57	5
auto[TlIntgErrData]	96	1			T55	7		T56	3		T57	8
auto[TlIntgErrBoth]	97	1			T55	6		T56	2		T57	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30544539

1

T1

756

T2

50919

T3

17044

auto[1]

35734509

1

T1

734

T2

84133

T3

17295

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6366844	1			T1	66		T2	4658		T3	1480
auto[TlIntgErrNone]	partial	auto[1]	6931487	1			T1	66		T2	7708		T3	1510
auto[TlIntgErrNone]	full_word	auto[0]	24177575	1			T1	690		T2	46261		T3	15564
auto[TlIntgErrNone]	full_word	auto[1]	28802872	1			T1	668		T2	76425		T3	15785
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T55	1		T56	2		T57	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T55	5		T56	3		T57	4
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T55	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T55	3		T57	4		T131	9
auto[TlIntgErrData]	partial	auto[1]	45	1			T55	4		T56	3		T57	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T57	3		T132	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T129	2		T133	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T55	2		T56	2		T57	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T55	3		T57	5		T131	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T134	1		T133	1		T135	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T55	1		T129	2		T136	1