Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	685471	1			T2	950		T10	548		T25	2321
auto[1]	10905705	1			T2	673		T3	7734		T5	24
auto[2]	559706	1			T2	644		T10	500		T25	2121
auto[3]	10784082	1			T2	354		T3	7790		T5	24

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14893199	1			T2	2004		T3	12874		T5	40
auto[1]	2189583	1			T2	236		T3	1307		T5	4
auto[2]	2201059	1			T2	343		T3	1226		T5	4
auto[3]	3651123	1			T2	38		T3	117		T10	18

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8615220

1

T2

2619

T3

15506

T5

48

auto[1]

14319744

1

T2

2

T3

18

T10

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	266394	1			T2	793		T10	467		T25	1912
auto[0]	auto[0]	auto[1]	27238	1			T2	71		T10	39		T25	200
auto[0]	auto[0]	auto[2]	27179	1			T2	76		T10	39		T25	195
auto[0]	auto[0]	auto[3]	6204	1			T2	9		T10	3		T25	11
auto[0]	auto[1]	auto[0]	3295756	1			T2	508		T3	6389		T5	20
auto[0]	auto[1]	auto[1]	341503	1			T2	98		T3	677		T5	2
auto[0]	auto[1]	auto[2]	332148	1			T2	58		T3	596		T5	2
auto[0]	auto[1]	auto[3]	57033	1			T2	9		T3	66		T10	10
auto[0]	auto[2]	auto[0]	224426	1			T2	496		T10	415		T25	1758
auto[0]	auto[2]	auto[1]	22942	1			T2	44		T10	38		T25	168
auto[0]	auto[2]	auto[2]	26406	1			T2	94		T10	43		T25	165
auto[0]	auto[2]	auto[3]	5645	1			T2	10		T10	4		T25	23
auto[0]	auto[3]	auto[0]	3256052	1			T2	206		T3	6474		T5	20
auto[0]	auto[3]	auto[1]	327902	1			T2	23		T3	625		T5	2
auto[0]	auto[3]	auto[2]	340495	1			T2	115		T3	628		T5	2
auto[0]	auto[3]	auto[3]	57897	1			T2	9		T3	51		T10	1
auto[1]	auto[0]	auto[0]	11986	1			T2	1		T25	2		T84	1
auto[1]	auto[0]	auto[1]	53462	1			T107	760		T108	412		T143	1
auto[1]	auto[0]	auto[2]	53419	1			T25	1		T107	792		T108	413
auto[1]	auto[0]	auto[3]	239589	1			T144	1		T107	3510		T108	1827
auto[1]	auto[1]	auto[0]	3917161	1			T3	4		T10	1		T11	3
auto[1]	auto[1]	auto[1]	701370	1			T3	1		T41	3946		T26	1
auto[1]	auto[1]	auto[2]	687422	1			T3	1		T41	4075		T60	1
auto[1]	auto[1]	auto[3]	1573312	1			T41	409		T107	11786		T108	5280
auto[1]	auto[2]	auto[0]	9212	1			T25	7		T84	1		T145	2
auto[1]	auto[2]	auto[1]	40352	1			T61	1		T146	2851		T147	1
auto[1]	auto[2]	auto[2]	42060	1			T107	701		T108	336		T112	888
auto[1]	auto[2]	auto[3]	188663	1			T107	3109		T108	1548		T112	3769
auto[1]	auto[3]	auto[0]	3912212	1			T3	7		T11	2		T12	6
auto[1]	auto[3]	auto[1]	674814	1			T3	4		T12	2		T41	4137
auto[1]	auto[3]	auto[2]	691930	1			T3	1		T41	4124		T26	1
auto[1]	auto[3]	auto[3]	1522780	1			T2	1		T41	356		T107	11381