Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	325192847	197718	0	0
ctrl_regwen_rd_A	325192847	3656	0	0
exec_rd_A	325192847	3249	0	0
exec_regwen_rd_A	325192847	3315	0	0
readback_rd_A	325192847	2757	0	0
readback_regwen_rd_A	325192847	2491	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325192847	197718	0	0
T12	113711	6094	0	0
T13	13445	833	0	0
T14	1170	0	0	0
T21	0	10635	0	0
T25	159395	0	0	0
T26	241061	0	0	0
T27	2246	0	0	0
T40	19201	0	0	0
T41	142020	0	0	0
T45	0	8489	0	0
T51	0	5112	0	0
T53	5252	0	0	0
T54	6452	0	0	0
T65	0	4650	0	0
T66	0	3156	0	0
T67	0	1430	0	0
T68	0	2078	0	0
T69	0	2512	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325192847	3656	0	0
T13	13445	34	0	0
T14	1170	0	0	0
T25	159395	0	0	0
T26	241061	0	0	0
T27	2246	0	0	0
T40	19201	0	0	0
T41	142020	0	0	0
T47	10363	0	0	0
T53	5252	0	0	0
T54	6452	0	0	0
T69	0	229	0	0
T117	0	105	0	0
T118	0	333	0	0
T119	0	185	0	0
T120	0	348	0	0
T121	0	164	0	0
T122	0	130	0	0
T123	0	82	0	0
T124	0	82	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325192847	3249	0	0
T13	13445	29	0	0
T14	1170	0	0	0
T25	159395	0	0	0
T26	241061	0	0	0
T27	2246	0	0	0
T40	19201	0	0	0
T41	142020	0	0	0
T47	10363	0	0	0
T53	5252	0	0	0
T54	6452	0	0	0
T69	0	146	0	0
T117	0	72	0	0
T118	0	272	0	0
T119	0	213	0	0
T120	0	290	0	0
T121	0	103	0	0
T122	0	108	0	0
T123	0	103	0	0
T124	0	29	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325192847	3315	0	0
T13	13445	18	0	0
T14	1170	0	0	0
T25	159395	0	0	0
T26	241061	0	0	0
T27	2246	0	0	0
T40	19201	0	0	0
T41	142020	0	0	0
T47	10363	0	0	0
T53	5252	0	0	0
T54	6452	0	0	0
T69	0	180	0	0
T117	0	69	0	0
T118	0	339	0	0
T119	0	215	0	0
T120	0	251	0	0
T121	0	118	0	0
T122	0	118	0	0
T123	0	66	0	0
T124	0	45	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325192847	2757	0	0
T13	13445	37	0	0
T14	1170	0	0	0
T25	159395	0	0	0
T26	241061	0	0	0
T27	2246	0	0	0
T40	19201	0	0	0
T41	142020	0	0	0
T47	10363	0	0	0
T53	5252	0	0	0
T54	6452	0	0	0
T69	0	201	0	0
T117	0	131	0	0
T118	0	318	0	0
T119	0	154	0	0
T120	0	282	0	0
T121	0	154	0	0
T122	0	103	0	0
T123	0	82	0	0
T124	0	37	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325192847	2491	0	0
T13	13445	32	0	0
T14	1170	0	0	0
T25	159395	0	0	0
T26	241061	0	0	0
T27	2246	0	0	0
T40	19201	0	0	0
T41	142020	0	0	0
T47	10363	0	0	0
T53	5252	0	0	0
T54	6452	0	0	0
T69	0	185	0	0
T117	0	78	0	0
T118	0	253	0	0
T119	0	189	0	0
T120	0	296	0	0
T121	0	91	0	0
T122	0	138	0	0
T123	0	61	0	0
T124	0	26	0	0