| T798 |
/workspace/coverage/default/49.sram_ctrl_bijection.2649410125 |
|
|
Jul 01 05:01:29 PM PDT 24 |
Jul 01 05:02:50 PM PDT 24 |
20983891128 ps |
| T799 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1692006080 |
|
|
Jul 01 05:00:57 PM PDT 24 |
Jul 01 05:03:38 PM PDT 24 |
619597611 ps |
| T800 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1527070498 |
|
|
Jul 01 04:58:31 PM PDT 24 |
Jul 01 05:00:37 PM PDT 24 |
431535832 ps |
| T801 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.202357920 |
|
|
Jul 01 05:00:30 PM PDT 24 |
Jul 01 05:00:33 PM PDT 24 |
111595904 ps |
| T802 |
/workspace/coverage/default/10.sram_ctrl_regwen.2911201052 |
|
|
Jul 01 04:58:34 PM PDT 24 |
Jul 01 04:59:08 PM PDT 24 |
1111224122 ps |
| T803 |
/workspace/coverage/default/2.sram_ctrl_bijection.551327782 |
|
|
Jul 01 04:58:08 PM PDT 24 |
Jul 01 04:58:44 PM PDT 24 |
2804704555 ps |
| T804 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1487655972 |
|
|
Jul 01 04:58:10 PM PDT 24 |
Jul 01 05:36:13 PM PDT 24 |
48780682644 ps |
| T805 |
/workspace/coverage/default/23.sram_ctrl_smoke.3060032374 |
|
|
Jul 01 04:59:01 PM PDT 24 |
Jul 01 05:00:15 PM PDT 24 |
2068980961 ps |
| T806 |
/workspace/coverage/default/45.sram_ctrl_executable.669985355 |
|
|
Jul 01 05:01:08 PM PDT 24 |
Jul 01 05:09:00 PM PDT 24 |
13765875168 ps |
| T807 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.2788755737 |
|
|
Jul 01 04:58:50 PM PDT 24 |
Jul 01 05:17:27 PM PDT 24 |
13780014768 ps |
| T808 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2864354579 |
|
|
Jul 01 05:01:04 PM PDT 24 |
Jul 01 05:06:36 PM PDT 24 |
31313090926 ps |
| T809 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3332885371 |
|
|
Jul 01 05:00:02 PM PDT 24 |
Jul 01 05:01:49 PM PDT 24 |
138989906 ps |
| T810 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3845574985 |
|
|
Jul 01 04:58:21 PM PDT 24 |
Jul 01 04:58:31 PM PDT 24 |
499200449 ps |
| T811 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1290774045 |
|
|
Jul 01 04:59:35 PM PDT 24 |
Jul 01 05:03:05 PM PDT 24 |
2061591510 ps |
| T812 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3306324990 |
|
|
Jul 01 04:58:22 PM PDT 24 |
Jul 01 04:58:29 PM PDT 24 |
330768487 ps |
| T813 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3151012650 |
|
|
Jul 01 05:00:29 PM PDT 24 |
Jul 01 05:00:52 PM PDT 24 |
1022534296 ps |
| T814 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3060498003 |
|
|
Jul 01 05:00:51 PM PDT 24 |
Jul 01 05:00:54 PM PDT 24 |
79188825 ps |
| T815 |
/workspace/coverage/default/0.sram_ctrl_stress_all.216165091 |
|
|
Jul 01 04:58:10 PM PDT 24 |
Jul 01 05:38:12 PM PDT 24 |
14787393950 ps |
| T816 |
/workspace/coverage/default/38.sram_ctrl_alert_test.264977743 |
|
|
Jul 01 05:00:18 PM PDT 24 |
Jul 01 05:00:21 PM PDT 24 |
20891442 ps |
| T817 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.422311329 |
|
|
Jul 01 04:58:37 PM PDT 24 |
Jul 01 05:03:37 PM PDT 24 |
4294602905 ps |
| T818 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.322219645 |
|
|
Jul 01 04:58:09 PM PDT 24 |
Jul 01 04:58:21 PM PDT 24 |
653976483 ps |
| T819 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.3473228387 |
|
|
Jul 01 04:59:00 PM PDT 24 |
Jul 01 05:05:40 PM PDT 24 |
16248008445 ps |
| T820 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.3289702598 |
|
|
Jul 01 04:59:00 PM PDT 24 |
Jul 01 04:59:09 PM PDT 24 |
173618946 ps |
| T821 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3542012008 |
|
|
Jul 01 05:00:49 PM PDT 24 |
Jul 01 05:00:57 PM PDT 24 |
4473024213 ps |
| T822 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1694701059 |
|
|
Jul 01 04:58:22 PM PDT 24 |
Jul 01 04:59:13 PM PDT 24 |
93121277 ps |
| T823 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.281532678 |
|
|
Jul 01 04:58:41 PM PDT 24 |
Jul 01 04:58:45 PM PDT 24 |
66813735 ps |
| T824 |
/workspace/coverage/default/40.sram_ctrl_stress_all.99876230 |
|
|
Jul 01 05:00:33 PM PDT 24 |
Jul 01 05:42:26 PM PDT 24 |
121507911242 ps |
| T825 |
/workspace/coverage/default/6.sram_ctrl_smoke.3129726061 |
|
|
Jul 01 04:58:24 PM PDT 24 |
Jul 01 04:59:34 PM PDT 24 |
2160290754 ps |
| T826 |
/workspace/coverage/default/34.sram_ctrl_smoke.3053097956 |
|
|
Jul 01 04:59:51 PM PDT 24 |
Jul 01 05:01:39 PM PDT 24 |
664912950 ps |
| T827 |
/workspace/coverage/default/24.sram_ctrl_stress_all.3548246691 |
|
|
Jul 01 04:59:07 PM PDT 24 |
Jul 01 05:23:55 PM PDT 24 |
18061921084 ps |
| T828 |
/workspace/coverage/default/43.sram_ctrl_stress_all.113115769 |
|
|
Jul 01 05:00:50 PM PDT 24 |
Jul 01 05:03:36 PM PDT 24 |
16013121817 ps |
| T829 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.412288265 |
|
|
Jul 01 04:58:20 PM PDT 24 |
Jul 01 04:58:26 PM PDT 24 |
46918574 ps |
| T830 |
/workspace/coverage/default/20.sram_ctrl_smoke.3705777492 |
|
|
Jul 01 04:58:58 PM PDT 24 |
Jul 01 04:59:19 PM PDT 24 |
879824340 ps |
| T831 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1564412257 |
|
|
Jul 01 04:58:08 PM PDT 24 |
Jul 01 04:58:12 PM PDT 24 |
79729931 ps |
| T832 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2689502087 |
|
|
Jul 01 04:58:11 PM PDT 24 |
Jul 01 04:58:20 PM PDT 24 |
1618528831 ps |
| T833 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2298443235 |
|
|
Jul 01 04:58:28 PM PDT 24 |
Jul 01 04:58:35 PM PDT 24 |
15218213 ps |
| T834 |
/workspace/coverage/default/42.sram_ctrl_executable.198110146 |
|
|
Jul 01 05:00:41 PM PDT 24 |
Jul 01 05:07:57 PM PDT 24 |
2180774884 ps |
| T835 |
/workspace/coverage/default/1.sram_ctrl_regwen.3453621375 |
|
|
Jul 01 04:58:15 PM PDT 24 |
Jul 01 05:00:48 PM PDT 24 |
2602184922 ps |
| T836 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1944477063 |
|
|
Jul 01 05:01:06 PM PDT 24 |
Jul 01 05:25:54 PM PDT 24 |
6631203048 ps |
| T837 |
/workspace/coverage/default/25.sram_ctrl_bijection.2083679161 |
|
|
Jul 01 04:59:15 PM PDT 24 |
Jul 01 05:00:20 PM PDT 24 |
36866803698 ps |
| T838 |
/workspace/coverage/default/16.sram_ctrl_bijection.3053630309 |
|
|
Jul 01 04:59:01 PM PDT 24 |
Jul 01 04:59:26 PM PDT 24 |
1792619798 ps |
| T839 |
/workspace/coverage/default/42.sram_ctrl_bijection.4214695335 |
|
|
Jul 01 05:00:45 PM PDT 24 |
Jul 01 05:02:12 PM PDT 24 |
19186677456 ps |
| T840 |
/workspace/coverage/default/19.sram_ctrl_alert_test.3553619 |
|
|
Jul 01 04:58:48 PM PDT 24 |
Jul 01 04:58:53 PM PDT 24 |
15584595 ps |
| T841 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.708203516 |
|
|
Jul 01 05:00:17 PM PDT 24 |
Jul 01 05:00:23 PM PDT 24 |
60260603 ps |
| T842 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1872148550 |
|
|
Jul 01 05:01:15 PM PDT 24 |
Jul 01 05:01:46 PM PDT 24 |
344148534 ps |
| T843 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1555239652 |
|
|
Jul 01 04:58:45 PM PDT 24 |
Jul 01 04:58:50 PM PDT 24 |
234141928 ps |
| T844 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.537335277 |
|
|
Jul 01 05:01:24 PM PDT 24 |
Jul 01 05:01:32 PM PDT 24 |
208077783 ps |
| T845 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2974700079 |
|
|
Jul 01 04:58:38 PM PDT 24 |
Jul 01 05:05:19 PM PDT 24 |
14569968814 ps |
| T846 |
/workspace/coverage/default/19.sram_ctrl_executable.3328714863 |
|
|
Jul 01 04:58:55 PM PDT 24 |
Jul 01 05:02:29 PM PDT 24 |
8211936090 ps |
| T847 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.1247438904 |
|
|
Jul 01 04:58:40 PM PDT 24 |
Jul 01 04:58:45 PM PDT 24 |
54592919 ps |
| T848 |
/workspace/coverage/default/47.sram_ctrl_alert_test.2557517710 |
|
|
Jul 01 05:01:22 PM PDT 24 |
Jul 01 05:01:26 PM PDT 24 |
16954624 ps |
| T849 |
/workspace/coverage/default/36.sram_ctrl_bijection.561859818 |
|
|
Jul 01 05:00:03 PM PDT 24 |
Jul 01 05:00:39 PM PDT 24 |
538043975 ps |
| T850 |
/workspace/coverage/default/35.sram_ctrl_regwen.1504291695 |
|
|
Jul 01 05:00:01 PM PDT 24 |
Jul 01 05:24:03 PM PDT 24 |
28090004378 ps |
| T851 |
/workspace/coverage/default/44.sram_ctrl_bijection.2406826389 |
|
|
Jul 01 05:00:48 PM PDT 24 |
Jul 01 05:02:00 PM PDT 24 |
5048915180 ps |
| T852 |
/workspace/coverage/default/12.sram_ctrl_bijection.3399936650 |
|
|
Jul 01 04:58:35 PM PDT 24 |
Jul 01 04:59:45 PM PDT 24 |
3858184615 ps |
| T853 |
/workspace/coverage/default/36.sram_ctrl_executable.3347803178 |
|
|
Jul 01 05:00:03 PM PDT 24 |
Jul 01 05:08:06 PM PDT 24 |
5139399088 ps |
| T854 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3634654732 |
|
|
Jul 01 04:58:06 PM PDT 24 |
Jul 01 04:58:14 PM PDT 24 |
210939262 ps |
| T855 |
/workspace/coverage/default/3.sram_ctrl_executable.1212415376 |
|
|
Jul 01 04:58:22 PM PDT 24 |
Jul 01 05:19:16 PM PDT 24 |
15105965787 ps |
| T856 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1675880786 |
|
|
Jul 01 05:01:15 PM PDT 24 |
Jul 01 05:20:34 PM PDT 24 |
3301421580 ps |
| T857 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2111795077 |
|
|
Jul 01 04:59:43 PM PDT 24 |
Jul 01 04:59:51 PM PDT 24 |
338954151 ps |
| T858 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.311786530 |
|
|
Jul 01 05:00:43 PM PDT 24 |
Jul 01 05:00:53 PM PDT 24 |
2260457478 ps |
| T859 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.3171676788 |
|
|
Jul 01 05:01:05 PM PDT 24 |
Jul 01 05:01:22 PM PDT 24 |
71572887 ps |
| T860 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2831482948 |
|
|
Jul 01 04:59:42 PM PDT 24 |
Jul 01 04:59:45 PM PDT 24 |
10666973 ps |
| T861 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2999227372 |
|
|
Jul 01 04:58:49 PM PDT 24 |
Jul 01 04:58:54 PM PDT 24 |
43479919 ps |
| T862 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3082568708 |
|
|
Jul 01 04:58:47 PM PDT 24 |
Jul 01 05:02:39 PM PDT 24 |
1792278072 ps |
| T863 |
/workspace/coverage/default/40.sram_ctrl_smoke.2621628207 |
|
|
Jul 01 05:00:27 PM PDT 24 |
Jul 01 05:00:40 PM PDT 24 |
2499506734 ps |
| T864 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2301462345 |
|
|
Jul 01 05:01:13 PM PDT 24 |
Jul 01 05:01:29 PM PDT 24 |
971644312 ps |
| T865 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1117793438 |
|
|
Jul 01 04:58:24 PM PDT 24 |
Jul 01 04:58:38 PM PDT 24 |
2852873079 ps |
| T866 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.2427880994 |
|
|
Jul 01 04:59:25 PM PDT 24 |
Jul 01 05:04:07 PM PDT 24 |
16255527192 ps |
| T867 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2187069258 |
|
|
Jul 01 04:58:43 PM PDT 24 |
Jul 01 04:59:46 PM PDT 24 |
5342757339 ps |
| T868 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2617344695 |
|
|
Jul 01 04:59:28 PM PDT 24 |
Jul 01 05:04:48 PM PDT 24 |
954144735 ps |
| T869 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3059597397 |
|
|
Jul 01 05:00:57 PM PDT 24 |
Jul 01 05:01:15 PM PDT 24 |
265911431 ps |
| T870 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.3550748957 |
|
|
Jul 01 04:59:07 PM PDT 24 |
Jul 01 04:59:16 PM PDT 24 |
2104842370 ps |
| T871 |
/workspace/coverage/default/29.sram_ctrl_bijection.1580592646 |
|
|
Jul 01 04:59:30 PM PDT 24 |
Jul 01 04:59:49 PM PDT 24 |
748680502 ps |
| T872 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.347054881 |
|
|
Jul 01 05:01:11 PM PDT 24 |
Jul 01 05:01:22 PM PDT 24 |
831246327 ps |
| T873 |
/workspace/coverage/default/1.sram_ctrl_alert_test.3213320695 |
|
|
Jul 01 04:58:09 PM PDT 24 |
Jul 01 04:58:13 PM PDT 24 |
25146374 ps |
| T874 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1117199356 |
|
|
Jul 01 05:00:58 PM PDT 24 |
Jul 01 05:01:11 PM PDT 24 |
1931701552 ps |
| T875 |
/workspace/coverage/default/33.sram_ctrl_regwen.3372618535 |
|
|
Jul 01 04:59:54 PM PDT 24 |
Jul 01 05:11:59 PM PDT 24 |
20360985488 ps |
| T876 |
/workspace/coverage/default/35.sram_ctrl_smoke.2808834521 |
|
|
Jul 01 05:00:00 PM PDT 24 |
Jul 01 05:02:14 PM PDT 24 |
138182835 ps |
| T877 |
/workspace/coverage/default/33.sram_ctrl_executable.711461803 |
|
|
Jul 01 04:59:57 PM PDT 24 |
Jul 01 05:17:33 PM PDT 24 |
3499522005 ps |
| T878 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.2123664201 |
|
|
Jul 01 05:00:32 PM PDT 24 |
Jul 01 05:00:43 PM PDT 24 |
722312400 ps |
| T879 |
/workspace/coverage/default/8.sram_ctrl_smoke.985524135 |
|
|
Jul 01 04:58:24 PM PDT 24 |
Jul 01 04:58:59 PM PDT 24 |
377770086 ps |
| T880 |
/workspace/coverage/default/28.sram_ctrl_partial_access.4149061791 |
|
|
Jul 01 04:59:24 PM PDT 24 |
Jul 01 04:59:36 PM PDT 24 |
854836931 ps |
| T881 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.646776304 |
|
|
Jul 01 04:59:00 PM PDT 24 |
Jul 01 04:59:49 PM PDT 24 |
117879219 ps |
| T882 |
/workspace/coverage/default/36.sram_ctrl_smoke.3622099632 |
|
|
Jul 01 05:00:01 PM PDT 24 |
Jul 01 05:00:19 PM PDT 24 |
240358568 ps |
| T883 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2066840543 |
|
|
Jul 01 05:01:31 PM PDT 24 |
Jul 01 05:04:40 PM PDT 24 |
3647280639 ps |
| T884 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3003395740 |
|
|
Jul 01 04:58:47 PM PDT 24 |
Jul 01 04:58:52 PM PDT 24 |
18878653 ps |
| T885 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3753371169 |
|
|
Jul 01 04:58:57 PM PDT 24 |
Jul 01 05:03:35 PM PDT 24 |
3896222977 ps |
| T886 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.3138280548 |
|
|
Jul 01 04:59:52 PM PDT 24 |
Jul 01 05:00:01 PM PDT 24 |
236712325 ps |
| T887 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.840600436 |
|
|
Jul 01 04:58:10 PM PDT 24 |
Jul 01 04:59:32 PM PDT 24 |
24693559853 ps |
| T888 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.207882914 |
|
|
Jul 01 05:00:56 PM PDT 24 |
Jul 01 05:01:08 PM PDT 24 |
694762418 ps |
| T889 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1071129832 |
|
|
Jul 01 05:00:50 PM PDT 24 |
Jul 01 05:03:00 PM PDT 24 |
292975587 ps |
| T890 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.173063105 |
|
|
Jul 01 04:59:41 PM PDT 24 |
Jul 01 04:59:52 PM PDT 24 |
136127011 ps |
| T891 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2076050332 |
|
|
Jul 01 04:58:09 PM PDT 24 |
Jul 01 04:58:16 PM PDT 24 |
62685318 ps |
| T892 |
/workspace/coverage/default/44.sram_ctrl_executable.364603371 |
|
|
Jul 01 05:00:59 PM PDT 24 |
Jul 01 05:07:07 PM PDT 24 |
2249432067 ps |
| T893 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.2365946323 |
|
|
Jul 01 04:58:52 PM PDT 24 |
Jul 01 04:59:08 PM PDT 24 |
906857992 ps |
| T894 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.4064231278 |
|
|
Jul 01 05:01:28 PM PDT 24 |
Jul 01 05:01:36 PM PDT 24 |
374255904 ps |
| T895 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2789902152 |
|
|
Jul 01 04:59:42 PM PDT 24 |
Jul 01 04:59:58 PM PDT 24 |
393194698 ps |
| T896 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.158861161 |
|
|
Jul 01 05:00:19 PM PDT 24 |
Jul 01 05:00:22 PM PDT 24 |
45916765 ps |
| T897 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.454021942 |
|
|
Jul 01 04:58:41 PM PDT 24 |
Jul 01 04:58:50 PM PDT 24 |
225988795 ps |
| T898 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.1565430754 |
|
|
Jul 01 04:58:51 PM PDT 24 |
Jul 01 04:58:59 PM PDT 24 |
615114375 ps |
| T899 |
/workspace/coverage/default/46.sram_ctrl_stress_all.287798282 |
|
|
Jul 01 05:01:11 PM PDT 24 |
Jul 01 05:51:45 PM PDT 24 |
9676924017 ps |
| T900 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3816291682 |
|
|
Jul 01 04:58:21 PM PDT 24 |
Jul 01 05:25:19 PM PDT 24 |
3617422189 ps |
| T901 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3814625862 |
|
|
Jul 01 04:58:47 PM PDT 24 |
Jul 01 05:51:22 PM PDT 24 |
95885863591 ps |
| T902 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.773116586 |
|
|
Jul 01 04:58:48 PM PDT 24 |
Jul 01 04:58:57 PM PDT 24 |
2097106724 ps |
| T903 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1912716108 |
|
|
Jul 01 05:00:34 PM PDT 24 |
Jul 01 05:04:31 PM PDT 24 |
1412800528 ps |
| T904 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2809871828 |
|
|
Jul 01 04:58:37 PM PDT 24 |
Jul 01 05:03:12 PM PDT 24 |
3552727467 ps |
| T905 |
/workspace/coverage/default/27.sram_ctrl_regwen.3511754887 |
|
|
Jul 01 04:59:19 PM PDT 24 |
Jul 01 05:36:08 PM PDT 24 |
47515972555 ps |
| T906 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.2197815717 |
|
|
Jul 01 05:00:18 PM PDT 24 |
Jul 01 05:00:24 PM PDT 24 |
999294236 ps |
| T907 |
/workspace/coverage/default/30.sram_ctrl_stress_all.4007346576 |
|
|
Jul 01 04:59:34 PM PDT 24 |
Jul 01 06:02:40 PM PDT 24 |
600741116997 ps |
| T908 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.6522405 |
|
|
Jul 01 04:58:57 PM PDT 24 |
Jul 01 04:59:02 PM PDT 24 |
27824021 ps |
| T909 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.2771222426 |
|
|
Jul 01 05:01:13 PM PDT 24 |
Jul 01 05:02:32 PM PDT 24 |
789173722 ps |
| T910 |
/workspace/coverage/default/13.sram_ctrl_bijection.2619090384 |
|
|
Jul 01 04:58:46 PM PDT 24 |
Jul 01 04:59:13 PM PDT 24 |
364540139 ps |
| T911 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.455458091 |
|
|
Jul 01 04:58:03 PM PDT 24 |
Jul 01 04:58:10 PM PDT 24 |
27280412 ps |
| T912 |
/workspace/coverage/default/38.sram_ctrl_executable.2675612099 |
|
|
Jul 01 05:00:17 PM PDT 24 |
Jul 01 05:01:10 PM PDT 24 |
12066133357 ps |
| T913 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2065995348 |
|
|
Jul 01 05:00:06 PM PDT 24 |
Jul 01 05:00:13 PM PDT 24 |
151632157 ps |
| T914 |
/workspace/coverage/default/38.sram_ctrl_smoke.997725495 |
|
|
Jul 01 05:00:17 PM PDT 24 |
Jul 01 05:00:31 PM PDT 24 |
214619474 ps |
| T915 |
/workspace/coverage/default/7.sram_ctrl_smoke.3267328761 |
|
|
Jul 01 04:58:24 PM PDT 24 |
Jul 01 04:58:39 PM PDT 24 |
499172760 ps |
| T916 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1381279941 |
|
|
Jul 01 04:58:26 PM PDT 24 |
Jul 01 04:58:37 PM PDT 24 |
173946043 ps |
| T917 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2004831743 |
|
|
Jul 01 04:59:54 PM PDT 24 |
Jul 01 05:07:19 PM PDT 24 |
71619616535 ps |
| T918 |
/workspace/coverage/default/9.sram_ctrl_stress_all.4032414917 |
|
|
Jul 01 04:58:28 PM PDT 24 |
Jul 01 05:09:31 PM PDT 24 |
12374882103 ps |
| T919 |
/workspace/coverage/default/31.sram_ctrl_partial_access.3357201424 |
|
|
Jul 01 04:59:34 PM PDT 24 |
Jul 01 04:59:52 PM PDT 24 |
1229574585 ps |
| T920 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1242360565 |
|
|
Jul 01 04:58:09 PM PDT 24 |
Jul 01 04:58:16 PM PDT 24 |
87261286 ps |
| T921 |
/workspace/coverage/default/48.sram_ctrl_executable.2089872387 |
|
|
Jul 01 05:01:20 PM PDT 24 |
Jul 01 05:03:22 PM PDT 24 |
13053723691 ps |
| T922 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3214201869 |
|
|
Jul 01 04:59:41 PM PDT 24 |
Jul 01 05:03:42 PM PDT 24 |
19672526853 ps |
| T923 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1418762424 |
|
|
Jul 01 04:59:01 PM PDT 24 |
Jul 01 04:59:12 PM PDT 24 |
172822591 ps |
| T924 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.597016105 |
|
|
Jul 01 04:59:00 PM PDT 24 |
Jul 01 04:59:35 PM PDT 24 |
98223429 ps |
| T925 |
/workspace/coverage/default/16.sram_ctrl_smoke.1711949235 |
|
|
Jul 01 04:58:40 PM PDT 24 |
Jul 01 04:59:47 PM PDT 24 |
2063003043 ps |
| T926 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1988383524 |
|
|
Jul 01 04:58:53 PM PDT 24 |
Jul 01 05:04:08 PM PDT 24 |
86638368071 ps |
| T927 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2599570885 |
|
|
Jul 01 04:58:59 PM PDT 24 |
Jul 01 05:03:29 PM PDT 24 |
3011010427 ps |
| T928 |
/workspace/coverage/default/30.sram_ctrl_executable.2287928059 |
|
|
Jul 01 04:59:34 PM PDT 24 |
Jul 01 05:03:31 PM PDT 24 |
20689387896 ps |
| T929 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3339412483 |
|
|
Jul 01 04:58:24 PM PDT 24 |
Jul 01 05:23:59 PM PDT 24 |
177802425984 ps |
| T930 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3881952060 |
|
|
Jul 01 04:58:01 PM PDT 24 |
Jul 01 05:09:44 PM PDT 24 |
41801965544 ps |
| T931 |
/workspace/coverage/default/35.sram_ctrl_executable.3145096092 |
|
|
Jul 01 05:00:04 PM PDT 24 |
Jul 01 05:05:18 PM PDT 24 |
18751852456 ps |
| T932 |
/workspace/coverage/default/6.sram_ctrl_regwen.2046559701 |
|
|
Jul 01 04:58:26 PM PDT 24 |
Jul 01 05:05:27 PM PDT 24 |
1552208929 ps |
| T933 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.4213842378 |
|
|
Jul 01 05:00:06 PM PDT 24 |
Jul 01 05:12:26 PM PDT 24 |
2071334115 ps |
| T934 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3127507348 |
|
|
Jul 01 04:58:00 PM PDT 24 |
Jul 01 05:02:45 PM PDT 24 |
3045466174 ps |
| T935 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.501808365 |
|
|
Jul 01 05:01:29 PM PDT 24 |
Jul 01 05:01:37 PM PDT 24 |
417481474 ps |
| T936 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.758812263 |
|
|
Jul 01 05:00:01 PM PDT 24 |
Jul 01 05:01:26 PM PDT 24 |
3079065734 ps |
| T937 |
/workspace/coverage/default/5.sram_ctrl_executable.3120206047 |
|
|
Jul 01 04:58:23 PM PDT 24 |
Jul 01 05:18:07 PM PDT 24 |
12265036183 ps |
| T938 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3245890018 |
|
|
Jul 01 04:58:14 PM PDT 24 |
Jul 01 04:58:17 PM PDT 24 |
214604709 ps |
| T939 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.610899328 |
|
|
Jul 01 04:59:13 PM PDT 24 |
Jul 01 04:59:46 PM PDT 24 |
379053931 ps |
| T58 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1874091165 |
|
|
Jul 01 04:27:23 PM PDT 24 |
Jul 01 04:27:35 PM PDT 24 |
42359456 ps |
| T55 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.516738702 |
|
|
Jul 01 04:27:15 PM PDT 24 |
Jul 01 04:27:31 PM PDT 24 |
866193237 ps |
| T59 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1534164315 |
|
|
Jul 01 04:27:08 PM PDT 24 |
Jul 01 04:27:23 PM PDT 24 |
16331402 ps |
| T75 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2511385431 |
|
|
Jul 01 04:26:52 PM PDT 24 |
Jul 01 04:27:03 PM PDT 24 |
97860908 ps |
| T56 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4105356291 |
|
|
Jul 01 04:27:01 PM PDT 24 |
Jul 01 04:27:16 PM PDT 24 |
176869846 ps |
| T57 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4280581157 |
|
|
Jul 01 04:27:09 PM PDT 24 |
Jul 01 04:27:27 PM PDT 24 |
253219201 ps |
| T940 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3503112133 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:23 PM PDT 24 |
48698528 ps |
| T941 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3707926177 |
|
|
Jul 01 04:27:05 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
134680118 ps |
| T115 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.455621191 |
|
|
Jul 01 04:27:00 PM PDT 24 |
Jul 01 04:27:14 PM PDT 24 |
270494784 ps |
| T116 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3138668825 |
|
|
Jul 01 04:27:03 PM PDT 24 |
Jul 01 04:27:17 PM PDT 24 |
53893909 ps |
| T131 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3926681259 |
|
|
Jul 01 04:27:17 PM PDT 24 |
Jul 01 04:27:33 PM PDT 24 |
1360887853 ps |
| T138 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.419729694 |
|
|
Jul 01 04:26:59 PM PDT 24 |
Jul 01 04:27:13 PM PDT 24 |
344102021 ps |
| T942 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2482340134 |
|
|
Jul 01 04:27:03 PM PDT 24 |
Jul 01 04:27:20 PM PDT 24 |
466065480 ps |
| T139 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2378268935 |
|
|
Jul 01 04:27:39 PM PDT 24 |
Jul 01 04:27:50 PM PDT 24 |
325281202 ps |
| T76 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2149875311 |
|
|
Jul 01 04:27:03 PM PDT 24 |
Jul 01 04:27:17 PM PDT 24 |
20001704 ps |
| T943 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3559446078 |
|
|
Jul 01 04:27:05 PM PDT 24 |
Jul 01 04:27:21 PM PDT 24 |
100707177 ps |
| T77 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.728718591 |
|
|
Jul 01 04:26:50 PM PDT 24 |
Jul 01 04:27:04 PM PDT 24 |
446670838 ps |
| T78 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2019628328 |
|
|
Jul 01 04:27:02 PM PDT 24 |
Jul 01 04:27:15 PM PDT 24 |
38446445 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2385915457 |
|
|
Jul 01 04:26:59 PM PDT 24 |
Jul 01 04:27:12 PM PDT 24 |
23935630 ps |
| T944 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.786840966 |
|
|
Jul 01 04:27:08 PM PDT 24 |
Jul 01 04:27:27 PM PDT 24 |
592808551 ps |
| T80 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3729152723 |
|
|
Jul 01 04:27:33 PM PDT 24 |
Jul 01 04:27:44 PM PDT 24 |
53907205 ps |
| T81 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1877190495 |
|
|
Jul 01 04:27:00 PM PDT 24 |
Jul 01 04:27:14 PM PDT 24 |
69090164 ps |
| T82 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2954865032 |
|
|
Jul 01 04:27:06 PM PDT 24 |
Jul 01 04:27:21 PM PDT 24 |
270445976 ps |
| T140 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.449799363 |
|
|
Jul 01 04:26:48 PM PDT 24 |
Jul 01 04:27:00 PM PDT 24 |
445762900 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3687802701 |
|
|
Jul 01 04:27:04 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
402419762 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1394876750 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:23 PM PDT 24 |
55037961 ps |
| T104 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2899040823 |
|
|
Jul 01 04:27:05 PM PDT 24 |
Jul 01 04:27:20 PM PDT 24 |
805523967 ps |
| T946 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4165900382 |
|
|
Jul 01 04:27:32 PM PDT 24 |
Jul 01 04:27:43 PM PDT 24 |
30976445 ps |
| T105 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1710499507 |
|
|
Jul 01 04:27:03 PM PDT 24 |
Jul 01 04:27:17 PM PDT 24 |
120195226 ps |
| T106 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2379144978 |
|
|
Jul 01 04:26:58 PM PDT 24 |
Jul 01 04:27:11 PM PDT 24 |
33487279 ps |
| T947 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1529356904 |
|
|
Jul 01 04:27:00 PM PDT 24 |
Jul 01 04:27:16 PM PDT 24 |
44027643 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3717524736 |
|
|
Jul 01 04:26:51 PM PDT 24 |
Jul 01 04:27:02 PM PDT 24 |
72522787 ps |
| T949 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1062645920 |
|
|
Jul 01 04:26:55 PM PDT 24 |
Jul 01 04:27:07 PM PDT 24 |
16241211 ps |
| T85 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2761904773 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:24 PM PDT 24 |
1741723795 ps |
| T129 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1365826039 |
|
|
Jul 01 04:27:22 PM PDT 24 |
Jul 01 04:27:36 PM PDT 24 |
224018288 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2112892558 |
|
|
Jul 01 04:26:52 PM PDT 24 |
Jul 01 04:27:05 PM PDT 24 |
397189488 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2108816836 |
|
|
Jul 01 04:27:08 PM PDT 24 |
Jul 01 04:27:28 PM PDT 24 |
49177143 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3777598143 |
|
|
Jul 01 04:27:02 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
164279780 ps |
| T952 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.663595292 |
|
|
Jul 01 04:27:12 PM PDT 24 |
Jul 01 04:27:28 PM PDT 24 |
52805396 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2149207586 |
|
|
Jul 01 04:27:06 PM PDT 24 |
Jul 01 04:27:22 PM PDT 24 |
11679811 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.846389696 |
|
|
Jul 01 04:26:55 PM PDT 24 |
Jul 01 04:27:09 PM PDT 24 |
264738505 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1362390532 |
|
|
Jul 01 04:27:09 PM PDT 24 |
Jul 01 04:27:25 PM PDT 24 |
16649602 ps |
| T955 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2838511212 |
|
|
Jul 01 04:27:03 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
935462548 ps |
| T956 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2304735970 |
|
|
Jul 01 04:27:02 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
85114635 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2179613037 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:24 PM PDT 24 |
836696051 ps |
| T958 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1793861991 |
|
|
Jul 01 04:27:16 PM PDT 24 |
Jul 01 04:27:31 PM PDT 24 |
51929327 ps |
| T959 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.15837030 |
|
|
Jul 01 04:27:00 PM PDT 24 |
Jul 01 04:27:15 PM PDT 24 |
81738951 ps |
| T88 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.327679078 |
|
|
Jul 01 04:26:55 PM PDT 24 |
Jul 01 04:27:07 PM PDT 24 |
17785716 ps |
| T960 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1928668343 |
|
|
Jul 01 04:27:05 PM PDT 24 |
Jul 01 04:27:23 PM PDT 24 |
1008481913 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2304507664 |
|
|
Jul 01 04:26:56 PM PDT 24 |
Jul 01 04:27:09 PM PDT 24 |
46541169 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3906274261 |
|
|
Jul 01 04:27:14 PM PDT 24 |
Jul 01 04:27:29 PM PDT 24 |
94953447 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1977308746 |
|
|
Jul 01 04:27:16 PM PDT 24 |
Jul 01 04:27:34 PM PDT 24 |
692365921 ps |
| T134 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2188266019 |
|
|
Jul 01 04:27:01 PM PDT 24 |
Jul 01 04:27:15 PM PDT 24 |
264784806 ps |
| T963 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2308904165 |
|
|
Jul 01 04:27:04 PM PDT 24 |
Jul 01 04:27:18 PM PDT 24 |
41507973 ps |
| T964 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3343507159 |
|
|
Jul 01 04:27:10 PM PDT 24 |
Jul 01 04:27:27 PM PDT 24 |
160483215 ps |
| T965 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3195518990 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:25 PM PDT 24 |
438779460 ps |
| T966 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1313947394 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:22 PM PDT 24 |
90147019 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3475429060 |
|
|
Jul 01 04:27:16 PM PDT 24 |
Jul 01 04:27:30 PM PDT 24 |
14698844 ps |
| T968 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1672491819 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:22 PM PDT 24 |
27368874 ps |
| T130 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2082360637 |
|
|
Jul 01 04:26:58 PM PDT 24 |
Jul 01 04:27:12 PM PDT 24 |
99232023 ps |
| T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3822823863 |
|
|
Jul 01 04:27:04 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
41874740 ps |
| T99 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3521834435 |
|
|
Jul 01 04:27:20 PM PDT 24 |
Jul 01 04:27:36 PM PDT 24 |
504876399 ps |
| T100 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3837701711 |
|
|
Jul 01 04:27:06 PM PDT 24 |
Jul 01 04:27:21 PM PDT 24 |
14646200 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3655019459 |
|
|
Jul 01 04:27:02 PM PDT 24 |
Jul 01 04:27:15 PM PDT 24 |
36123813 ps |
| T93 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1405183120 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:22 PM PDT 24 |
104368728 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4012096081 |
|
|
Jul 01 04:27:15 PM PDT 24 |
Jul 01 04:27:30 PM PDT 24 |
96332372 ps |
| T971 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2786422912 |
|
|
Jul 01 04:27:00 PM PDT 24 |
Jul 01 04:27:14 PM PDT 24 |
1069237257 ps |
| T972 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.222395869 |
|
|
Jul 01 04:27:05 PM PDT 24 |
Jul 01 04:27:20 PM PDT 24 |
24207419 ps |
| T973 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2351012706 |
|
|
Jul 01 04:27:05 PM PDT 24 |
Jul 01 04:27:20 PM PDT 24 |
17659143 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2888373922 |
|
|
Jul 01 04:27:12 PM PDT 24 |
Jul 01 04:27:27 PM PDT 24 |
46500550 ps |
| T101 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.806961453 |
|
|
Jul 01 04:27:20 PM PDT 24 |
Jul 01 04:27:33 PM PDT 24 |
44632726 ps |
| T102 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2476651029 |
|
|
Jul 01 04:26:56 PM PDT 24 |
Jul 01 04:27:09 PM PDT 24 |
451276576 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1243017913 |
|
|
Jul 01 04:27:04 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
243526717 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4002581417 |
|
|
Jul 01 04:27:13 PM PDT 24 |
Jul 01 04:27:28 PM PDT 24 |
53795415 ps |
| T977 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4265664801 |
|
|
Jul 01 04:27:32 PM PDT 24 |
Jul 01 04:27:44 PM PDT 24 |
79344544 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1316791478 |
|
|
Jul 01 04:26:54 PM PDT 24 |
Jul 01 04:27:08 PM PDT 24 |
711068436 ps |
| T103 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1705151634 |
|
|
Jul 01 04:27:03 PM PDT 24 |
Jul 01 04:27:17 PM PDT 24 |
36592082 ps |
| T94 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3765790459 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:23 PM PDT 24 |
317553796 ps |
| T979 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2762655614 |
|
|
Jul 01 04:27:03 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
30701545 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3854237954 |
|
|
Jul 01 04:27:11 PM PDT 24 |
Jul 01 04:27:26 PM PDT 24 |
18689937 ps |
| T95 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1228085863 |
|
|
Jul 01 04:27:08 PM PDT 24 |
Jul 01 04:27:26 PM PDT 24 |
865559943 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3187996134 |
|
|
Jul 01 04:27:08 PM PDT 24 |
Jul 01 04:27:27 PM PDT 24 |
2373225783 ps |
| T982 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.645914804 |
|
|
Jul 01 04:27:02 PM PDT 24 |
Jul 01 04:27:15 PM PDT 24 |
51819126 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.183898133 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:22 PM PDT 24 |
16160799 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1896676813 |
|
|
Jul 01 04:27:41 PM PDT 24 |
Jul 01 04:27:51 PM PDT 24 |
161049630 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1316032418 |
|
|
Jul 01 04:27:01 PM PDT 24 |
Jul 01 04:27:15 PM PDT 24 |
29679776 ps |
| T986 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1249791299 |
|
|
Jul 01 04:27:29 PM PDT 24 |
Jul 01 04:27:41 PM PDT 24 |
97102360 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1416005137 |
|
|
Jul 01 04:26:56 PM PDT 24 |
Jul 01 04:27:09 PM PDT 24 |
33664744 ps |
| T988 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.320960905 |
|
|
Jul 01 04:27:00 PM PDT 24 |
Jul 01 04:27:13 PM PDT 24 |
16255570 ps |
| T989 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3005263673 |
|
|
Jul 01 04:27:05 PM PDT 24 |
Jul 01 04:27:21 PM PDT 24 |
44314239 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1170053835 |
|
|
Jul 01 04:27:03 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
529626128 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1413193011 |
|
|
Jul 01 04:27:00 PM PDT 24 |
Jul 01 04:27:13 PM PDT 24 |
63071810 ps |
| T991 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.763438054 |
|
|
Jul 01 04:27:19 PM PDT 24 |
Jul 01 04:27:32 PM PDT 24 |
62701732 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3246003961 |
|
|
Jul 01 04:27:10 PM PDT 24 |
Jul 01 04:27:29 PM PDT 24 |
162839316 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3802745777 |
|
|
Jul 01 04:27:00 PM PDT 24 |
Jul 01 04:27:17 PM PDT 24 |
577352476 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3070752246 |
|
|
Jul 01 04:26:55 PM PDT 24 |
Jul 01 04:27:10 PM PDT 24 |
121825919 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3782833285 |
|
|
Jul 01 04:27:04 PM PDT 24 |
Jul 01 04:27:19 PM PDT 24 |
151062030 ps |
| T996 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.974101424 |
|
|
Jul 01 04:27:05 PM PDT 24 |
Jul 01 04:27:20 PM PDT 24 |
3842709341 ps |
| T97 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3214253569 |
|
|
Jul 01 04:27:12 PM PDT 24 |
Jul 01 04:27:28 PM PDT 24 |
260102043 ps |
| T997 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4241169009 |
|
|
Jul 01 04:27:20 PM PDT 24 |
Jul 01 04:27:33 PM PDT 24 |
76318482 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2663952934 |
|
|
Jul 01 04:26:49 PM PDT 24 |
Jul 01 04:26:59 PM PDT 24 |
11286279 ps |
| T999 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.476700286 |
|
|
Jul 01 04:27:04 PM PDT 24 |
Jul 01 04:27:18 PM PDT 24 |
146068600 ps |
| T133 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2918632541 |
|
|
Jul 01 04:27:27 PM PDT 24 |
Jul 01 04:27:41 PM PDT 24 |
301633826 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.324871147 |
|
|
Jul 01 04:27:08 PM PDT 24 |
Jul 01 04:27:23 PM PDT 24 |
91436505 ps |
| T1001 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4274594677 |
|
|
Jul 01 04:27:01 PM PDT 24 |
Jul 01 04:27:16 PM PDT 24 |
148036242 ps |
| T135 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2791437230 |
|
|
Jul 01 04:27:13 PM PDT 24 |
Jul 01 04:27:29 PM PDT 24 |
252587965 ps |
| T137 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2070143553 |
|
|
Jul 01 04:27:07 PM PDT 24 |
Jul 01 04:27:23 PM PDT 24 |
702661928 ps |
| T1002 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1413269660 |
|
|
Jul 01 04:27:00 PM PDT 24 |
Jul 01 04:27:17 PM PDT 24 |
561792251 ps |