SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.93 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.26 |
T1003 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3784430177 | Jul 01 04:26:59 PM PDT 24 | Jul 01 04:27:12 PM PDT 24 | 23097650 ps | ||
T1004 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4023945583 | Jul 01 04:27:01 PM PDT 24 | Jul 01 04:27:15 PM PDT 24 | 278115491 ps | ||
T132 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2007137369 | Jul 01 04:26:55 PM PDT 24 | Jul 01 04:27:08 PM PDT 24 | 265744135 ps | ||
T1005 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1184983664 | Jul 01 04:27:02 PM PDT 24 | Jul 01 04:27:20 PM PDT 24 | 111708448 ps | ||
T1006 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2540257488 | Jul 01 04:27:05 PM PDT 24 | Jul 01 04:27:22 PM PDT 24 | 31538869 ps | ||
T1007 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3786292489 | Jul 01 04:27:26 PM PDT 24 | Jul 01 04:27:40 PM PDT 24 | 98505940 ps | ||
T1008 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4223960684 | Jul 01 04:27:03 PM PDT 24 | Jul 01 04:27:18 PM PDT 24 | 120053380 ps | ||
T1009 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2309184062 | Jul 01 04:27:16 PM PDT 24 | Jul 01 04:27:30 PM PDT 24 | 44199190 ps | ||
T1010 | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2944629162 | Jul 01 04:26:49 PM PDT 24 | Jul 01 04:27:02 PM PDT 24 | 445372630 ps | ||
T1011 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3287287167 | Jul 01 04:27:24 PM PDT 24 | Jul 01 04:27:39 PM PDT 24 | 395636101 ps | ||
T1012 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1362993250 | Jul 01 04:26:53 PM PDT 24 | Jul 01 04:27:05 PM PDT 24 | 11002034 ps | ||
T1013 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4258775746 | Jul 01 04:27:10 PM PDT 24 | Jul 01 04:27:25 PM PDT 24 | 116123551 ps | ||
T1014 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3053574606 | Jul 01 04:27:28 PM PDT 24 | Jul 01 04:27:43 PM PDT 24 | 139420390 ps | ||
T1015 | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1121038471 | Jul 01 04:27:08 PM PDT 24 | Jul 01 04:27:25 PM PDT 24 | 209022564 ps | ||
T1016 | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3058147028 | Jul 01 04:26:59 PM PDT 24 | Jul 01 04:27:12 PM PDT 24 | 36001167 ps | ||
T1017 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.906483981 | Jul 01 04:27:04 PM PDT 24 | Jul 01 04:27:19 PM PDT 24 | 23068286 ps | ||
T1018 | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1398606477 | Jul 01 04:27:26 PM PDT 24 | Jul 01 04:27:39 PM PDT 24 | 305066276 ps | ||
T1019 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3239480226 | Jul 01 04:27:35 PM PDT 24 | Jul 01 04:27:47 PM PDT 24 | 47358445 ps | ||
T1020 | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3223330898 | Jul 01 04:27:12 PM PDT 24 | Jul 01 04:27:28 PM PDT 24 | 231803476 ps | ||
T136 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3078284295 | Jul 01 04:27:31 PM PDT 24 | Jul 01 04:27:43 PM PDT 24 | 159236075 ps | ||
T1021 | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2524573724 | Jul 01 04:27:03 PM PDT 24 | Jul 01 04:27:17 PM PDT 24 | 45274748 ps |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4109430092 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 611274895 ps |
CPU time | 4.72 seconds |
Started | Jul 01 05:01:07 PM PDT 24 |
Finished | Jul 01 05:01:15 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-b9d943c9-b274-4681-8ef8-0b42de8e9f84 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4109430092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.4109430092 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.118907690 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 12899040552 ps |
CPU time | 1033.29 seconds |
Started | Jul 01 04:58:00 PM PDT 24 |
Finished | Jul 01 05:15:20 PM PDT 24 |
Peak memory | 354320 kb |
Host | smart-b7daaa84-55db-47a4-9ccd-a689c2583df1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118907690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable .118907690 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.1235531975 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 209646085 ps |
CPU time | 2.69 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 04:58:35 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-9a7368c6-3bf8-44d6-a5f6-d378f5d82c31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235531975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.1235531975 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3729432346 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 14575497409 ps |
CPU time | 792.68 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:14:37 PM PDT 24 |
Peak memory | 381060 kb |
Host | smart-48b92321-b7ac-4e23-a1f3-d73068f0bf1e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3729432346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3729432346 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.516738702 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 866193237 ps |
CPU time | 2.51 seconds |
Started | Jul 01 04:27:15 PM PDT 24 |
Finished | Jul 01 04:27:31 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-0ee0dd4e-a09e-49bd-b786-6830eef2a066 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516738702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.sram_ctrl_tl_intg_err.516738702 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.2824643806 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 414234515 ps |
CPU time | 1.78 seconds |
Started | Jul 01 04:58:00 PM PDT 24 |
Finished | Jul 01 04:58:09 PM PDT 24 |
Peak memory | 224548 kb |
Host | smart-1689d9d7-4698-4873-ac88-43bf566f15af |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824643806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2824643806 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2536650996 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 16708092272 ps |
CPU time | 449.85 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:08:48 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-0e825ba4-9f36-490a-83db-48fc776368d4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536650996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.2536650996 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.3616254149 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 15229269 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:58:32 PM PDT 24 |
Finished | Jul 01 04:58:38 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-748133fb-6fb8-4345-9a9a-7405c1b25067 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616254149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3616254149 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.1331825864 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 322111923568 ps |
CPU time | 2559.25 seconds |
Started | Jul 01 04:58:40 PM PDT 24 |
Finished | Jul 01 05:41:24 PM PDT 24 |
Peak memory | 382572 kb |
Host | smart-dce51d7a-7170-4f0e-90c3-736ef98cc8ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331825864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.1331825864 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.728718591 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 446670838 ps |
CPU time | 3.42 seconds |
Started | Jul 01 04:26:50 PM PDT 24 |
Finished | Jul 01 04:27:04 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-da0cab81-6e05-4905-97ea-de03c019da92 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728718591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.728718591 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.372142618 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 2536940978 ps |
CPU time | 705.44 seconds |
Started | Jul 01 04:58:54 PM PDT 24 |
Finished | Jul 01 05:10:44 PM PDT 24 |
Peak memory | 369552 kb |
Host | smart-472dff8e-463d-44f0-babc-9538ee9b85ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372142618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_access_during_key_req.372142618 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.2351606634 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 41666200 ps |
CPU time | 0.76 seconds |
Started | Jul 01 04:58:35 PM PDT 24 |
Finished | Jul 01 04:58:41 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-4fb7163b-9baf-470c-8160-405de0143b70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351606634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2351606634 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.3001410168 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 63329462313 ps |
CPU time | 4177.21 seconds |
Started | Jul 01 05:00:41 PM PDT 24 |
Finished | Jul 01 06:10:19 PM PDT 24 |
Peak memory | 384240 kb |
Host | smart-56dfadeb-1556-4995-b612-d08f4494e0a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001410168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.3001410168 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1365826039 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 224018288 ps |
CPU time | 2.43 seconds |
Started | Jul 01 04:27:22 PM PDT 24 |
Finished | Jul 01 04:27:36 PM PDT 24 |
Peak memory | 210368 kb |
Host | smart-6a7c6ef9-6e75-46ba-9b59-436603dd270d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365826039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.1365826039 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2188266019 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 264784806 ps |
CPU time | 1.56 seconds |
Started | Jul 01 04:27:01 PM PDT 24 |
Finished | Jul 01 04:27:15 PM PDT 24 |
Peak memory | 210272 kb |
Host | smart-4b56c622-c04d-4351-9a07-0edb06ff2c7e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188266019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.2188266019 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.1822705791 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 144904854344 ps |
CPU time | 1369.78 seconds |
Started | Jul 01 04:58:44 PM PDT 24 |
Finished | Jul 01 05:21:37 PM PDT 24 |
Peak memory | 375660 kb |
Host | smart-7d13cea2-e87f-458d-ae16-574c81719aa1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822705791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1822705791 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2007137369 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 265744135 ps |
CPU time | 1.37 seconds |
Started | Jul 01 04:26:55 PM PDT 24 |
Finished | Jul 01 04:27:08 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-a2e0fea0-33f0-4a63-95d5-f5e110b2e1ae |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007137369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.2007137369 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.283235534 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 3015237611 ps |
CPU time | 8.46 seconds |
Started | Jul 01 04:58:29 PM PDT 24 |
Finished | Jul 01 04:58:43 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-814b12ea-1b83-4b92-ab9a-f693c8292e3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283235534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_esc alation.283235534 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3687802701 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 402419762 ps |
CPU time | 2.07 seconds |
Started | Jul 01 04:27:04 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-6171a399-8a0f-4bd0-879d-35609104f356 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687802701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3687802701 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1413193011 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 63071810 ps |
CPU time | 0.71 seconds |
Started | Jul 01 04:27:00 PM PDT 24 |
Finished | Jul 01 04:27:13 PM PDT 24 |
Peak memory | 201748 kb |
Host | smart-e48eb54c-de3f-42e4-bd02-6d19a10b440d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413193011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.1413193011 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1243017913 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 243526717 ps |
CPU time | 1.98 seconds |
Started | Jul 01 04:27:04 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 201884 kb |
Host | smart-46ce9577-5507-4e82-8479-5b276f612a11 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243017913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.1243017913 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3655019459 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 36123813 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:27:02 PM PDT 24 |
Finished | Jul 01 04:27:15 PM PDT 24 |
Peak memory | 201692 kb |
Host | smart-69fb0a1c-458d-4ac8-a154-4c609ce63f18 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655019459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.3655019459 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2304507664 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 46541169 ps |
CPU time | 0.95 seconds |
Started | Jul 01 04:26:56 PM PDT 24 |
Finished | Jul 01 04:27:09 PM PDT 24 |
Peak memory | 210092 kb |
Host | smart-04096a38-45d3-4867-acb4-b02f51c63980 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304507664 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2304507664 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2385915457 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 23935630 ps |
CPU time | 0.64 seconds |
Started | Jul 01 04:26:59 PM PDT 24 |
Finished | Jul 01 04:27:12 PM PDT 24 |
Peak memory | 201796 kb |
Host | smart-c2cd1549-213b-4dc6-a425-53ae7fd0f771 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385915457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.2385915457 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1062645920 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 16241211 ps |
CPU time | 0.78 seconds |
Started | Jul 01 04:26:55 PM PDT 24 |
Finished | Jul 01 04:27:07 PM PDT 24 |
Peak memory | 201684 kb |
Host | smart-eb09ad64-b5b8-442f-a6cd-e966aa4d95ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062645920 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1062645920 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3777598143 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 164279780 ps |
CPU time | 4.79 seconds |
Started | Jul 01 04:27:02 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 202052 kb |
Host | smart-c73e6b3e-3dec-46ec-8dc6-09c7be342980 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777598143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.3777598143 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.449799363 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 445762900 ps |
CPU time | 2.03 seconds |
Started | Jul 01 04:26:48 PM PDT 24 |
Finished | Jul 01 04:27:00 PM PDT 24 |
Peak memory | 202232 kb |
Host | smart-ac93e518-808e-4906-a0ec-e866c229aaf2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449799363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.sram_ctrl_tl_intg_err.449799363 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3784430177 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 23097650 ps |
CPU time | 0.75 seconds |
Started | Jul 01 04:26:59 PM PDT 24 |
Finished | Jul 01 04:27:12 PM PDT 24 |
Peak memory | 201772 kb |
Host | smart-0335b515-e78d-4a7a-a2a8-3d93a4debe65 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784430177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.3784430177 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.324871147 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 91436505 ps |
CPU time | 1.21 seconds |
Started | Jul 01 04:27:08 PM PDT 24 |
Finished | Jul 01 04:27:23 PM PDT 24 |
Peak memory | 201976 kb |
Host | smart-d8975454-505c-4c0f-9d30-e3c57fbc1064 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324871147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.324871147 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3475429060 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 14698844 ps |
CPU time | 0.7 seconds |
Started | Jul 01 04:27:16 PM PDT 24 |
Finished | Jul 01 04:27:30 PM PDT 24 |
Peak memory | 201556 kb |
Host | smart-e9adeb38-ff57-4f17-80ee-a41d6cefcf16 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475429060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.3475429060 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4012096081 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 96332372 ps |
CPU time | 1.2 seconds |
Started | Jul 01 04:27:15 PM PDT 24 |
Finished | Jul 01 04:27:30 PM PDT 24 |
Peak memory | 210164 kb |
Host | smart-85b73cc4-d923-48ef-beba-ba04a6218e1a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012096081 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.4012096081 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2663952934 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 11286279 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:26:49 PM PDT 24 |
Finished | Jul 01 04:26:59 PM PDT 24 |
Peak memory | 201772 kb |
Host | smart-15053caa-0421-4c38-8547-d3ffbd56cd0a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663952934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2663952934 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1170053835 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 529626128 ps |
CPU time | 2.06 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-12797964-93eb-48bb-ae4c-e249735c9f99 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170053835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1170053835 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2511385431 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 97860908 ps |
CPU time | 0.7 seconds |
Started | Jul 01 04:26:52 PM PDT 24 |
Finished | Jul 01 04:27:03 PM PDT 24 |
Peak memory | 201676 kb |
Host | smart-2b2cd8e9-a3ab-44a5-927b-f7011ef15849 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511385431 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.2511385431 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2482340134 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 466065480 ps |
CPU time | 4.11 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:20 PM PDT 24 |
Peak memory | 210276 kb |
Host | smart-e7f62007-1602-4cf3-b44e-9ff564d1b3c1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482340134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2482340134 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2070143553 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 702661928 ps |
CPU time | 2.24 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:23 PM PDT 24 |
Peak memory | 210240 kb |
Host | smart-92236a2e-8efe-4601-b3b9-245e73addb75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070143553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.2070143553 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4274594677 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 148036242 ps |
CPU time | 1.71 seconds |
Started | Jul 01 04:27:01 PM PDT 24 |
Finished | Jul 01 04:27:16 PM PDT 24 |
Peak memory | 210312 kb |
Host | smart-04bfa223-12b1-4bfa-a441-dbeac8ee9823 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274594677 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.4274594677 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1405183120 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 104368728 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:22 PM PDT 24 |
Peak memory | 201724 kb |
Host | smart-f872c7eb-a771-4e80-9eb4-d7394aa11895 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405183120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.1405183120 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3187996134 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 2373225783 ps |
CPU time | 3.63 seconds |
Started | Jul 01 04:27:08 PM PDT 24 |
Finished | Jul 01 04:27:27 PM PDT 24 |
Peak memory | 202236 kb |
Host | smart-65204551-750a-4562-920c-b249a12d4de5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187996134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.3187996134 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2149875311 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 20001704 ps |
CPU time | 0.72 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:17 PM PDT 24 |
Peak memory | 201828 kb |
Host | smart-709d16a6-067d-4f24-9923-f18dc64848b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149875311 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2149875311 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.15837030 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 81738951 ps |
CPU time | 2.68 seconds |
Started | Jul 01 04:27:00 PM PDT 24 |
Finished | Jul 01 04:27:15 PM PDT 24 |
Peak memory | 210228 kb |
Host | smart-70da1bd6-b916-4d6a-99e7-a438a891af53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15837030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST _SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.15837030 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3503112133 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 48698528 ps |
CPU time | 1.08 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:23 PM PDT 24 |
Peak memory | 210104 kb |
Host | smart-a6c8df71-1640-416d-b0c8-5c7209cd7351 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503112133 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3503112133 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.806961453 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 44632726 ps |
CPU time | 0.69 seconds |
Started | Jul 01 04:27:20 PM PDT 24 |
Finished | Jul 01 04:27:33 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-18c3d22e-32b9-4dda-8e47-9849e2e9ebb0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806961453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_csr_rw.806961453 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1121038471 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 209022564 ps |
CPU time | 1.88 seconds |
Started | Jul 01 04:27:08 PM PDT 24 |
Finished | Jul 01 04:27:25 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-ff24d12c-c242-43ae-bfce-7da87ac66d50 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121038471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1121038471 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2524573724 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 45274748 ps |
CPU time | 0.8 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:17 PM PDT 24 |
Peak memory | 201828 kb |
Host | smart-015bbf23-6a6c-4722-820d-b55c680793bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524573724 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2524573724 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1529356904 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 44027643 ps |
CPU time | 3.5 seconds |
Started | Jul 01 04:27:00 PM PDT 24 |
Finished | Jul 01 04:27:16 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-d229922a-3061-449a-afcc-27d7a20b0fd2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529356904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1529356904 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4265664801 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 79344544 ps |
CPU time | 1.47 seconds |
Started | Jul 01 04:27:32 PM PDT 24 |
Finished | Jul 01 04:27:44 PM PDT 24 |
Peak memory | 202284 kb |
Host | smart-39cc5459-198e-44b0-8aee-13426e79157d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265664801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.4265664801 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1416005137 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 33664744 ps |
CPU time | 0.71 seconds |
Started | Jul 01 04:26:56 PM PDT 24 |
Finished | Jul 01 04:27:09 PM PDT 24 |
Peak memory | 201752 kb |
Host | smart-fffad19f-adb6-49d6-8105-8cf477db026f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416005137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.1416005137 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.974101424 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 3842709341 ps |
CPU time | 2.06 seconds |
Started | Jul 01 04:27:05 PM PDT 24 |
Finished | Jul 01 04:27:20 PM PDT 24 |
Peak memory | 202188 kb |
Host | smart-c45be5e5-2fcd-48aa-a3a7-1fd869e4c501 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974101424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.974101424 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3239480226 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 47358445 ps |
CPU time | 0.74 seconds |
Started | Jul 01 04:27:35 PM PDT 24 |
Finished | Jul 01 04:27:47 PM PDT 24 |
Peak memory | 201856 kb |
Host | smart-8aabf681-222f-49ca-9338-d1fbb4009c71 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239480226 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3239480226 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3246003961 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 162839316 ps |
CPU time | 4.18 seconds |
Started | Jul 01 04:27:10 PM PDT 24 |
Finished | Jul 01 04:27:29 PM PDT 24 |
Peak memory | 210288 kb |
Host | smart-210d14a3-f12c-45a4-8f26-35b6f05cc69a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246003961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.3246003961 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2308904165 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 41507973 ps |
CPU time | 1.39 seconds |
Started | Jul 01 04:27:04 PM PDT 24 |
Finished | Jul 01 04:27:18 PM PDT 24 |
Peak memory | 210300 kb |
Host | smart-d100d832-e4ec-45fb-b6f5-7413f0ca20d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308904165 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2308904165 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4002581417 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 53795415 ps |
CPU time | 0.63 seconds |
Started | Jul 01 04:27:13 PM PDT 24 |
Finished | Jul 01 04:27:28 PM PDT 24 |
Peak memory | 201772 kb |
Host | smart-5ed11b61-8552-40c9-90e7-5f2a113c9d99 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002581417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.4002581417 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2179613037 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 836696051 ps |
CPU time | 2.01 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:24 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-bf2afd63-514b-4152-9dfa-6f295f8a608f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179613037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2179613037 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3070752246 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 121825919 ps |
CPU time | 0.8 seconds |
Started | Jul 01 04:26:55 PM PDT 24 |
Finished | Jul 01 04:27:10 PM PDT 24 |
Peak memory | 201864 kb |
Host | smart-ee248211-4b6d-4f29-90bc-1c200a41ac32 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070752246 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3070752246 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1928668343 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 1008481913 ps |
CPU time | 3.33 seconds |
Started | Jul 01 04:27:05 PM PDT 24 |
Finished | Jul 01 04:27:23 PM PDT 24 |
Peak memory | 211300 kb |
Host | smart-4c2aeaaf-22cf-4c60-8e6e-21c297e42309 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928668343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.1928668343 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3707926177 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 134680118 ps |
CPU time | 1.24 seconds |
Started | Jul 01 04:27:05 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 210336 kb |
Host | smart-f7a5b29d-e43e-4a50-9f0d-f22644e83e83 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707926177 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3707926177 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1672491819 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 27368874 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:22 PM PDT 24 |
Peak memory | 201268 kb |
Host | smart-e9fa33a6-19c2-46d6-bd16-9414bac8d045 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672491819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.1672491819 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3521834435 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 504876399 ps |
CPU time | 3.35 seconds |
Started | Jul 01 04:27:20 PM PDT 24 |
Finished | Jul 01 04:27:36 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-ad86c477-63ac-4b5c-a2e4-7872141249ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521834435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3521834435 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3058147028 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 36001167 ps |
CPU time | 0.75 seconds |
Started | Jul 01 04:26:59 PM PDT 24 |
Finished | Jul 01 04:27:12 PM PDT 24 |
Peak memory | 201788 kb |
Host | smart-202e0b9c-e832-4f04-93fe-2989d363756a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058147028 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.3058147028 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3559446078 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 100707177 ps |
CPU time | 2.08 seconds |
Started | Jul 01 04:27:05 PM PDT 24 |
Finished | Jul 01 04:27:21 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-68a00dd2-f8b2-448c-a95d-bc21e15dceb5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559446078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3559446078 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3926681259 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 1360887853 ps |
CPU time | 2.18 seconds |
Started | Jul 01 04:27:17 PM PDT 24 |
Finished | Jul 01 04:27:33 PM PDT 24 |
Peak memory | 210180 kb |
Host | smart-91b52024-8944-4188-901a-9fdd2d53ae1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926681259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.3926681259 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3138668825 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 53893909 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:17 PM PDT 24 |
Peak memory | 201768 kb |
Host | smart-19c72692-6821-4649-8b86-a337c27730b6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138668825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.3138668825 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1977308746 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 692365921 ps |
CPU time | 3.73 seconds |
Started | Jul 01 04:27:16 PM PDT 24 |
Finished | Jul 01 04:27:34 PM PDT 24 |
Peak memory | 202316 kb |
Host | smart-853796a2-dded-4e2c-b40a-1100d06f675e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977308746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1977308746 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1313947394 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 90147019 ps |
CPU time | 0.82 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:22 PM PDT 24 |
Peak memory | 201840 kb |
Host | smart-f58c43cd-98d8-47c7-be9f-bbac8927bd30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313947394 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1313947394 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1184983664 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 111708448 ps |
CPU time | 3.76 seconds |
Started | Jul 01 04:27:02 PM PDT 24 |
Finished | Jul 01 04:27:20 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-b7b8e8d2-903c-4a12-9bcf-6140a3f6ebca |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184983664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.1184983664 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2378268935 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 325281202 ps |
CPU time | 1.52 seconds |
Started | Jul 01 04:27:39 PM PDT 24 |
Finished | Jul 01 04:27:50 PM PDT 24 |
Peak memory | 210172 kb |
Host | smart-a23a6509-b696-4344-a525-93078f425602 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378268935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.2378268935 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1249791299 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 97102360 ps |
CPU time | 1.06 seconds |
Started | Jul 01 04:27:29 PM PDT 24 |
Finished | Jul 01 04:27:41 PM PDT 24 |
Peak memory | 210328 kb |
Host | smart-c9fa615c-78af-4245-8d9a-9d138475cbef |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249791299 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1249791299 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3729152723 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 53907205 ps |
CPU time | 0.62 seconds |
Started | Jul 01 04:27:33 PM PDT 24 |
Finished | Jul 01 04:27:44 PM PDT 24 |
Peak memory | 201848 kb |
Host | smart-e4041bfc-770f-4ded-87be-e89294b94da3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729152723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.3729152723 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1398606477 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 305066276 ps |
CPU time | 1.93 seconds |
Started | Jul 01 04:27:26 PM PDT 24 |
Finished | Jul 01 04:27:39 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-329aca51-40aa-4aba-8b72-e6b999d66cee |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398606477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1398606477 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2108816836 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 49177143 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:27:08 PM PDT 24 |
Finished | Jul 01 04:27:28 PM PDT 24 |
Peak memory | 201824 kb |
Host | smart-f0c7c02e-c1b7-43fd-a9aa-8394ac90237e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108816836 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2108816836 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2762655614 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 30701545 ps |
CPU time | 1.99 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 210312 kb |
Host | smart-ab7f5773-9c14-4671-9399-ad98a2e2628d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762655614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.2762655614 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2082360637 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 99232023 ps |
CPU time | 1.37 seconds |
Started | Jul 01 04:26:58 PM PDT 24 |
Finished | Jul 01 04:27:12 PM PDT 24 |
Peak memory | 201980 kb |
Host | smart-7979e3a0-0fd8-45a7-95a0-15ecea5b197b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082360637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.2082360637 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3343507159 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 160483215 ps |
CPU time | 2.56 seconds |
Started | Jul 01 04:27:10 PM PDT 24 |
Finished | Jul 01 04:27:27 PM PDT 24 |
Peak memory | 210336 kb |
Host | smart-23ef72ed-0d5e-4c91-aa14-63de42b518ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343507159 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3343507159 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3837701711 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 14646200 ps |
CPU time | 0.69 seconds |
Started | Jul 01 04:27:06 PM PDT 24 |
Finished | Jul 01 04:27:21 PM PDT 24 |
Peak memory | 201708 kb |
Host | smart-b8d364b9-a396-4d92-8efd-0e34048ee904 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837701711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.3837701711 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3214253569 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 260102043 ps |
CPU time | 2.08 seconds |
Started | Jul 01 04:27:12 PM PDT 24 |
Finished | Jul 01 04:27:28 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-6cbfc1b5-7110-48de-94b2-7a6197521c99 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214253569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3214253569 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2954865032 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 270445976 ps |
CPU time | 0.81 seconds |
Started | Jul 01 04:27:06 PM PDT 24 |
Finished | Jul 01 04:27:21 PM PDT 24 |
Peak memory | 201832 kb |
Host | smart-9188ead5-7af6-400b-8918-9cbf35dfe25b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954865032 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.2954865032 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.663595292 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 52805396 ps |
CPU time | 1.95 seconds |
Started | Jul 01 04:27:12 PM PDT 24 |
Finished | Jul 01 04:27:28 PM PDT 24 |
Peak memory | 202112 kb |
Host | smart-28520104-7f7f-4a21-8f01-b6fbce5f3ce6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663595292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.663595292 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.419729694 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 344102021 ps |
CPU time | 1.49 seconds |
Started | Jul 01 04:26:59 PM PDT 24 |
Finished | Jul 01 04:27:13 PM PDT 24 |
Peak memory | 210224 kb |
Host | smart-3c94f678-3169-42b8-8084-3ba0de686afd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419729694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.sram_ctrl_tl_intg_err.419729694 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1896676813 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 161049630 ps |
CPU time | 0.83 seconds |
Started | Jul 01 04:27:41 PM PDT 24 |
Finished | Jul 01 04:27:51 PM PDT 24 |
Peak memory | 201884 kb |
Host | smart-12fbdbd0-75a3-47ef-bede-ee5b42f885ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896676813 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1896676813 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1534164315 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 16331402 ps |
CPU time | 0.66 seconds |
Started | Jul 01 04:27:08 PM PDT 24 |
Finished | Jul 01 04:27:23 PM PDT 24 |
Peak memory | 201776 kb |
Host | smart-0d012873-4882-4694-a42b-0abe13e7bcc4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534164315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.1534164315 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3287287167 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 395636101 ps |
CPU time | 3.15 seconds |
Started | Jul 01 04:27:24 PM PDT 24 |
Finished | Jul 01 04:27:39 PM PDT 24 |
Peak memory | 202124 kb |
Host | smart-531ea38a-3655-4459-a363-11ca8fe6b0d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287287167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3287287167 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1710499507 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 120195226 ps |
CPU time | 0.69 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:17 PM PDT 24 |
Peak memory | 201592 kb |
Host | smart-95d8331c-75b9-4d4c-8f71-c4e364d063a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710499507 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1710499507 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3786292489 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 98505940 ps |
CPU time | 3.5 seconds |
Started | Jul 01 04:27:26 PM PDT 24 |
Finished | Jul 01 04:27:40 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-cef4920d-be0c-4b34-b301-e477f4b8b557 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786292489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3786292489 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3078284295 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 159236075 ps |
CPU time | 1.41 seconds |
Started | Jul 01 04:27:31 PM PDT 24 |
Finished | Jul 01 04:27:43 PM PDT 24 |
Peak memory | 210180 kb |
Host | smart-f00f31f8-de04-400d-b507-f53494628f78 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078284295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.3078284295 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4165900382 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 30976445 ps |
CPU time | 0.71 seconds |
Started | Jul 01 04:27:32 PM PDT 24 |
Finished | Jul 01 04:27:43 PM PDT 24 |
Peak memory | 201972 kb |
Host | smart-23a91806-d12c-4b72-81b0-0c3f05514ea5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165900382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.4165900382 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3765790459 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 317553796 ps |
CPU time | 2.01 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:23 PM PDT 24 |
Peak memory | 201984 kb |
Host | smart-ac153d05-8fbf-40b5-81e0-92c4eafd80e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765790459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.3765790459 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4241169009 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 76318482 ps |
CPU time | 0.71 seconds |
Started | Jul 01 04:27:20 PM PDT 24 |
Finished | Jul 01 04:27:33 PM PDT 24 |
Peak memory | 201808 kb |
Host | smart-577bf2e3-8cd7-46fd-9448-59db17a330c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241169009 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.4241169009 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.786840966 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 592808551 ps |
CPU time | 4.6 seconds |
Started | Jul 01 04:27:08 PM PDT 24 |
Finished | Jul 01 04:27:27 PM PDT 24 |
Peak memory | 202112 kb |
Host | smart-f78b0ea8-731d-4c27-9de0-9c03098e6857 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786840966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.786840966 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4105356291 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 176869846 ps |
CPU time | 1.57 seconds |
Started | Jul 01 04:27:01 PM PDT 24 |
Finished | Jul 01 04:27:16 PM PDT 24 |
Peak memory | 210396 kb |
Host | smart-0c324602-f040-4d4d-a490-343e38065828 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105356291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.4105356291 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2019628328 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 38446445 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:27:02 PM PDT 24 |
Finished | Jul 01 04:27:15 PM PDT 24 |
Peak memory | 201724 kb |
Host | smart-f6b3272f-6097-4637-a7bf-de71826e9367 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019628328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.2019628328 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4223960684 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 120053380 ps |
CPU time | 2.08 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:18 PM PDT 24 |
Peak memory | 201904 kb |
Host | smart-8e9619d0-a84a-45bb-9eda-bb9e1631699c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223960684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.4223960684 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2888373922 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 46500550 ps |
CPU time | 0.69 seconds |
Started | Jul 01 04:27:12 PM PDT 24 |
Finished | Jul 01 04:27:27 PM PDT 24 |
Peak memory | 201776 kb |
Host | smart-47029778-abbe-45c0-a7a9-c66ffbdb4a1b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888373922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.2888373922 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.645914804 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 51819126 ps |
CPU time | 1.09 seconds |
Started | Jul 01 04:27:02 PM PDT 24 |
Finished | Jul 01 04:27:15 PM PDT 24 |
Peak memory | 210112 kb |
Host | smart-2d727248-24c3-4b00-aaf3-f609c0940d6d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645914804 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.645914804 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2149207586 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 11679811 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:27:06 PM PDT 24 |
Finished | Jul 01 04:27:22 PM PDT 24 |
Peak memory | 201828 kb |
Host | smart-b76cfd4a-cf31-4269-b9cb-53f435c46d21 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149207586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.2149207586 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2944629162 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 445372630 ps |
CPU time | 3.23 seconds |
Started | Jul 01 04:26:49 PM PDT 24 |
Finished | Jul 01 04:27:02 PM PDT 24 |
Peak memory | 202120 kb |
Host | smart-2fd09c70-b588-49e8-9e6b-a3d6d0932fd6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944629162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.2944629162 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3717524736 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 72522787 ps |
CPU time | 0.79 seconds |
Started | Jul 01 04:26:51 PM PDT 24 |
Finished | Jul 01 04:27:02 PM PDT 24 |
Peak memory | 201840 kb |
Host | smart-dc81580a-529c-419d-9bb1-709617d9e825 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717524736 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3717524736 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1413269660 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 561792251 ps |
CPU time | 4.43 seconds |
Started | Jul 01 04:27:00 PM PDT 24 |
Finished | Jul 01 04:27:17 PM PDT 24 |
Peak memory | 210060 kb |
Host | smart-6ebdd6d8-a9f1-4a61-80a1-44774a78b8cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413269660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.1413269660 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.846389696 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 264738505 ps |
CPU time | 1.39 seconds |
Started | Jul 01 04:26:55 PM PDT 24 |
Finished | Jul 01 04:27:09 PM PDT 24 |
Peak memory | 210224 kb |
Host | smart-3f207252-4da4-422f-b204-92c718574ea3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846389696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.sram_ctrl_tl_intg_err.846389696 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.327679078 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 17785716 ps |
CPU time | 0.73 seconds |
Started | Jul 01 04:26:55 PM PDT 24 |
Finished | Jul 01 04:27:07 PM PDT 24 |
Peak memory | 201576 kb |
Host | smart-89cac3c4-6831-4091-a205-033aafc217d7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327679078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.327679078 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.455621191 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 270494784 ps |
CPU time | 1.38 seconds |
Started | Jul 01 04:27:00 PM PDT 24 |
Finished | Jul 01 04:27:14 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-fe247ca0-e38c-4346-991c-afad16eec863 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455621191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_bash.455621191 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2309184062 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 44199190 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:27:16 PM PDT 24 |
Finished | Jul 01 04:27:30 PM PDT 24 |
Peak memory | 201860 kb |
Host | smart-ee51a2f7-22b6-48e1-918f-96bee44c05c1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309184062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.2309184062 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4023945583 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 278115491 ps |
CPU time | 1.25 seconds |
Started | Jul 01 04:27:01 PM PDT 24 |
Finished | Jul 01 04:27:15 PM PDT 24 |
Peak memory | 210048 kb |
Host | smart-f47620d8-ccc4-45ed-81bb-6d840d7aaec5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023945583 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.4023945583 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1705151634 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 36592082 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:17 PM PDT 24 |
Peak memory | 201236 kb |
Host | smart-d6c9f6c0-2942-4f4d-a416-74c5311b44c2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705151634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.1705151634 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1228085863 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 865559943 ps |
CPU time | 3.44 seconds |
Started | Jul 01 04:27:08 PM PDT 24 |
Finished | Jul 01 04:27:26 PM PDT 24 |
Peak memory | 202168 kb |
Host | smart-500fcc01-3509-4210-b50c-c0966ece6b62 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228085863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1228085863 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3906274261 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 94953447 ps |
CPU time | 0.72 seconds |
Started | Jul 01 04:27:14 PM PDT 24 |
Finished | Jul 01 04:27:29 PM PDT 24 |
Peak memory | 201728 kb |
Host | smart-57c0ef3d-f41f-4505-b61e-08e2fcb217e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906274261 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3906274261 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1394876750 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 55037961 ps |
CPU time | 1.96 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:23 PM PDT 24 |
Peak memory | 210796 kb |
Host | smart-4f4affa3-e708-464a-85b5-8517b6b59080 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394876750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.1394876750 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.476700286 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 146068600 ps |
CPU time | 1.3 seconds |
Started | Jul 01 04:27:04 PM PDT 24 |
Finished | Jul 01 04:27:18 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-41987061-cae0-4c73-b2d4-1d7d960f69f7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476700286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.sram_ctrl_tl_intg_err.476700286 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.906483981 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 23068286 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:27:04 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 201660 kb |
Host | smart-da2a41b3-1d90-4fd9-a421-91eb969aa0c2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906483981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_aliasing.906483981 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1316032418 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 29679776 ps |
CPU time | 1.21 seconds |
Started | Jul 01 04:27:01 PM PDT 24 |
Finished | Jul 01 04:27:15 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-d3cb8ee0-d42e-4b59-9071-af129299fadd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316032418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.1316032418 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1877190495 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 69090164 ps |
CPU time | 0.72 seconds |
Started | Jul 01 04:27:00 PM PDT 24 |
Finished | Jul 01 04:27:14 PM PDT 24 |
Peak memory | 201172 kb |
Host | smart-f5eb370c-44ff-4dbd-9a11-51faa202cb62 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877190495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.1877190495 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1316791478 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 711068436 ps |
CPU time | 2.82 seconds |
Started | Jul 01 04:26:54 PM PDT 24 |
Finished | Jul 01 04:27:08 PM PDT 24 |
Peak memory | 210468 kb |
Host | smart-5f41f665-8920-40be-8ec6-3454dee05c81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316791478 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1316791478 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3854237954 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 18689937 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:27:11 PM PDT 24 |
Finished | Jul 01 04:27:26 PM PDT 24 |
Peak memory | 201772 kb |
Host | smart-df13bd6d-56b8-4698-9492-c1bdab2a99d8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854237954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.3854237954 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2112892558 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 397189488 ps |
CPU time | 2 seconds |
Started | Jul 01 04:26:52 PM PDT 24 |
Finished | Jul 01 04:27:05 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-67e72cf7-5a71-48f2-8d0c-baddeab6663b |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112892558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2112892558 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1362390532 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 16649602 ps |
CPU time | 0.66 seconds |
Started | Jul 01 04:27:09 PM PDT 24 |
Finished | Jul 01 04:27:25 PM PDT 24 |
Peak memory | 201760 kb |
Host | smart-399f9ae3-4bec-42db-baa8-79605d3e28d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362390532 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1362390532 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3802745777 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 577352476 ps |
CPU time | 4.53 seconds |
Started | Jul 01 04:27:00 PM PDT 24 |
Finished | Jul 01 04:27:17 PM PDT 24 |
Peak memory | 202104 kb |
Host | smart-0fe76d9e-1669-42b4-94da-5d30b36fb8e3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802745777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.3802745777 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2791437230 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 252587965 ps |
CPU time | 2.17 seconds |
Started | Jul 01 04:27:13 PM PDT 24 |
Finished | Jul 01 04:27:29 PM PDT 24 |
Peak memory | 210236 kb |
Host | smart-867fa21a-d8df-46ec-ad50-cda7ac7cc662 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791437230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.2791437230 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3005263673 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 44314239 ps |
CPU time | 1.33 seconds |
Started | Jul 01 04:27:05 PM PDT 24 |
Finished | Jul 01 04:27:21 PM PDT 24 |
Peak memory | 210264 kb |
Host | smart-e699c2bd-74f7-4bba-b06f-3838eab4137b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005263673 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3005263673 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1874091165 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 42359456 ps |
CPU time | 0.64 seconds |
Started | Jul 01 04:27:23 PM PDT 24 |
Finished | Jul 01 04:27:35 PM PDT 24 |
Peak memory | 201228 kb |
Host | smart-29355316-efe8-4bf2-bbe0-7228fea1d6fd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874091165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.1874091165 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.320960905 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 16255570 ps |
CPU time | 0.74 seconds |
Started | Jul 01 04:27:00 PM PDT 24 |
Finished | Jul 01 04:27:13 PM PDT 24 |
Peak memory | 201832 kb |
Host | smart-73a53dc3-fc37-4c4d-8ad6-e35456e090b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320960905 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.320960905 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3195518990 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 438779460 ps |
CPU time | 4.03 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:25 PM PDT 24 |
Peak memory | 202120 kb |
Host | smart-6ec0da78-21a5-4a76-baa1-c2b009f95ab2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195518990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.3195518990 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1362993250 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 11002034 ps |
CPU time | 0.63 seconds |
Started | Jul 01 04:26:53 PM PDT 24 |
Finished | Jul 01 04:27:05 PM PDT 24 |
Peak memory | 201744 kb |
Host | smart-6dd58289-b30b-4ff1-a3be-77689a277fee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362993250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.1362993250 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2899040823 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 805523967 ps |
CPU time | 2.14 seconds |
Started | Jul 01 04:27:05 PM PDT 24 |
Finished | Jul 01 04:27:20 PM PDT 24 |
Peak memory | 201980 kb |
Host | smart-e4ff5181-e605-4344-8f33-92ba83c86392 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899040823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2899040823 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.763438054 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 62701732 ps |
CPU time | 0.74 seconds |
Started | Jul 01 04:27:19 PM PDT 24 |
Finished | Jul 01 04:27:32 PM PDT 24 |
Peak memory | 201860 kb |
Host | smart-e0152613-6bb6-4d50-b55c-18c84a8cd045 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763438054 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.763438054 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2838511212 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 935462548 ps |
CPU time | 2.68 seconds |
Started | Jul 01 04:27:03 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 210300 kb |
Host | smart-fb56052e-faf7-470e-8ece-bd5850f8f439 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838511212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.2838511212 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3782833285 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 151062030 ps |
CPU time | 1.62 seconds |
Started | Jul 01 04:27:04 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 211264 kb |
Host | smart-99aeba24-fd8a-411e-9ea5-2fc467851daa |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782833285 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3782833285 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.183898133 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 16160799 ps |
CPU time | 0.63 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:22 PM PDT 24 |
Peak memory | 201748 kb |
Host | smart-570969ff-13c8-423c-aab6-ce479a848d94 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183898133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_csr_rw.183898133 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2476651029 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 451276576 ps |
CPU time | 2.06 seconds |
Started | Jul 01 04:26:56 PM PDT 24 |
Finished | Jul 01 04:27:09 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-16bca6da-7356-4f49-b658-7f352fc971a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476651029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2476651029 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2351012706 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 17659143 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:27:05 PM PDT 24 |
Finished | Jul 01 04:27:20 PM PDT 24 |
Peak memory | 201864 kb |
Host | smart-cd798eb2-b78f-4876-9519-423cc3844c2e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351012706 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.2351012706 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2540257488 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 31538869 ps |
CPU time | 2.42 seconds |
Started | Jul 01 04:27:05 PM PDT 24 |
Finished | Jul 01 04:27:22 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-90f108a2-4eb6-442a-ae5a-42e1f0166831 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540257488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.2540257488 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2918632541 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 301633826 ps |
CPU time | 2.68 seconds |
Started | Jul 01 04:27:27 PM PDT 24 |
Finished | Jul 01 04:27:41 PM PDT 24 |
Peak memory | 210392 kb |
Host | smart-c0d4e39e-2fa0-4fe0-97fc-e77f96907531 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918632541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2918632541 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3822823863 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 41874740 ps |
CPU time | 0.64 seconds |
Started | Jul 01 04:27:04 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 201688 kb |
Host | smart-93494f24-52a3-4bf6-88a2-d199eaff4570 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822823863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.3822823863 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3223330898 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 231803476 ps |
CPU time | 2.02 seconds |
Started | Jul 01 04:27:12 PM PDT 24 |
Finished | Jul 01 04:27:28 PM PDT 24 |
Peak memory | 202136 kb |
Host | smart-218cb693-cd92-404a-ae5c-43c23fff7bad |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223330898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3223330898 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2379144978 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 33487279 ps |
CPU time | 0.79 seconds |
Started | Jul 01 04:26:58 PM PDT 24 |
Finished | Jul 01 04:27:11 PM PDT 24 |
Peak memory | 201852 kb |
Host | smart-55cf3a78-236f-44d3-bea5-a3066469a371 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379144978 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2379144978 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2304735970 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 85114635 ps |
CPU time | 3.01 seconds |
Started | Jul 01 04:27:02 PM PDT 24 |
Finished | Jul 01 04:27:19 PM PDT 24 |
Peak memory | 202276 kb |
Host | smart-97b42af3-bfa5-4865-98a9-29241b37a409 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304735970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.2304735970 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2786422912 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 1069237257 ps |
CPU time | 1.56 seconds |
Started | Jul 01 04:27:00 PM PDT 24 |
Finished | Jul 01 04:27:14 PM PDT 24 |
Peak memory | 201796 kb |
Host | smart-f38c13a6-652a-4c97-bddc-3822fae16007 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786422912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.2786422912 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1793861991 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 51929327 ps |
CPU time | 1.39 seconds |
Started | Jul 01 04:27:16 PM PDT 24 |
Finished | Jul 01 04:27:31 PM PDT 24 |
Peak memory | 210224 kb |
Host | smart-077bd4ac-6caa-4a8d-8eca-f6689dc8f193 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793861991 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1793861991 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4258775746 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 116123551 ps |
CPU time | 0.63 seconds |
Started | Jul 01 04:27:10 PM PDT 24 |
Finished | Jul 01 04:27:25 PM PDT 24 |
Peak memory | 201744 kb |
Host | smart-af215140-f4f1-4471-a9f9-72c701942c7e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258775746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.4258775746 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2761904773 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 1741723795 ps |
CPU time | 3.07 seconds |
Started | Jul 01 04:27:07 PM PDT 24 |
Finished | Jul 01 04:27:24 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-8a8f93cf-3a5d-4c09-b9ee-c50e82d2b519 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761904773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.2761904773 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.222395869 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 24207419 ps |
CPU time | 0.72 seconds |
Started | Jul 01 04:27:05 PM PDT 24 |
Finished | Jul 01 04:27:20 PM PDT 24 |
Peak memory | 201836 kb |
Host | smart-c1bb7ee1-b33a-4785-8331-4ff61a87f65b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222395869 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.222395869 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3053574606 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 139420390 ps |
CPU time | 3.38 seconds |
Started | Jul 01 04:27:28 PM PDT 24 |
Finished | Jul 01 04:27:43 PM PDT 24 |
Peak memory | 210420 kb |
Host | smart-bf4f9a87-f2b8-41ab-846d-e80a62162570 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053574606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.3053574606 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4280581157 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 253219201 ps |
CPU time | 2.04 seconds |
Started | Jul 01 04:27:09 PM PDT 24 |
Finished | Jul 01 04:27:27 PM PDT 24 |
Peak memory | 210184 kb |
Host | smart-dbcd7639-3de0-4296-89f7-721bb38a7b34 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280581157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.4280581157 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3881952060 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 41801965544 ps |
CPU time | 696.11 seconds |
Started | Jul 01 04:58:01 PM PDT 24 |
Finished | Jul 01 05:09:44 PM PDT 24 |
Peak memory | 362460 kb |
Host | smart-904b519b-7939-47c9-9c31-ede51dbec947 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881952060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.3881952060 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.4140266258 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 15260351 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:58:01 PM PDT 24 |
Finished | Jul 01 04:58:09 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-45bc14c7-0b49-4cd0-bbff-a447af9266e6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140266258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.4140266258 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.3090595368 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 541308623 ps |
CPU time | 36.37 seconds |
Started | Jul 01 04:58:04 PM PDT 24 |
Finished | Jul 01 04:58:46 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-3a10b805-5979-4369-a49c-5e93f4053b57 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090595368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 3090595368 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.377266125 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 166568159 ps |
CPU time | 1.37 seconds |
Started | Jul 01 04:58:02 PM PDT 24 |
Finished | Jul 01 04:58:10 PM PDT 24 |
Peak memory | 210852 kb |
Host | smart-7c77d4c5-149a-4218-948b-fa4502b90714 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377266125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca lation.377266125 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.3189120134 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 97914871 ps |
CPU time | 43.27 seconds |
Started | Jul 01 04:58:00 PM PDT 24 |
Finished | Jul 01 04:58:50 PM PDT 24 |
Peak memory | 303012 kb |
Host | smart-b18a1a1e-d997-4145-a006-421ed33ebf63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189120134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.3189120134 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3634654732 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 210939262 ps |
CPU time | 3.07 seconds |
Started | Jul 01 04:58:06 PM PDT 24 |
Finished | Jul 01 04:58:14 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-05ec83e3-78e1-4503-8667-417c3b0621f9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634654732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.3634654732 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.3943260605 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 516134197 ps |
CPU time | 5.56 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 04:58:19 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-1e239e98-ec74-4f96-bbbf-5afceb24fb66 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943260605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.3943260605 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.358391935 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 3468286085 ps |
CPU time | 1074.14 seconds |
Started | Jul 01 04:57:57 PM PDT 24 |
Finished | Jul 01 05:16:00 PM PDT 24 |
Peak memory | 371704 kb |
Host | smart-19ede460-1d1e-4f7c-a336-d92f91db3cf2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358391935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multipl e_keys.358391935 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.3980119514 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 572293291 ps |
CPU time | 5.2 seconds |
Started | Jul 01 04:58:02 PM PDT 24 |
Finished | Jul 01 04:58:14 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-2aa1283d-f05d-4641-b5fa-5c5c056198e2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980119514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.3980119514 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3260387086 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 23703208671 ps |
CPU time | 318.44 seconds |
Started | Jul 01 04:58:00 PM PDT 24 |
Finished | Jul 01 05:03:26 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-946de1a0-a14a-4c21-a54e-bd6e5fb40731 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260387086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.3260387086 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.455458091 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 27280412 ps |
CPU time | 0.76 seconds |
Started | Jul 01 04:58:03 PM PDT 24 |
Finished | Jul 01 04:58:10 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-65ae1349-bf27-49f0-af89-e1b03d83e1a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455458091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.455458091 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.2681129125 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 105983232835 ps |
CPU time | 1617.24 seconds |
Started | Jul 01 04:58:02 PM PDT 24 |
Finished | Jul 01 05:25:06 PM PDT 24 |
Peak memory | 373744 kb |
Host | smart-60b0f28f-42aa-4b37-b393-8454265d1d6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681129125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2681129125 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.3375365039 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 74740234 ps |
CPU time | 2.26 seconds |
Started | Jul 01 04:57:56 PM PDT 24 |
Finished | Jul 01 04:58:07 PM PDT 24 |
Peak memory | 206212 kb |
Host | smart-44555f10-9b38-4db4-9f86-6509c7ec7677 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375365039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3375365039 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.216165091 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 14787393950 ps |
CPU time | 2398.48 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 05:38:12 PM PDT 24 |
Peak memory | 370728 kb |
Host | smart-1b53efd9-15d4-4273-92c7-0bc7d62521be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216165091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_stress_all.216165091 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2633886291 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 2262972868 ps |
CPU time | 179.23 seconds |
Started | Jul 01 04:58:02 PM PDT 24 |
Finished | Jul 01 05:01:08 PM PDT 24 |
Peak memory | 385432 kb |
Host | smart-ed965cfa-76a5-47b7-910f-14420191f9b0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2633886291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.2633886291 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3632606303 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 2832050668 ps |
CPU time | 285.66 seconds |
Started | Jul 01 04:58:01 PM PDT 24 |
Finished | Jul 01 05:02:54 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-b3d20be7-aad1-4717-a5f2-87e7784053e0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632606303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.3632606303 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.989645484 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 427684412 ps |
CPU time | 29.43 seconds |
Started | Jul 01 04:58:04 PM PDT 24 |
Finished | Jul 01 04:58:39 PM PDT 24 |
Peak memory | 300856 kb |
Host | smart-32c10a19-efc3-4959-8e62-fc28430085e3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989645484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_throughput_w_partial_write.989645484 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.3870631802 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 13328847407 ps |
CPU time | 891.05 seconds |
Started | Jul 01 04:58:07 PM PDT 24 |
Finished | Jul 01 05:13:02 PM PDT 24 |
Peak memory | 371308 kb |
Host | smart-ca06a8f4-0592-4615-ae51-114f3f4893f4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870631802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.3870631802 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.3213320695 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 25146374 ps |
CPU time | 0.66 seconds |
Started | Jul 01 04:58:09 PM PDT 24 |
Finished | Jul 01 04:58:13 PM PDT 24 |
Peak memory | 202376 kb |
Host | smart-75ad1941-c018-45ea-a2b0-002350996041 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213320695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.3213320695 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.3650294611 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 1903929557 ps |
CPU time | 30.83 seconds |
Started | Jul 01 04:58:03 PM PDT 24 |
Finished | Jul 01 04:58:40 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-e8561830-df02-4177-be4f-ea52f823d2b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650294611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 3650294611 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.1728162787 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 36947748753 ps |
CPU time | 727.51 seconds |
Started | Jul 01 04:58:13 PM PDT 24 |
Finished | Jul 01 05:10:23 PM PDT 24 |
Peak memory | 371476 kb |
Host | smart-12729502-6e71-4995-8c0c-2eb909d41c0d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728162787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.1728162787 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.322219645 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 653976483 ps |
CPU time | 8.2 seconds |
Started | Jul 01 04:58:09 PM PDT 24 |
Finished | Jul 01 04:58:21 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-54ccacbd-8f86-4ba2-8da1-5c2301aaea1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322219645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esca lation.322219645 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.2121948934 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 233536939 ps |
CPU time | 8.96 seconds |
Started | Jul 01 04:58:14 PM PDT 24 |
Finished | Jul 01 04:58:24 PM PDT 24 |
Peak memory | 241292 kb |
Host | smart-f4f17915-5845-4e3a-8d8f-69f7b29a3ffd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121948934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.2121948934 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3775599925 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 1673467304 ps |
CPU time | 3.68 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 04:58:17 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-ba3c7b11-0d19-4a1a-bda7-32deba87ad88 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775599925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.3775599925 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.720315612 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 465449765 ps |
CPU time | 10.66 seconds |
Started | Jul 01 04:58:11 PM PDT 24 |
Finished | Jul 01 04:58:25 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-6c59279c-973d-4341-b431-27ccf6a461cc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720315612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ mem_walk.720315612 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.1193936429 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 8941319990 ps |
CPU time | 678.92 seconds |
Started | Jul 01 04:58:02 PM PDT 24 |
Finished | Jul 01 05:09:27 PM PDT 24 |
Peak memory | 375112 kb |
Host | smart-38c028a6-560d-4ba7-97d4-871ad82d970e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193936429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.1193936429 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.1265207308 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 555636339 ps |
CPU time | 45.62 seconds |
Started | Jul 01 04:58:00 PM PDT 24 |
Finished | Jul 01 04:58:54 PM PDT 24 |
Peak memory | 317060 kb |
Host | smart-4178b587-2ca7-4378-a60f-1b0782a32fc2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265207308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.1265207308 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4269102480 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 6940213869 ps |
CPU time | 249.49 seconds |
Started | Jul 01 04:58:02 PM PDT 24 |
Finished | Jul 01 05:02:18 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-9c63257a-13a0-4ea3-a195-9595a1e8ab1b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269102480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.4269102480 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.2554810621 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 50654835 ps |
CPU time | 0.77 seconds |
Started | Jul 01 04:58:07 PM PDT 24 |
Finished | Jul 01 04:58:12 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-8f6516ad-0cd7-4932-83af-91ed902d1901 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554810621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2554810621 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.3453621375 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 2602184922 ps |
CPU time | 151.19 seconds |
Started | Jul 01 04:58:15 PM PDT 24 |
Finished | Jul 01 05:00:48 PM PDT 24 |
Peak memory | 314008 kb |
Host | smart-2952dc17-368f-4cdf-ac63-1a0631023e44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453621375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3453621375 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.2454605211 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 229580820 ps |
CPU time | 3.1 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 04:58:17 PM PDT 24 |
Peak memory | 232664 kb |
Host | smart-7f72cc0e-94ca-422e-b340-a98385a363b6 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454605211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2454605211 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.2136363601 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 379646252 ps |
CPU time | 4.35 seconds |
Started | Jul 01 04:58:07 PM PDT 24 |
Finished | Jul 01 04:58:16 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-a8118423-8f22-4482-8593-12574aa9860b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136363601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2136363601 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.1487655972 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 48780682644 ps |
CPU time | 2279.22 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 05:36:13 PM PDT 24 |
Peak memory | 383424 kb |
Host | smart-29bab595-cd38-4623-96ad-a402508fad02 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487655972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.1487655972 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3127507348 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 3045466174 ps |
CPU time | 277.6 seconds |
Started | Jul 01 04:58:00 PM PDT 24 |
Finished | Jul 01 05:02:45 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-fec0c314-bc66-4927-bc8a-e065da48342b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127507348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.3127507348 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4293886514 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 157625567 ps |
CPU time | 8.79 seconds |
Started | Jul 01 04:58:09 PM PDT 24 |
Finished | Jul 01 04:58:22 PM PDT 24 |
Peak memory | 237316 kb |
Host | smart-275c7e36-96e5-4079-b8ca-879755d253f3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293886514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.4293886514 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3082568708 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 1792278072 ps |
CPU time | 228.53 seconds |
Started | Jul 01 04:58:47 PM PDT 24 |
Finished | Jul 01 05:02:39 PM PDT 24 |
Peak memory | 372872 kb |
Host | smart-a66661d7-31a6-4f65-ab07-0641078f7236 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082568708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.3082568708 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.2459570881 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 30499273 ps |
CPU time | 0.64 seconds |
Started | Jul 01 04:58:31 PM PDT 24 |
Finished | Jul 01 04:58:37 PM PDT 24 |
Peak memory | 201616 kb |
Host | smart-dbe145f5-529c-4ec3-85e7-0e47fdcac9b9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459570881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.2459570881 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.465582972 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 3496759083 ps |
CPU time | 44.04 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 04:59:12 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-ec65b7b4-d975-4d22-8736-5b58012c11a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465582972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection. 465582972 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.2378047991 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 42108672845 ps |
CPU time | 731.46 seconds |
Started | Jul 01 04:58:32 PM PDT 24 |
Finished | Jul 01 05:10:49 PM PDT 24 |
Peak memory | 363500 kb |
Host | smart-872f8ec9-0aa1-4834-83fe-ed7cd93cdecf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378047991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.2378047991 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.1683516394 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 2257995019 ps |
CPU time | 6.8 seconds |
Started | Jul 01 04:58:33 PM PDT 24 |
Finished | Jul 01 04:58:45 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-1eab961e-38f7-4cf3-bedd-286fb48852eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683516394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.1683516394 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.1373610514 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 87550949 ps |
CPU time | 2.09 seconds |
Started | Jul 01 04:58:29 PM PDT 24 |
Finished | Jul 01 04:58:36 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-78c75761-3f43-4fa6-abec-eb6897de5291 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373610514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.1373610514 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3880785039 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 49069340 ps |
CPU time | 2.7 seconds |
Started | Jul 01 04:58:31 PM PDT 24 |
Finished | Jul 01 04:58:39 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-f082637b-6a42-4369-adbf-f98c2ce7dbef |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880785039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.3880785039 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.3539074992 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 2617131026 ps |
CPU time | 12.14 seconds |
Started | Jul 01 04:58:33 PM PDT 24 |
Finished | Jul 01 04:58:50 PM PDT 24 |
Peak memory | 211300 kb |
Host | smart-9357e394-3852-42ce-a085-a021d44a06b7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539074992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.3539074992 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.2541032497 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 6078717378 ps |
CPU time | 594.25 seconds |
Started | Jul 01 04:58:32 PM PDT 24 |
Finished | Jul 01 05:08:31 PM PDT 24 |
Peak memory | 372480 kb |
Host | smart-8ca112f3-2606-4d4e-a908-5f16339584fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541032497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2541032497 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.3992639254 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 484300406 ps |
CPU time | 57.24 seconds |
Started | Jul 01 04:58:35 PM PDT 24 |
Finished | Jul 01 04:59:37 PM PDT 24 |
Peak memory | 314964 kb |
Host | smart-6f2d87ea-70cd-4fed-ba03-7c15dffc0909 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992639254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.3992639254 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3586137636 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 54554062166 ps |
CPU time | 226.03 seconds |
Started | Jul 01 04:58:28 PM PDT 24 |
Finished | Jul 01 05:02:20 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-19647bad-cbe6-4155-b7b4-22c65b2b1bf2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586137636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.3586137636 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.296176196 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 50343020 ps |
CPU time | 0.84 seconds |
Started | Jul 01 04:58:34 PM PDT 24 |
Finished | Jul 01 04:58:40 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-b1388f43-1a76-4d27-bec4-02ad4fd10b0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296176196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.296176196 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.2911201052 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 1111224122 ps |
CPU time | 28.86 seconds |
Started | Jul 01 04:58:34 PM PDT 24 |
Finished | Jul 01 04:59:08 PM PDT 24 |
Peak memory | 253260 kb |
Host | smart-067efc81-89a5-49f0-b4f1-c924f980f6a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911201052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2911201052 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.337581948 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 135266480 ps |
CPU time | 128.69 seconds |
Started | Jul 01 04:58:33 PM PDT 24 |
Finished | Jul 01 05:00:46 PM PDT 24 |
Peak memory | 368032 kb |
Host | smart-57a7fe60-32ea-4d86-9d37-0077e254c878 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337581948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.337581948 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3793894497 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 7236525742 ps |
CPU time | 556.34 seconds |
Started | Jul 01 04:58:34 PM PDT 24 |
Finished | Jul 01 05:07:55 PM PDT 24 |
Peak memory | 380672 kb |
Host | smart-f262d408-4273-4f6b-bd11-81de5c18593e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3793894497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3793894497 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2127914136 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 3102682790 ps |
CPU time | 93.15 seconds |
Started | Jul 01 04:58:29 PM PDT 24 |
Finished | Jul 01 05:00:07 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-9f88a0d0-a9f1-474c-bd88-9384b6628643 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127914136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.2127914136 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2944552200 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 445656962 ps |
CPU time | 70.61 seconds |
Started | Jul 01 04:58:31 PM PDT 24 |
Finished | Jul 01 04:59:46 PM PDT 24 |
Peak memory | 311592 kb |
Host | smart-dcaebfc2-532d-4e0b-b163-ebcaccf42135 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944552200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2944552200 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3035695441 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 3736852230 ps |
CPU time | 1123.95 seconds |
Started | Jul 01 04:58:35 PM PDT 24 |
Finished | Jul 01 05:17:24 PM PDT 24 |
Peak memory | 362376 kb |
Host | smart-167ae4ab-5f9f-489a-9e60-4406b8307672 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035695441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3035695441 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.4122342096 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 1006795296 ps |
CPU time | 60.09 seconds |
Started | Jul 01 04:58:34 PM PDT 24 |
Finished | Jul 01 04:59:39 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-e2d6fc4c-86e3-4aee-9779-bd3195e01026 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122342096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .4122342096 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.2286526000 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 8477111788 ps |
CPU time | 562.62 seconds |
Started | Jul 01 04:58:36 PM PDT 24 |
Finished | Jul 01 05:08:04 PM PDT 24 |
Peak memory | 371584 kb |
Host | smart-82035a26-000a-42cf-b080-882dd107e19a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286526000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.2286526000 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1117793438 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 2852873079 ps |
CPU time | 9.11 seconds |
Started | Jul 01 04:58:24 PM PDT 24 |
Finished | Jul 01 04:58:38 PM PDT 24 |
Peak memory | 215232 kb |
Host | smart-dc502924-4e00-4271-b71c-5c8aec597202 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117793438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1117793438 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.3353374540 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 139177676 ps |
CPU time | 145.73 seconds |
Started | Jul 01 04:58:32 PM PDT 24 |
Finished | Jul 01 05:01:03 PM PDT 24 |
Peak memory | 368976 kb |
Host | smart-a70f0e79-036a-49ae-8ffe-59e3d0b33bef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353374540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.3353374540 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2553368326 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 58434488 ps |
CPU time | 2.85 seconds |
Started | Jul 01 04:58:34 PM PDT 24 |
Finished | Jul 01 04:58:42 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-e7e487e2-f109-4632-83f5-da2918b3fd0e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553368326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.2553368326 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.2604902041 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 133478900 ps |
CPU time | 8.48 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:58:40 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-715d89f8-b9a6-42d8-b076-6ba558c4ed76 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604902041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.2604902041 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.49761300 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 3517707739 ps |
CPU time | 1035.68 seconds |
Started | Jul 01 04:58:32 PM PDT 24 |
Finished | Jul 01 05:15:53 PM PDT 24 |
Peak memory | 366512 kb |
Host | smart-cfbdb8bf-b52c-4662-85df-0b8d0c484d7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49761300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multipl e_keys.49761300 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.864672792 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 35810867 ps |
CPU time | 1.13 seconds |
Started | Jul 01 04:58:37 PM PDT 24 |
Finished | Jul 01 04:58:43 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-ffa2453a-b870-4392-ab57-eecd282f9821 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864672792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.s ram_ctrl_partial_access.864672792 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2682960210 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 69353484283 ps |
CPU time | 351.82 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:04:16 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-5e3c573b-43c1-4491-b8f6-d3cb33b96af5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682960210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.2682960210 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.1792112073 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 9465329939 ps |
CPU time | 919.36 seconds |
Started | Jul 01 04:58:25 PM PDT 24 |
Finished | Jul 01 05:13:50 PM PDT 24 |
Peak memory | 368440 kb |
Host | smart-baf6527e-2010-4b40-af1b-1edcc3e64dc0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792112073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1792112073 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.188845028 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 4308228411 ps |
CPU time | 19.33 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:59:06 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-24f6aa82-a518-4d60-b4a7-05cb5f8b1299 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188845028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.188845028 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.2542697815 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 183511461399 ps |
CPU time | 3943.77 seconds |
Started | Jul 01 04:58:35 PM PDT 24 |
Finished | Jul 01 06:04:24 PM PDT 24 |
Peak memory | 382972 kb |
Host | smart-83612d7f-fb17-4100-b69a-4ead9dbf3874 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542697815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.2542697815 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1103075016 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 8140398064 ps |
CPU time | 569.84 seconds |
Started | Jul 01 04:58:28 PM PDT 24 |
Finished | Jul 01 05:08:04 PM PDT 24 |
Peak memory | 358524 kb |
Host | smart-5d99f312-dbc2-4b3a-9042-3584ecc5397b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1103075016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1103075016 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1937158035 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 13548627741 ps |
CPU time | 296.32 seconds |
Started | Jul 01 04:58:29 PM PDT 24 |
Finished | Jul 01 05:03:31 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-700c9e2f-7536-4405-b8a5-a4cc7975a2fb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937158035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.1937158035 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1856316467 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 62267884 ps |
CPU time | 0.93 seconds |
Started | Jul 01 04:58:34 PM PDT 24 |
Finished | Jul 01 04:58:39 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-8cbe92b1-6115-4327-8fb1-e4c747411bc8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856316467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1856316467 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2711503004 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 4192208833 ps |
CPU time | 576.14 seconds |
Started | Jul 01 04:58:31 PM PDT 24 |
Finished | Jul 01 05:08:13 PM PDT 24 |
Peak memory | 367572 kb |
Host | smart-f5383148-8fc7-487a-98b8-4bc7554f0547 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711503004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.2711503004 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.47155385 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 11923441 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:58:47 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-dade78df-3d2f-40aa-b1d6-dc9cd45e9fa2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47155385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_alert_test.47155385 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.3399936650 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 3858184615 ps |
CPU time | 65.23 seconds |
Started | Jul 01 04:58:35 PM PDT 24 |
Finished | Jul 01 04:59:45 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-3e8624aa-048c-4311-9654-35459dd313d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399936650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .3399936650 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.1051076455 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 6580903632 ps |
CPU time | 896.33 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 05:13:47 PM PDT 24 |
Peak memory | 374508 kb |
Host | smart-3151c844-4413-4d3a-95ac-fe8a64fd9327 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051076455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.1051076455 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.799726147 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 148356426 ps |
CPU time | 2.1 seconds |
Started | Jul 01 04:58:44 PM PDT 24 |
Finished | Jul 01 04:58:49 PM PDT 24 |
Peak memory | 216236 kb |
Host | smart-5e6ac5fb-8f5e-4f7b-be28-deff208fcc40 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799726147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.sram_ctrl_max_throughput.799726147 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1104257037 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 417438840 ps |
CPU time | 5.79 seconds |
Started | Jul 01 04:58:39 PM PDT 24 |
Finished | Jul 01 04:58:49 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-1ece01bc-0b52-4506-a86e-e039e62daec1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104257037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.1104257037 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.4091071658 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 1246963240 ps |
CPU time | 5.72 seconds |
Started | Jul 01 04:58:37 PM PDT 24 |
Finished | Jul 01 04:58:48 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-6b1580c1-0aa1-47a8-aa26-1e2f44a54e3e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091071658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.4091071658 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.2324637059 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 10712371317 ps |
CPU time | 1142.82 seconds |
Started | Jul 01 04:58:34 PM PDT 24 |
Finished | Jul 01 05:17:42 PM PDT 24 |
Peak memory | 364516 kb |
Host | smart-c952211a-87f8-4083-be59-f433fc56ef79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324637059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.2324637059 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.4166941411 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 2153066312 ps |
CPU time | 17.53 seconds |
Started | Jul 01 04:58:35 PM PDT 24 |
Finished | Jul 01 04:58:58 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-34dd00ef-0798-4d6e-9ed3-af8d0e45486f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166941411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.4166941411 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1290493887 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 26340944737 ps |
CPU time | 337.78 seconds |
Started | Jul 01 04:58:50 PM PDT 24 |
Finished | Jul 01 05:04:32 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-9add157f-ad90-42a5-b196-c0d1d2e0ac59 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290493887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.1290493887 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.294253976 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 96106122 ps |
CPU time | 0.81 seconds |
Started | Jul 01 04:58:33 PM PDT 24 |
Finished | Jul 01 04:58:39 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-ae00cc8d-2297-4e78-986d-1acce847a474 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294253976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.294253976 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.3226647172 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 33603906 ps |
CPU time | 1.74 seconds |
Started | Jul 01 04:58:24 PM PDT 24 |
Finished | Jul 01 04:58:31 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-f1af786a-0960-44c7-870d-89d6cf7b405f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226647172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3226647172 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.3917208988 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 20326817273 ps |
CPU time | 1301.39 seconds |
Started | Jul 01 04:58:57 PM PDT 24 |
Finished | Jul 01 05:20:42 PM PDT 24 |
Peak memory | 372752 kb |
Host | smart-ebb4aadd-60d6-4c46-87ee-5b9ebb185e3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917208988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.3917208988 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.221390072 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 4867010775 ps |
CPU time | 289.19 seconds |
Started | Jul 01 04:58:40 PM PDT 24 |
Finished | Jul 01 05:03:33 PM PDT 24 |
Peak memory | 373748 kb |
Host | smart-be1ed31c-64b9-446e-a9c5-02a29b7d1b58 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=221390072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.221390072 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2447876235 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 3439319935 ps |
CPU time | 316.23 seconds |
Started | Jul 01 04:58:24 PM PDT 24 |
Finished | Jul 01 05:03:45 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-d5fa4f9e-266b-4d93-8eec-f127ecb159ff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447876235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.2447876235 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.908710540 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1510557792 ps |
CPU time | 100.07 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 05:00:32 PM PDT 24 |
Peak memory | 356840 kb |
Host | smart-c57bc944-13d6-4f6f-9ca9-c44de116b7dd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908710540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.908710540 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3886608758 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 17976174179 ps |
CPU time | 1191.47 seconds |
Started | Jul 01 04:58:42 PM PDT 24 |
Finished | Jul 01 05:18:37 PM PDT 24 |
Peak memory | 371628 kb |
Host | smart-7159818a-0add-4499-b0c5-94b57a338986 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886608758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.3886608758 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.4086064775 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 30884400 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:58:35 PM PDT 24 |
Finished | Jul 01 04:58:41 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-94f120ae-5e1f-4183-a4aa-7698a8db49f8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086064775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.4086064775 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.2619090384 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 364540139 ps |
CPU time | 22.56 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 04:59:13 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-532b0008-a5ac-404f-b9ea-fad8bf81108a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619090384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .2619090384 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.2300854703 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 11666000930 ps |
CPU time | 369.25 seconds |
Started | Jul 01 04:58:37 PM PDT 24 |
Finished | Jul 01 05:04:51 PM PDT 24 |
Peak memory | 363080 kb |
Host | smart-b3530665-8e4f-439d-903d-f912421994d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300854703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.2300854703 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.3851924493 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 698563502 ps |
CPU time | 6.84 seconds |
Started | Jul 01 04:58:36 PM PDT 24 |
Finished | Jul 01 04:58:48 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-1af4ebc1-f9b6-439a-8707-f3c9dedc0173 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851924493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.3851924493 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.2564659077 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 63046665 ps |
CPU time | 8.8 seconds |
Started | Jul 01 04:58:32 PM PDT 24 |
Finished | Jul 01 04:58:46 PM PDT 24 |
Peak memory | 240608 kb |
Host | smart-dd0d2bfa-03ab-478e-aa54-e11315e5ab55 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564659077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.2564659077 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3075795208 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 197162133 ps |
CPU time | 3.3 seconds |
Started | Jul 01 04:58:35 PM PDT 24 |
Finished | Jul 01 04:58:43 PM PDT 24 |
Peak memory | 211168 kb |
Host | smart-72cf0b87-3270-48b7-af5f-4d7a2093aba8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075795208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.3075795208 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.3421006795 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 468231788 ps |
CPU time | 5.55 seconds |
Started | Jul 01 04:58:32 PM PDT 24 |
Finished | Jul 01 04:58:43 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-1242ebfb-1b65-4af8-81f5-a600d579a50d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421006795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.3421006795 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.486308952 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 45873953280 ps |
CPU time | 596.93 seconds |
Started | Jul 01 04:58:36 PM PDT 24 |
Finished | Jul 01 05:08:38 PM PDT 24 |
Peak memory | 360712 kb |
Host | smart-d5badbc7-00cc-428a-863a-ab38719a64d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486308952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip le_keys.486308952 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.4252697871 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 982641424 ps |
CPU time | 18.62 seconds |
Started | Jul 01 04:58:44 PM PDT 24 |
Finished | Jul 01 04:59:06 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-9137b3cf-e8ea-47d8-aab9-f52709873e99 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252697871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.4252697871 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1861221192 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 4608256649 ps |
CPU time | 340.66 seconds |
Started | Jul 01 04:58:32 PM PDT 24 |
Finished | Jul 01 05:04:18 PM PDT 24 |
Peak memory | 203016 kb |
Host | smart-a0f48f7f-ebba-44dd-b0a3-61d283189c23 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861221192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.1861221192 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.2999227372 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 43479919 ps |
CPU time | 0.75 seconds |
Started | Jul 01 04:58:49 PM PDT 24 |
Finished | Jul 01 04:58:54 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-949bf873-1ca0-4353-8aeb-4d842529c92f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999227372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2999227372 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.2026230087 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 10267877859 ps |
CPU time | 353.92 seconds |
Started | Jul 01 04:58:39 PM PDT 24 |
Finished | Jul 01 05:04:37 PM PDT 24 |
Peak memory | 371328 kb |
Host | smart-b92ee2e0-755a-424d-979b-79c009552ac0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026230087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2026230087 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.1412878846 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 380073951 ps |
CPU time | 7.33 seconds |
Started | Jul 01 04:58:45 PM PDT 24 |
Finished | Jul 01 04:58:55 PM PDT 24 |
Peak memory | 234940 kb |
Host | smart-02a992e9-2305-45b9-85fb-6ad8ea1ff837 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412878846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1412878846 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.2082667725 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 23085131389 ps |
CPU time | 1815.92 seconds |
Started | Jul 01 04:58:36 PM PDT 24 |
Finished | Jul 01 05:28:57 PM PDT 24 |
Peak memory | 375732 kb |
Host | smart-52a8b7b2-96ec-4b6b-86af-e315183d6ecc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082667725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.2082667725 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.674262081 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 832714482 ps |
CPU time | 46.39 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 04:59:29 PM PDT 24 |
Peak memory | 275524 kb |
Host | smart-0349d274-104e-49c7-90a0-940e513aecce |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=674262081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.674262081 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2974700079 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 14569968814 ps |
CPU time | 396.48 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 05:05:19 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-3abb4729-3ef9-426d-8863-c24a5093e028 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974700079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.2974700079 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1342336055 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 68996346 ps |
CPU time | 9.97 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 04:58:53 PM PDT 24 |
Peak memory | 251628 kb |
Host | smart-0c092a73-6c8c-47d8-865a-b04bb318f249 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342336055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1342336055 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.422311329 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 4294602905 ps |
CPU time | 295.4 seconds |
Started | Jul 01 04:58:37 PM PDT 24 |
Finished | Jul 01 05:03:37 PM PDT 24 |
Peak memory | 368548 kb |
Host | smart-aaf4213c-c1ca-4263-bb64-867e82397e34 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422311329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_access_during_key_req.422311329 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.3762775491 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 13812419 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:58:39 PM PDT 24 |
Finished | Jul 01 04:58:44 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-7fafd173-12b1-451a-b95f-7f31f3b8ae25 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762775491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3762775491 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.3805643978 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 4507610759 ps |
CPU time | 68.2 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:59:54 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-df346bb5-1e7f-4374-85ba-53f6a125cbef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805643978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .3805643978 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.1318090326 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 4801229907 ps |
CPU time | 634.53 seconds |
Started | Jul 01 04:58:37 PM PDT 24 |
Finished | Jul 01 05:09:16 PM PDT 24 |
Peak memory | 365268 kb |
Host | smart-ea2c4a48-b428-4611-a054-7d54c50c2dba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318090326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.1318090326 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.3229459548 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 624704308 ps |
CPU time | 5.58 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 04:58:58 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-cbdf2338-7d3b-4d59-8077-838030185547 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229459548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.3229459548 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.2537493138 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 249605095 ps |
CPU time | 90.7 seconds |
Started | Jul 01 04:58:44 PM PDT 24 |
Finished | Jul 01 05:00:18 PM PDT 24 |
Peak memory | 351880 kb |
Host | smart-ad45b958-e747-422d-b312-e6afd4a401e0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537493138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.2537493138 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3731802668 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 357623911 ps |
CPU time | 3.32 seconds |
Started | Jul 01 04:58:45 PM PDT 24 |
Finished | Jul 01 04:58:52 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-ba2073b2-bde3-462b-a589-e1cf766777b6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731802668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3731802668 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.3163919849 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 270735491 ps |
CPU time | 9.08 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:58:55 PM PDT 24 |
Peak memory | 211224 kb |
Host | smart-6354c3f3-08c0-47d9-a88f-d38b69057acc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163919849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.3163919849 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.1628907212 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 11465811885 ps |
CPU time | 126.78 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 05:01:10 PM PDT 24 |
Peak memory | 344340 kb |
Host | smart-bca0a407-5e41-46e9-beb0-cd9428364726 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628907212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.1628907212 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.267230360 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 240153349 ps |
CPU time | 11.71 seconds |
Started | Jul 01 04:58:42 PM PDT 24 |
Finished | Jul 01 04:58:57 PM PDT 24 |
Peak memory | 247912 kb |
Host | smart-28bc2bb9-1d46-42fe-9e35-57cce43fa786 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267230360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s ram_ctrl_partial_access.267230360 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2440183961 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 24386124512 ps |
CPU time | 309.27 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 05:03:52 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-3dd88502-782d-47c5-ae2b-33e34ff07b71 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440183961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.2440183961 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.1843329406 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 136314038 ps |
CPU time | 0.74 seconds |
Started | Jul 01 04:58:49 PM PDT 24 |
Finished | Jul 01 04:58:54 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-0d3ae4e6-8b6c-4c61-a9c7-73537504391d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843329406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1843329406 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.903430256 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 7785846758 ps |
CPU time | 947.96 seconds |
Started | Jul 01 04:58:42 PM PDT 24 |
Finished | Jul 01 05:14:34 PM PDT 24 |
Peak memory | 375404 kb |
Host | smart-b4337580-b2cc-4e25-8d17-8e55944e89b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903430256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.903430256 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.2463761662 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 3173880927 ps |
CPU time | 17.04 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:59:03 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-161e4ac5-92e5-49b5-afff-c9beecff48ca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463761662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2463761662 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1547946410 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 2240325677 ps |
CPU time | 275.02 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 05:03:32 PM PDT 24 |
Peak memory | 369456 kb |
Host | smart-10360a5c-d9bf-40bd-8dfd-c1e33c9b9a83 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1547946410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1547946410 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.275078850 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 32318201890 ps |
CPU time | 400.36 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 05:05:33 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-75441f35-89b4-4662-971f-3092b66ac0b2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275078850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14 .sram_ctrl_stress_pipeline.275078850 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1373185203 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 173604015 ps |
CPU time | 4.28 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 04:58:47 PM PDT 24 |
Peak memory | 225432 kb |
Host | smart-8ceef695-196b-40d7-8266-d59d8c7707fb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373185203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1373185203 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.4266746159 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 1366281485 ps |
CPU time | 157.29 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 05:01:27 PM PDT 24 |
Peak memory | 324432 kb |
Host | smart-0d9ea262-d32a-4df7-983c-f80185b62a73 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266746159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.4266746159 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.1753721344 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 24034990 ps |
CPU time | 0.69 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:58:47 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-388ef47e-f37a-454f-9673-267760f9f4a5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753721344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.1753721344 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.1170704093 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 4214399428 ps |
CPU time | 43.86 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 04:59:26 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-6aa2f0f0-139a-430d-a0e1-24508d09a0f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170704093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .1170704093 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.1761165940 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 389158760 ps |
CPU time | 1.87 seconds |
Started | Jul 01 04:58:42 PM PDT 24 |
Finished | Jul 01 04:58:47 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-2859787c-ce57-4963-b8b7-56f543e83f60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761165940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.1761165940 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.923901894 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 522238828 ps |
CPU time | 152.42 seconds |
Started | Jul 01 04:58:55 PM PDT 24 |
Finished | Jul 01 05:01:32 PM PDT 24 |
Peak memory | 370484 kb |
Host | smart-eee524f0-c290-4df4-b736-8ccfd19e3100 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923901894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.sram_ctrl_max_throughput.923901894 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.454021942 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 225988795 ps |
CPU time | 5.37 seconds |
Started | Jul 01 04:58:41 PM PDT 24 |
Finished | Jul 01 04:58:50 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-aa1f8760-8dc6-41e8-9fcb-43be9d5550dc |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454021942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_mem_partial_access.454021942 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.4119574120 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 284261125 ps |
CPU time | 4.54 seconds |
Started | Jul 01 04:58:37 PM PDT 24 |
Finished | Jul 01 04:58:46 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-3057cfa8-6be7-48c4-832d-82671c8dc31f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119574120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.4119574120 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.59916896 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 456142203 ps |
CPU time | 23.61 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:59:20 PM PDT 24 |
Peak memory | 272484 kb |
Host | smart-bf735d08-2996-4760-9ec3-e7ad2cca42b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59916896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multipl e_keys.59916896 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.590729425 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 631457831 ps |
CPU time | 12.7 seconds |
Started | Jul 01 04:58:41 PM PDT 24 |
Finished | Jul 01 04:58:57 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-d2079732-e990-4dd4-82fa-429e9979a8b2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590729425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s ram_ctrl_partial_access.590729425 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.730713258 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 14607071183 ps |
CPU time | 274.72 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 05:03:25 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-ae0c46f9-6f81-4a78-8db9-ce152d9d9bdd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730713258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.sram_ctrl_partial_access_b2b.730713258 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.281532678 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 66813735 ps |
CPU time | 0.73 seconds |
Started | Jul 01 04:58:41 PM PDT 24 |
Finished | Jul 01 04:58:45 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-e76f081d-d508-4fb7-9a20-2116669ae29c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281532678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.281532678 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.4058400176 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 33777198059 ps |
CPU time | 1317.15 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 05:20:50 PM PDT 24 |
Peak memory | 356184 kb |
Host | smart-39807fed-5180-4b47-8362-7505743a3fa1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058400176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.4058400176 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.1830129615 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 2165143917 ps |
CPU time | 12.27 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:58:59 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-5787b100-1297-4884-8007-62e318f1c68d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830129615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1830129615 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.3628829001 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 123447387617 ps |
CPU time | 2037.19 seconds |
Started | Jul 01 04:58:42 PM PDT 24 |
Finished | Jul 01 05:32:43 PM PDT 24 |
Peak memory | 380932 kb |
Host | smart-93c63732-f319-48a8-86ac-6b73472d56ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628829001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.3628829001 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2187069258 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 5342757339 ps |
CPU time | 59.43 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:59:46 PM PDT 24 |
Peak memory | 274932 kb |
Host | smart-07e66e83-bd6d-40f5-a817-9e6159d1f5c6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2187069258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2187069258 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1715653787 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 1804145892 ps |
CPU time | 172.06 seconds |
Started | Jul 01 04:58:33 PM PDT 24 |
Finished | Jul 01 05:01:30 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-2ef4ee48-fa19-4c33-9246-d383ce664a04 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715653787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.1715653787 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.863815811 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 113098126 ps |
CPU time | 1.68 seconds |
Started | Jul 01 04:58:40 PM PDT 24 |
Finished | Jul 01 04:58:45 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-f63bed41-0c42-4b36-a4eb-0d6e30cf86d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863815811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.863815811 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1104869216 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 8041394064 ps |
CPU time | 1647.32 seconds |
Started | Jul 01 04:58:45 PM PDT 24 |
Finished | Jul 01 05:26:17 PM PDT 24 |
Peak memory | 372404 kb |
Host | smart-e9171440-4702-4194-81cd-66761b3d0864 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104869216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.1104869216 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.629831750 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 13081813 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 04:58:51 PM PDT 24 |
Peak memory | 202272 kb |
Host | smart-01bdb10c-f2cb-42c5-ae9a-f97d6a4b6662 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629831750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.629831750 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.3053630309 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 1792619798 ps |
CPU time | 18.84 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 04:59:26 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-08dc7f10-c336-46b9-8ec4-7d4761d37292 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053630309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .3053630309 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.4199867279 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 39028595384 ps |
CPU time | 748.29 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 05:11:15 PM PDT 24 |
Peak memory | 374648 kb |
Host | smart-b53074d8-1b92-4d3a-8691-0a1d2d036024 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199867279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.4199867279 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.2577729857 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 471521524 ps |
CPU time | 5.35 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 04:58:48 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-405ce0f3-d52c-49fb-b05e-0a9f01425340 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577729857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2577729857 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.350845095 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 457443145 ps |
CPU time | 1.46 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 04:58:52 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-d5b0a3e6-8a46-4f8b-8c70-8135ea879a4b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350845095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.sram_ctrl_max_throughput.350845095 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1126567011 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 680009075 ps |
CPU time | 6.12 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 04:58:48 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-71d0d22c-c203-4f76-813a-813ea0b0889f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126567011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.1126567011 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.3474277858 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 375556846 ps |
CPU time | 5.85 seconds |
Started | Jul 01 04:58:40 PM PDT 24 |
Finished | Jul 01 04:58:49 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-338ac6db-9770-4f46-93c6-eb9be28c256f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474277858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.3474277858 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.3639412596 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 16023904888 ps |
CPU time | 747.68 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 05:11:21 PM PDT 24 |
Peak memory | 369216 kb |
Host | smart-7477c791-c5b3-46fd-89ce-e9d052cfff64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639412596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.3639412596 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.341952640 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 159155432 ps |
CPU time | 3.13 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 04:58:45 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-50c1a5a7-2f7e-4362-817e-fbd33871f87a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341952640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_partial_access.341952640 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2809871828 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 3552727467 ps |
CPU time | 270.36 seconds |
Started | Jul 01 04:58:37 PM PDT 24 |
Finished | Jul 01 05:03:12 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-f0ab50ba-d213-4572-875b-b637bb7fd39f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809871828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.2809871828 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.1620669851 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 42657600 ps |
CPU time | 0.75 seconds |
Started | Jul 01 04:58:53 PM PDT 24 |
Finished | Jul 01 04:58:59 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-84896240-d8a5-4c2a-bde1-b9c3098f222f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620669851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1620669851 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.2195133395 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 9243400202 ps |
CPU time | 1020.18 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 05:15:43 PM PDT 24 |
Peak memory | 374752 kb |
Host | smart-a991e3c9-01a9-4fec-843e-cbe6640a3289 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195133395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2195133395 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.1711949235 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 2063003043 ps |
CPU time | 62.77 seconds |
Started | Jul 01 04:58:40 PM PDT 24 |
Finished | Jul 01 04:59:47 PM PDT 24 |
Peak memory | 313104 kb |
Host | smart-da34ce56-d1a0-42b9-ac53-ecbf799d04d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711949235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1711949235 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1085654875 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 7176699332 ps |
CPU time | 62.67 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:59:59 PM PDT 24 |
Peak memory | 297648 kb |
Host | smart-5cef268f-c32f-4c64-a647-95eb3d1e1add |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1085654875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1085654875 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.242855893 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 11056911189 ps |
CPU time | 264.34 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 05:03:17 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-bbb79e37-08d7-4ded-be7e-0e70491107a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242855893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_stress_pipeline.242855893 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3352624772 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 160280464 ps |
CPU time | 91.26 seconds |
Started | Jul 01 04:58:39 PM PDT 24 |
Finished | Jul 01 05:00:15 PM PDT 24 |
Peak memory | 337660 kb |
Host | smart-c801e5ec-96c9-4049-babc-531816fb178f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352624772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.3352624772 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3636195345 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 22142051644 ps |
CPU time | 1932.24 seconds |
Started | Jul 01 04:58:47 PM PDT 24 |
Finished | Jul 01 05:31:03 PM PDT 24 |
Peak memory | 374400 kb |
Host | smart-fe4e18dc-0041-4d45-bea8-f1195477f07c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636195345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.3636195345 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.2957807946 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 11968310 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:58:38 PM PDT 24 |
Finished | Jul 01 04:58:44 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-341b56b2-7520-4fe6-a36a-92a78bd95675 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957807946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2957807946 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.1709230047 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 7713906539 ps |
CPU time | 69.17 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:59:56 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-8a977f08-8279-48c4-bf93-d63243127e44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709230047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .1709230047 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.929151731 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 4401980804 ps |
CPU time | 527 seconds |
Started | Jul 01 04:58:42 PM PDT 24 |
Finished | Jul 01 05:07:32 PM PDT 24 |
Peak memory | 358960 kb |
Host | smart-25e5d3a1-a741-43e1-8e76-a1623b2d6991 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929151731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl e.929151731 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.773116586 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 2097106724 ps |
CPU time | 4.73 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 04:58:57 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-27e0e245-1422-4af1-8ebc-06fc79c1fbfc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773116586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esc alation.773116586 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.1762026542 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 387140816 ps |
CPU time | 46.92 seconds |
Started | Jul 01 04:58:47 PM PDT 24 |
Finished | Jul 01 04:59:38 PM PDT 24 |
Peak memory | 304996 kb |
Host | smart-664b3c1c-b5c3-4da7-b02d-0393b6a19a2e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762026542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.1762026542 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1474517303 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 65858255 ps |
CPU time | 4.18 seconds |
Started | Jul 01 04:58:51 PM PDT 24 |
Finished | Jul 01 04:59:00 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-4810d5b6-9bd0-4e93-8e0f-c06ad8687f14 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474517303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.1474517303 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.3583825422 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 291208466 ps |
CPU time | 5.92 seconds |
Started | Jul 01 04:58:53 PM PDT 24 |
Finished | Jul 01 04:59:03 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-9f3879b1-355c-4f3c-9842-9f7ea2e0e76c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583825422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.3583825422 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.1023411493 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 6737973870 ps |
CPU time | 388.31 seconds |
Started | Jul 01 04:58:49 PM PDT 24 |
Finished | Jul 01 05:05:22 PM PDT 24 |
Peak memory | 373144 kb |
Host | smart-913fe7b7-4b1d-46bd-bad2-5b03f7cb71fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023411493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1023411493 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.3740435096 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 319231709 ps |
CPU time | 3.32 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:59:00 PM PDT 24 |
Peak memory | 209364 kb |
Host | smart-4dafb9f5-a38c-4623-8e7d-0eac864e52fc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740435096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.3740435096 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4008278542 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 13943972543 ps |
CPU time | 365.78 seconds |
Started | Jul 01 04:58:41 PM PDT 24 |
Finished | Jul 01 05:04:50 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-147f8ad4-add4-4ac4-b6f3-af82a11a5090 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008278542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.4008278542 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.1247438904 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 54592919 ps |
CPU time | 0.76 seconds |
Started | Jul 01 04:58:40 PM PDT 24 |
Finished | Jul 01 04:58:45 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-bd38a4ca-f318-4f02-bdce-ab409c037c92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247438904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1247438904 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.816860028 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 6418508164 ps |
CPU time | 662.75 seconds |
Started | Jul 01 04:58:49 PM PDT 24 |
Finished | Jul 01 05:09:56 PM PDT 24 |
Peak memory | 368628 kb |
Host | smart-7770abc8-cd11-4ee5-b7a3-752eaacc1a26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816860028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.816860028 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.3578741320 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 5524034356 ps |
CPU time | 11.94 seconds |
Started | Jul 01 04:58:51 PM PDT 24 |
Finished | Jul 01 04:59:07 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-70b04790-b0f4-4302-9192-d24cec5a408b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578741320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3578741320 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.2042181891 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 16125650987 ps |
CPU time | 1287.8 seconds |
Started | Jul 01 04:58:56 PM PDT 24 |
Finished | Jul 01 05:20:28 PM PDT 24 |
Peak memory | 372572 kb |
Host | smart-65fc8740-80f0-4163-b04f-88cf38c105b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042181891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.2042181891 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3204657199 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 2880377505 ps |
CPU time | 281.94 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 05:03:29 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-836ba5b4-0acb-400c-a963-19beb3e46062 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204657199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.3204657199 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3549064884 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 327279516 ps |
CPU time | 2.86 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:59:00 PM PDT 24 |
Peak memory | 219000 kb |
Host | smart-32f4259d-1d12-4c1f-8877-ae6d762f5d0d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549064884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.3549064884 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.190326467 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 25881963 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 04:59:05 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-df7ca56e-46f7-4466-a29a-978a2e5655ad |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190326467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.190326467 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.390138041 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 38573472806 ps |
CPU time | 95.62 seconds |
Started | Jul 01 04:58:39 PM PDT 24 |
Finished | Jul 01 05:00:19 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-d57ae672-7b0b-41f4-913d-4f7e903a0954 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390138041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection. 390138041 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.2273928253 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 3245664422 ps |
CPU time | 1411.05 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 05:22:27 PM PDT 24 |
Peak memory | 374872 kb |
Host | smart-014de438-4e65-400d-9a28-e3298bd85c32 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273928253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.2273928253 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.1368976886 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 216668839 ps |
CPU time | 2.57 seconds |
Started | Jul 01 04:58:47 PM PDT 24 |
Finished | Jul 01 04:58:54 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-ac224bb4-2a7a-4a96-851e-285398152d04 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368976886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.1368976886 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.4036219169 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 97534288 ps |
CPU time | 63.4 seconds |
Started | Jul 01 04:58:43 PM PDT 24 |
Finished | Jul 01 04:59:50 PM PDT 24 |
Peak memory | 296012 kb |
Host | smart-f3bf67d9-77f8-424f-9bb3-5d06c626e2b6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036219169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.4036219169 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1972880099 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 97620918 ps |
CPU time | 3.13 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 04:58:56 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-8a548e90-d0cf-4e00-88f3-179dbda1abbd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972880099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.1972880099 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.3811178621 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 80320905 ps |
CPU time | 4.91 seconds |
Started | Jul 01 04:58:53 PM PDT 24 |
Finished | Jul 01 04:59:02 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-3cc77718-ba05-4abd-8294-8eb48fc2bc8d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811178621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3811178621 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.67782421 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 4924415618 ps |
CPU time | 404.19 seconds |
Started | Jul 01 04:58:47 PM PDT 24 |
Finished | Jul 01 05:05:35 PM PDT 24 |
Peak memory | 366192 kb |
Host | smart-92ef79b6-7ccd-4a0e-a6d7-46931743ee60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67782421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multipl e_keys.67782421 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.1663307083 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 10572012350 ps |
CPU time | 21.12 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:59:18 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-193e05a6-f0d1-41d1-9678-2b180f6fac20 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663307083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.1663307083 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3490426768 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 52289177849 ps |
CPU time | 330.02 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 05:04:23 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-8908ca2b-779c-4966-ba99-76c82021b24d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490426768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.3490426768 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.6522405 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 27824021 ps |
CPU time | 0.81 seconds |
Started | Jul 01 04:58:57 PM PDT 24 |
Finished | Jul 01 04:59:02 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-f396398f-ffa9-4712-b8bd-f022072f3445 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6522405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.6522405 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.3658005413 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 62056623050 ps |
CPU time | 359.44 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 05:05:05 PM PDT 24 |
Peak memory | 366168 kb |
Host | smart-bd2f8c1b-fd08-488b-a5cc-4927bdd02e76 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658005413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3658005413 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.692566139 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 130578652 ps |
CPU time | 153.74 seconds |
Started | Jul 01 04:58:47 PM PDT 24 |
Finished | Jul 01 05:01:25 PM PDT 24 |
Peak memory | 360252 kb |
Host | smart-57b43a2c-5337-4375-9bbb-9b0dbdeb04ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692566139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.692566139 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.4053044564 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 1166085213 ps |
CPU time | 252.78 seconds |
Started | Jul 01 04:58:51 PM PDT 24 |
Finished | Jul 01 05:03:08 PM PDT 24 |
Peak memory | 372772 kb |
Host | smart-0612371e-f20f-4725-b7ad-e74ec3cb7579 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4053044564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.4053044564 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2007241917 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 17669500865 ps |
CPU time | 314.47 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 05:04:19 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-088d6eb3-8c68-499e-9ab9-f4c01b847a52 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007241917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.2007241917 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1555239652 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 234141928 ps |
CPU time | 2.22 seconds |
Started | Jul 01 04:58:45 PM PDT 24 |
Finished | Jul 01 04:58:50 PM PDT 24 |
Peak memory | 217224 kb |
Host | smart-763385dc-2ba9-49ca-9284-fd7fe2a2570b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555239652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1555239652 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.2788755737 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 13780014768 ps |
CPU time | 1111.61 seconds |
Started | Jul 01 04:58:50 PM PDT 24 |
Finished | Jul 01 05:17:27 PM PDT 24 |
Peak memory | 372720 kb |
Host | smart-44098508-396f-47da-a5de-5abdd1b2ad80 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788755737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.2788755737 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.3553619 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 15584595 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 04:58:53 PM PDT 24 |
Peak memory | 202308 kb |
Host | smart-55530c14-dc87-41c0-adc6-9d3118011660 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sram_ctrl_alert_test.3553619 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.3116720131 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 14106015883 ps |
CPU time | 62.1 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 05:00:07 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-8aad242d-97e9-477c-b0f1-c73723493900 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116720131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .3116720131 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.3328714863 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 8211936090 ps |
CPU time | 209.51 seconds |
Started | Jul 01 04:58:55 PM PDT 24 |
Finished | Jul 01 05:02:29 PM PDT 24 |
Peak memory | 352252 kb |
Host | smart-3ea86ec3-aa02-47b5-8602-3958d49d2a27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328714863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.3328714863 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.1565430754 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 615114375 ps |
CPU time | 3.97 seconds |
Started | Jul 01 04:58:51 PM PDT 24 |
Finished | Jul 01 04:58:59 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-09ed3695-a2d0-400c-ac4a-847bae035ef9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565430754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.1565430754 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.397469192 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 132671252 ps |
CPU time | 142.2 seconds |
Started | Jul 01 04:58:50 PM PDT 24 |
Finished | Jul 01 05:01:17 PM PDT 24 |
Peak memory | 359056 kb |
Host | smart-9c766eba-4661-42d9-98da-e5d7a85c969a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397469192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.sram_ctrl_max_throughput.397469192 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.3289702598 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 173618946 ps |
CPU time | 2.72 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:09 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-6afb3392-6160-42df-8c62-b79304b3f3f9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289702598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.3289702598 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.899901860 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 1322576417 ps |
CPU time | 6.38 seconds |
Started | Jul 01 04:58:51 PM PDT 24 |
Finished | Jul 01 04:59:02 PM PDT 24 |
Peak memory | 211288 kb |
Host | smart-a76b9a2c-d949-47d0-a86e-5a9db1b055b7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899901860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _mem_walk.899901860 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.3753371169 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 3896222977 ps |
CPU time | 273.91 seconds |
Started | Jul 01 04:58:57 PM PDT 24 |
Finished | Jul 01 05:03:35 PM PDT 24 |
Peak memory | 368024 kb |
Host | smart-de02995b-e9c8-4a82-88dd-c056c2398421 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753371169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.3753371169 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.1070033885 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 834741459 ps |
CPU time | 35.92 seconds |
Started | Jul 01 04:58:51 PM PDT 24 |
Finished | Jul 01 04:59:31 PM PDT 24 |
Peak memory | 280076 kb |
Host | smart-ed68db8c-f117-4cd6-8e6b-a73210f7311b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070033885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.1070033885 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1960149939 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 46167386519 ps |
CPU time | 358.52 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 05:04:49 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-706265fe-3a63-405a-8a9d-397374a06aa7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960149939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.1960149939 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.2805434892 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 40196526 ps |
CPU time | 0.8 seconds |
Started | Jul 01 04:58:57 PM PDT 24 |
Finished | Jul 01 04:59:02 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-34553981-5688-459e-91b2-900f87593e54 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805434892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2805434892 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.2735992889 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 18883383178 ps |
CPU time | 1016.76 seconds |
Started | Jul 01 04:58:51 PM PDT 24 |
Finished | Jul 01 05:15:53 PM PDT 24 |
Peak memory | 367916 kb |
Host | smart-280acf10-9d8a-4ef1-8ee1-b80ee52765aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735992889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2735992889 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.3023548969 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 827126300 ps |
CPU time | 12.54 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 04:59:05 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-d62ac4a7-fbb6-40c5-a243-c872516ac945 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023548969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3023548969 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.3814625862 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 95885863591 ps |
CPU time | 3150.22 seconds |
Started | Jul 01 04:58:47 PM PDT 24 |
Finished | Jul 01 05:51:22 PM PDT 24 |
Peak memory | 382724 kb |
Host | smart-622f6156-eb12-4682-88a0-1dd03ef61671 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814625862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.3814625862 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3889445775 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 4738037505 ps |
CPU time | 687.67 seconds |
Started | Jul 01 04:58:55 PM PDT 24 |
Finished | Jul 01 05:10:27 PM PDT 24 |
Peak memory | 362948 kb |
Host | smart-4411e8c3-5d71-42a1-9fca-742acd853b19 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3889445775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3889445775 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.139140924 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 6082468543 ps |
CPU time | 282.21 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 05:03:45 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-bad7da59-aad2-4263-b871-4a9235d6a907 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139140924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sram_ctrl_stress_pipeline.139140924 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3824537675 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 567333479 ps |
CPU time | 118.48 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 05:00:55 PM PDT 24 |
Peak memory | 357348 kb |
Host | smart-64fe5457-3f75-40cd-81da-ff403d6a504a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824537675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3824537675 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2807546700 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 7620182571 ps |
CPU time | 724.18 seconds |
Started | Jul 01 04:58:08 PM PDT 24 |
Finished | Jul 01 05:10:16 PM PDT 24 |
Peak memory | 371676 kb |
Host | smart-a76fe34d-6577-4b42-a75e-15b8603ea308 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807546700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.2807546700 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.4270171505 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 26151095 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:58:09 PM PDT 24 |
Finished | Jul 01 04:58:13 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-117fd134-4ca2-441a-ae98-c7aa0ed22f3a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270171505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.4270171505 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.551327782 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 2804704555 ps |
CPU time | 32.45 seconds |
Started | Jul 01 04:58:08 PM PDT 24 |
Finished | Jul 01 04:58:44 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-979c4726-e938-4539-a1bd-81a876aed4b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551327782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.551327782 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.1573097055 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 8378116892 ps |
CPU time | 874.6 seconds |
Started | Jul 01 04:58:11 PM PDT 24 |
Finished | Jul 01 05:12:49 PM PDT 24 |
Peak memory | 368676 kb |
Host | smart-ac2a88f2-2b34-410a-8779-6c35d5644b16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573097055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.1573097055 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.2689502087 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 1618528831 ps |
CPU time | 5.32 seconds |
Started | Jul 01 04:58:11 PM PDT 24 |
Finished | Jul 01 04:58:20 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-48219f52-2da3-42b2-9764-213d9b42be3f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689502087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.2689502087 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.1242360565 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 87261286 ps |
CPU time | 3.43 seconds |
Started | Jul 01 04:58:09 PM PDT 24 |
Finished | Jul 01 04:58:16 PM PDT 24 |
Peak memory | 220824 kb |
Host | smart-c603dea7-42c4-42ec-b6f5-1e5d33ea4b6e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242360565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.1242360565 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1033862936 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 407293177 ps |
CPU time | 5.34 seconds |
Started | Jul 01 04:58:08 PM PDT 24 |
Finished | Jul 01 04:58:17 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-f8e73f7f-341f-4de2-9319-ecf384c86b95 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033862936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.1033862936 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.2869535329 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 1145781833 ps |
CPU time | 11.55 seconds |
Started | Jul 01 04:58:13 PM PDT 24 |
Finished | Jul 01 04:58:27 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-047e82dd-2967-49ed-b503-53421e36fbc0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869535329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.2869535329 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.1223703698 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 628459691 ps |
CPU time | 137.52 seconds |
Started | Jul 01 04:58:08 PM PDT 24 |
Finished | Jul 01 05:00:30 PM PDT 24 |
Peak memory | 359096 kb |
Host | smart-a70e52f7-9d5c-487b-88cd-c57da8266c81 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223703698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.1223703698 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.69270984 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 1871910818 ps |
CPU time | 7.41 seconds |
Started | Jul 01 04:58:11 PM PDT 24 |
Finished | Jul 01 04:58:22 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-e6b5175b-e823-40cd-98d7-39d3893d81ba |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69270984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sra m_ctrl_partial_access.69270984 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3790924065 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 37182770631 ps |
CPU time | 341.24 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 05:03:55 PM PDT 24 |
Peak memory | 203004 kb |
Host | smart-d78f2583-f425-4a84-9aa9-a7bc92c57859 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790924065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.3790924065 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.1564412257 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 79729931 ps |
CPU time | 0.78 seconds |
Started | Jul 01 04:58:08 PM PDT 24 |
Finished | Jul 01 04:58:12 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-c2685d5c-5b81-4478-b887-2340fe337855 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564412257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1564412257 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.1603558124 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 7522155909 ps |
CPU time | 424.69 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 05:05:19 PM PDT 24 |
Peak memory | 358240 kb |
Host | smart-4d76964d-d841-402a-ba2e-df1ab693c9ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603558124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1603558124 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.2210199998 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 143221852 ps |
CPU time | 1.9 seconds |
Started | Jul 01 04:58:13 PM PDT 24 |
Finished | Jul 01 04:58:17 PM PDT 24 |
Peak memory | 224640 kb |
Host | smart-ba24c1cb-5035-45bd-97c7-ece096096af9 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210199998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2210199998 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.2742764648 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 53613366 ps |
CPU time | 4.93 seconds |
Started | Jul 01 04:58:08 PM PDT 24 |
Finished | Jul 01 04:58:16 PM PDT 24 |
Peak memory | 222592 kb |
Host | smart-a5b151be-935a-4cc5-a9e4-389b4c432286 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742764648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2742764648 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.322432615 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 76647078792 ps |
CPU time | 4970.48 seconds |
Started | Jul 01 04:58:08 PM PDT 24 |
Finished | Jul 01 06:21:03 PM PDT 24 |
Peak memory | 383124 kb |
Host | smart-d0d5f40e-fa1f-466d-a765-a9ac4f23e40e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322432615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_stress_all.322432615 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.840600436 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 24693559853 ps |
CPU time | 78.32 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 04:59:32 PM PDT 24 |
Peak memory | 285740 kb |
Host | smart-f0112f45-65da-4956-8292-0af6ba5c7b22 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=840600436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.840600436 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1085127584 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 3181800353 ps |
CPU time | 312.41 seconds |
Started | Jul 01 04:58:09 PM PDT 24 |
Finished | Jul 01 05:03:25 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-004190dd-5ff4-4b11-8574-a5969e5d591a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085127584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.1085127584 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.858236630 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 149342037 ps |
CPU time | 128.71 seconds |
Started | Jul 01 04:58:13 PM PDT 24 |
Finished | Jul 01 05:00:24 PM PDT 24 |
Peak memory | 368420 kb |
Host | smart-e8402384-4a21-41f0-99f2-a803bc5f9ff6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858236630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.858236630 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.734457771 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 1163226546 ps |
CPU time | 296 seconds |
Started | Jul 01 04:58:55 PM PDT 24 |
Finished | Jul 01 05:03:56 PM PDT 24 |
Peak memory | 348020 kb |
Host | smart-ed9e5dda-899f-4921-b49c-869bacf472c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734457771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 20.sram_ctrl_access_during_key_req.734457771 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.3003395740 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 18878653 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:58:47 PM PDT 24 |
Finished | Jul 01 04:58:52 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-4b3fa483-552d-41b8-9943-a6a1057d0c01 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003395740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.3003395740 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.2430607858 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 8247207987 ps |
CPU time | 20.91 seconds |
Started | Jul 01 04:58:53 PM PDT 24 |
Finished | Jul 01 04:59:19 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-b7d34002-4fdf-4c44-96b7-39b87b6d739c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430607858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .2430607858 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.1930638074 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 2622761059 ps |
CPU time | 517.52 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 05:07:28 PM PDT 24 |
Peak memory | 370524 kb |
Host | smart-07c65d6c-d74b-4b25-b7c2-faf5d6c7e95e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930638074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.1930638074 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.3157078436 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 514215740 ps |
CPU time | 5.64 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:59:02 PM PDT 24 |
Peak memory | 214732 kb |
Host | smart-a2d5a8de-3ce6-4e7f-af9b-057bc9a0208f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157078436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.3157078436 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.2532248053 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 213769294 ps |
CPU time | 7.03 seconds |
Started | Jul 01 04:58:50 PM PDT 24 |
Finished | Jul 01 04:59:01 PM PDT 24 |
Peak memory | 235720 kb |
Host | smart-4ae681df-3a30-4445-a298-8933a86275f7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532248053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.2532248053 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3798433614 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 68519848 ps |
CPU time | 4.44 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 04:59:09 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-29844d42-8360-404e-90cc-3ab0c498f633 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798433614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.3798433614 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.2365946323 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 906857992 ps |
CPU time | 10.93 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:59:08 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-2d5a55f7-46b7-4276-938e-08da174d134f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365946323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.2365946323 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.3515727953 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 15770216858 ps |
CPU time | 717.25 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 05:10:50 PM PDT 24 |
Peak memory | 374776 kb |
Host | smart-0333cbf4-2252-446f-9d59-0df1b757d557 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515727953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.3515727953 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.2998148291 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 233664818 ps |
CPU time | 4.34 seconds |
Started | Jul 01 04:58:54 PM PDT 24 |
Finished | Jul 01 04:59:03 PM PDT 24 |
Peak memory | 219040 kb |
Host | smart-636f4fbb-9464-4d91-abc0-96304727ad74 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998148291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.2998148291 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2177943327 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 54524033812 ps |
CPU time | 328.03 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 05:04:31 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-86276fa6-8b2c-4440-9461-e13638128a33 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177943327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.2177943327 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.1247546738 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 28821184 ps |
CPU time | 0.76 seconds |
Started | Jul 01 04:58:49 PM PDT 24 |
Finished | Jul 01 04:58:54 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-d666d583-c964-48f9-8203-51e82652254c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247546738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1247546738 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.223383287 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 26379943984 ps |
CPU time | 464.47 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 05:06:34 PM PDT 24 |
Peak memory | 374560 kb |
Host | smart-8fa07eeb-e31b-41d1-b76c-2e07b6d095be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223383287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.223383287 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.3705777492 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 879824340 ps |
CPU time | 15.44 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 04:59:19 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-650d0270-241c-4fca-84ec-8a640bdbfdd4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705777492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3705777492 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.958870062 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 124062321485 ps |
CPU time | 4068.41 seconds |
Started | Jul 01 04:58:50 PM PDT 24 |
Finished | Jul 01 06:06:43 PM PDT 24 |
Peak memory | 375740 kb |
Host | smart-2a49187c-484b-43c2-a1c7-df27901ca855 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958870062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_stress_all.958870062 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3754505424 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 9199009497 ps |
CPU time | 214.57 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 05:02:39 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-6f4399fc-b0da-4e1c-b88d-f48ad444ec5c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754505424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.3754505424 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.870985938 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 138418955 ps |
CPU time | 11.62 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:59:09 PM PDT 24 |
Peak memory | 251940 kb |
Host | smart-dbad8a2a-209c-4310-bf29-54a7e4f3edde |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870985938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.870985938 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3347188579 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 786509312 ps |
CPU time | 141.92 seconds |
Started | Jul 01 04:58:53 PM PDT 24 |
Finished | Jul 01 05:01:20 PM PDT 24 |
Peak memory | 373180 kb |
Host | smart-60cd89d9-78c0-45d3-8296-e5b2344a9ca1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347188579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.3347188579 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.530139670 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 70970466 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:58:58 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-6ebfd3cb-a6a5-445f-a57b-9ef3f0db2742 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530139670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.530139670 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.940798817 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 648884602 ps |
CPU time | 42.15 seconds |
Started | Jul 01 04:58:48 PM PDT 24 |
Finished | Jul 01 04:59:35 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-53f6c19b-9bce-4b97-bde1-ef79c7c44e3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940798817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection. 940798817 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.1495409411 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 582523587 ps |
CPU time | 136.36 seconds |
Started | Jul 01 04:58:53 PM PDT 24 |
Finished | Jul 01 05:01:15 PM PDT 24 |
Peak memory | 353912 kb |
Host | smart-1a68ab2d-1de8-4adf-af3b-730417fb74e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495409411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.1495409411 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.3788824299 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 6560545352 ps |
CPU time | 6.08 seconds |
Started | Jul 01 04:58:49 PM PDT 24 |
Finished | Jul 01 04:59:00 PM PDT 24 |
Peak memory | 202988 kb |
Host | smart-23ec121f-a30c-424f-91f2-1c679cb04825 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788824299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.3788824299 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.597016105 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 98223429 ps |
CPU time | 29.98 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:35 PM PDT 24 |
Peak memory | 293624 kb |
Host | smart-4a85cfda-d0b0-4ffd-89de-ac3a0a94507e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597016105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.sram_ctrl_max_throughput.597016105 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1418762424 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 172822591 ps |
CPU time | 5.65 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 04:59:12 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-d8ec7e55-bc69-42d8-ad00-d91b6eb7bb94 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418762424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.1418762424 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.3200603146 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 451553408 ps |
CPU time | 10.72 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:15 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-ce18a6ac-7b52-46dd-a649-cdeb939012f4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200603146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.3200603146 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.197936057 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 9889973110 ps |
CPU time | 822.41 seconds |
Started | Jul 01 04:58:54 PM PDT 24 |
Finished | Jul 01 05:12:40 PM PDT 24 |
Peak memory | 375800 kb |
Host | smart-8b769966-4601-42b0-8afe-38554d32d654 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197936057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multip le_keys.197936057 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.1276274085 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 529971177 ps |
CPU time | 3.36 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:09 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-6272d771-e6c5-40c8-8c43-4c300253827b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276274085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.1276274085 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1988383524 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 86638368071 ps |
CPU time | 310.85 seconds |
Started | Jul 01 04:58:53 PM PDT 24 |
Finished | Jul 01 05:04:08 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-8bd87da3-a6d3-4767-b5be-fdbb5e2dd2b3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988383524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.1988383524 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.1040178267 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 96759179 ps |
CPU time | 0.74 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 04:59:07 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-8f2a8472-6bf5-40d0-9616-004b430f528c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040178267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1040178267 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.188944661 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 19348026590 ps |
CPU time | 655.01 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 05:09:58 PM PDT 24 |
Peak memory | 337940 kb |
Host | smart-144b5c38-e929-4e76-bec3-b80b4c22e208 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188944661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.188944661 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.1979282469 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 1554316488 ps |
CPU time | 15.85 seconds |
Started | Jul 01 04:59:02 PM PDT 24 |
Finished | Jul 01 04:59:23 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-f5f1ad6e-517f-4c38-b04e-edd586f6db21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979282469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1979282469 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.613244477 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 118464197120 ps |
CPU time | 1899.88 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 05:30:45 PM PDT 24 |
Peak memory | 374652 kb |
Host | smart-03f49f99-a23a-4710-a9c1-6c3dd8aeff63 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613244477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_stress_all.613244477 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1162275236 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 7059005988 ps |
CPU time | 44.9 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:50 PM PDT 24 |
Peak memory | 289952 kb |
Host | smart-7250b01c-afdb-4cef-9a5b-26f03e55102c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1162275236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1162275236 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.4076926397 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 11481127132 ps |
CPU time | 283.61 seconds |
Started | Jul 01 04:58:47 PM PDT 24 |
Finished | Jul 01 05:03:35 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-1708c818-b788-4d6e-bffa-70c1a27bf610 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076926397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.4076926397 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3613051104 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 136624989 ps |
CPU time | 109.79 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 05:00:54 PM PDT 24 |
Peak memory | 334736 kb |
Host | smart-9b734af2-392f-45a1-a1af-c1c762df3124 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613051104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3613051104 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.664381597 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 1531399372 ps |
CPU time | 102.31 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 05:00:46 PM PDT 24 |
Peak memory | 359148 kb |
Host | smart-4729d256-a0b7-427f-9d77-c78a438a9a4c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664381597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 22.sram_ctrl_access_during_key_req.664381597 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.3105962173 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 35439438 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 04:59:05 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-5ca57c0d-ba8b-418a-892c-7c5442f6ad44 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105962173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.3105962173 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.1630252610 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1272566513 ps |
CPU time | 20.91 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:26 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-dce47525-7c82-4609-9e25-ef1a80b70a6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630252610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .1630252610 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.3731108816 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 1479737104 ps |
CPU time | 56.11 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 05:00:02 PM PDT 24 |
Peak memory | 295364 kb |
Host | smart-7677ead2-cf2b-450f-855d-2ca07f8e5da2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731108816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.3731108816 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.141643541 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 847168689 ps |
CPU time | 5.27 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:11 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-54183c9d-2f99-461c-8715-0e67e01e7f44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141643541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc alation.141643541 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.720151521 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 149922679 ps |
CPU time | 95.45 seconds |
Started | Jul 01 04:59:02 PM PDT 24 |
Finished | Jul 01 05:00:43 PM PDT 24 |
Peak memory | 343864 kb |
Host | smart-22164459-b6c8-4367-a056-5d781e3ffdf3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720151521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.sram_ctrl_max_throughput.720151521 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2333119113 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 454700390 ps |
CPU time | 3.28 seconds |
Started | Jul 01 04:58:53 PM PDT 24 |
Finished | Jul 01 04:59:01 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-4c24e1a7-9bc0-48a9-b141-5dfed51d1e51 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333119113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.2333119113 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.593475676 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 178332470 ps |
CPU time | 10.94 seconds |
Started | Jul 01 04:59:02 PM PDT 24 |
Finished | Jul 01 04:59:18 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-9a0e801b-c308-4be2-a9f0-9267b660e730 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593475676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl _mem_walk.593475676 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.3272776671 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 2650461763 ps |
CPU time | 111.17 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 05:00:57 PM PDT 24 |
Peak memory | 359332 kb |
Host | smart-475bb143-c902-4e05-a830-e1eb81763d1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272776671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.3272776671 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.2879973407 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 10070743494 ps |
CPU time | 14.86 seconds |
Started | Jul 01 04:58:52 PM PDT 24 |
Finished | Jul 01 04:59:12 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-0e847952-ed14-4b3b-817e-e96101a86311 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879973407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.2879973407 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3859435586 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 31765535808 ps |
CPU time | 365.52 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 05:05:08 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-c9989bc7-8fc4-482e-99bb-baa271f9d1b7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859435586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.3859435586 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.1724952616 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 32967883 ps |
CPU time | 0.77 seconds |
Started | Jul 01 04:58:57 PM PDT 24 |
Finished | Jul 01 04:59:02 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-a83018f4-65e8-4e26-9df4-39b875fd9ab5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724952616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1724952616 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.2863689830 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 16225966580 ps |
CPU time | 1703.41 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 05:27:28 PM PDT 24 |
Peak memory | 375780 kb |
Host | smart-a2c7dbac-10d3-4ad5-984e-1ccb047c2478 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863689830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2863689830 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.1290984876 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 423617478 ps |
CPU time | 3.94 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:10 PM PDT 24 |
Peak memory | 214852 kb |
Host | smart-8d758d04-0628-4e9f-b71b-e6d1cba168fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290984876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1290984876 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.490303868 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 32261416762 ps |
CPU time | 1474.2 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 05:23:37 PM PDT 24 |
Peak memory | 380632 kb |
Host | smart-de7e0047-5be8-4879-a6ee-4285e10f7303 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490303868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_stress_all.490303868 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.47670790 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 32054076610 ps |
CPU time | 263.7 seconds |
Started | Jul 01 04:59:02 PM PDT 24 |
Finished | Jul 01 05:03:31 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-198727ab-2d08-426f-b68f-a4d53f7a8395 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47670790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_stress_pipeline.47670790 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2008842038 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 131302034 ps |
CPU time | 41.28 seconds |
Started | Jul 01 04:58:54 PM PDT 24 |
Finished | Jul 01 04:59:40 PM PDT 24 |
Peak memory | 316900 kb |
Host | smart-6c9a20ce-1c9c-4375-9d7a-77aae489eb64 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008842038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.2008842038 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1435720043 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 6535618539 ps |
CPU time | 733.46 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 05:11:20 PM PDT 24 |
Peak memory | 370668 kb |
Host | smart-e7a00c09-0a1e-4079-9f01-c1378149ed7e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435720043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.1435720043 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.915903009 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 34542390 ps |
CPU time | 0.63 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 04:59:05 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-ad96f743-cc4c-4102-85c1-92715d83cb59 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915903009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.915903009 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.1910299773 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 20414451908 ps |
CPU time | 65.56 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 05:00:08 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-ce9ba4bf-89c4-4235-bfa0-a59141f9ad1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910299773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .1910299773 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.3338076592 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 2453935688 ps |
CPU time | 704.51 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 05:10:51 PM PDT 24 |
Peak memory | 373472 kb |
Host | smart-c1024af0-b58d-4cd8-84f2-5a07b44f7f62 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338076592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.3338076592 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.3314162427 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 63144053 ps |
CPU time | 1.15 seconds |
Started | Jul 01 04:59:02 PM PDT 24 |
Finished | Jul 01 04:59:08 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-63a2ee19-c2f4-499d-a2c1-4d0264c28528 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314162427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.3314162427 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.2686046621 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 89819893 ps |
CPU time | 29.54 seconds |
Started | Jul 01 04:59:05 PM PDT 24 |
Finished | Jul 01 04:59:38 PM PDT 24 |
Peak memory | 289588 kb |
Host | smart-e4e23a51-2e11-4811-b3e0-fa9178b2e71d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686046621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.2686046621 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1967334648 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 181446898 ps |
CPU time | 3.04 seconds |
Started | Jul 01 04:59:03 PM PDT 24 |
Finished | Jul 01 04:59:11 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-593ae9b0-2c44-4ff4-9161-de2a51effe25 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967334648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.1967334648 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.1287043899 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 484417605 ps |
CPU time | 5.64 seconds |
Started | Jul 01 04:59:11 PM PDT 24 |
Finished | Jul 01 04:59:18 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-070cb0f1-ae01-48d2-9c71-bac6bacef65c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287043899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.1287043899 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.3706367044 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 3380073881 ps |
CPU time | 780.51 seconds |
Started | Jul 01 04:58:53 PM PDT 24 |
Finished | Jul 01 05:11:59 PM PDT 24 |
Peak memory | 374728 kb |
Host | smart-dea2d27c-c186-469e-a493-6a53507d386c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706367044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.3706367044 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.2456705407 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 846189735 ps |
CPU time | 14.23 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:20 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-28c6294c-e0c7-4ba2-80ef-2a7c958001e8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456705407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.2456705407 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3894891884 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 4495871607 ps |
CPU time | 326.25 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 05:04:33 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-c6f0e1de-55c9-4efe-816b-6a41402cb467 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894891884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.3894891884 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.2911755994 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 29685226 ps |
CPU time | 0.81 seconds |
Started | Jul 01 04:59:02 PM PDT 24 |
Finished | Jul 01 04:59:08 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-a32b1aeb-79b2-458e-b74e-0e8dff747bea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911755994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2911755994 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.3748630053 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 3552973910 ps |
CPU time | 404.31 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 05:05:50 PM PDT 24 |
Peak memory | 367744 kb |
Host | smart-27e18bb6-8efc-49ca-bd9e-365bd3aec5d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748630053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3748630053 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.3060032374 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 2068980961 ps |
CPU time | 67.97 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 05:00:15 PM PDT 24 |
Peak memory | 317724 kb |
Host | smart-7a283e82-3ef7-4fa3-ace7-65f45123509c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060032374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3060032374 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.2903994061 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 15402281815 ps |
CPU time | 1036.27 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 05:16:21 PM PDT 24 |
Peak memory | 376296 kb |
Host | smart-c450ebe4-c708-4f4e-9479-d892b1c78e9c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903994061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.2903994061 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3206043483 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 2604736532 ps |
CPU time | 65.1 seconds |
Started | Jul 01 04:59:07 PM PDT 24 |
Finished | Jul 01 05:00:15 PM PDT 24 |
Peak memory | 297044 kb |
Host | smart-4f9c6a50-1e45-4151-b8f8-bbd6d2b73cc6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3206043483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3206043483 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.681243511 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 8586640040 ps |
CPU time | 411.58 seconds |
Started | Jul 01 04:58:57 PM PDT 24 |
Finished | Jul 01 05:05:52 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-5784245f-adde-47a9-927a-19c69deb924d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681243511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .sram_ctrl_stress_pipeline.681243511 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.646776304 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 117879219 ps |
CPU time | 42.64 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:49 PM PDT 24 |
Peak memory | 300892 kb |
Host | smart-64dc35e3-4536-4d15-a091-52b307718da6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646776304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.646776304 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2599570885 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 3011010427 ps |
CPU time | 265.24 seconds |
Started | Jul 01 04:58:59 PM PDT 24 |
Finished | Jul 01 05:03:29 PM PDT 24 |
Peak memory | 366036 kb |
Host | smart-a42e46db-e59f-4bc3-ae97-cfb8d4496755 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599570885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.2599570885 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.2229980685 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 28080176 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:59:08 PM PDT 24 |
Finished | Jul 01 04:59:12 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-7a28ca48-bd03-4b72-b647-9f493e498ec3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229980685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2229980685 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.1747709820 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 2226243640 ps |
CPU time | 48.85 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 04:59:55 PM PDT 24 |
Peak memory | 203016 kb |
Host | smart-facb2a3f-596a-4cbf-b6e2-a6ce8e27b775 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747709820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .1747709820 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.3644673559 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 5438976527 ps |
CPU time | 1224.06 seconds |
Started | Jul 01 04:59:06 PM PDT 24 |
Finished | Jul 01 05:19:34 PM PDT 24 |
Peak memory | 367640 kb |
Host | smart-9c176b80-21ef-4b49-8909-6db8f6750f24 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644673559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.3644673559 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.1874394298 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 250987089 ps |
CPU time | 3.02 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 04:59:10 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-9e0faaf0-2a0f-4f47-a86f-98abd1aa1b10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874394298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.1874394298 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.926802243 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 56980968 ps |
CPU time | 7.73 seconds |
Started | Jul 01 04:59:13 PM PDT 24 |
Finished | Jul 01 04:59:23 PM PDT 24 |
Peak memory | 237444 kb |
Host | smart-cd81f1ec-f5d0-41c3-b87e-b6324cc3c73d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926802243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.sram_ctrl_max_throughput.926802243 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.578323352 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 71500145 ps |
CPU time | 3.24 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 04:59:09 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-940a3334-38cb-480b-bdec-adf7c487a924 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578323352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .sram_ctrl_mem_partial_access.578323352 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.2053189564 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 598384134 ps |
CPU time | 8.85 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 04:59:12 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-3b1370e6-e27c-4868-b2a3-35cbb336574d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053189564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2053189564 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.3574417981 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 1223611060 ps |
CPU time | 157.34 seconds |
Started | Jul 01 04:59:13 PM PDT 24 |
Finished | Jul 01 05:01:52 PM PDT 24 |
Peak memory | 364632 kb |
Host | smart-cd67d60f-39b8-44bd-86a1-524968f6a514 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574417981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.3574417981 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.456387431 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 196559493 ps |
CPU time | 4.02 seconds |
Started | Jul 01 04:59:07 PM PDT 24 |
Finished | Jul 01 04:59:14 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-b4e5b1bc-9489-4524-be80-0185de05a337 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456387431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s ram_ctrl_partial_access.456387431 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3165301475 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 106092750515 ps |
CPU time | 363.79 seconds |
Started | Jul 01 04:59:03 PM PDT 24 |
Finished | Jul 01 05:05:11 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-b87957bb-bbee-4502-8c96-5e9cb92b218a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165301475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.3165301475 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.4209345521 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 28006093 ps |
CPU time | 0.74 seconds |
Started | Jul 01 04:59:03 PM PDT 24 |
Finished | Jul 01 04:59:08 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-99cadc51-db47-4efd-a706-b8383858e4d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209345521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.4209345521 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.3341167788 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 9572661244 ps |
CPU time | 627.26 seconds |
Started | Jul 01 04:59:03 PM PDT 24 |
Finished | Jul 01 05:09:35 PM PDT 24 |
Peak memory | 368692 kb |
Host | smart-3c3114f3-bbbf-4f5a-8a51-e091815222b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341167788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3341167788 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.3765343 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 2195797646 ps |
CPU time | 96.01 seconds |
Started | Jul 01 04:59:01 PM PDT 24 |
Finished | Jul 01 05:00:42 PM PDT 24 |
Peak memory | 332340 kb |
Host | smart-f2cee380-f18d-49d2-a739-aff5d1ef5e80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3765343 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.3548246691 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 18061921084 ps |
CPU time | 1484.82 seconds |
Started | Jul 01 04:59:07 PM PDT 24 |
Finished | Jul 01 05:23:55 PM PDT 24 |
Peak memory | 370344 kb |
Host | smart-21929688-260b-4964-8ec9-917479743f58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548246691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.3548246691 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2681029579 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 2115941514 ps |
CPU time | 833.56 seconds |
Started | Jul 01 04:58:58 PM PDT 24 |
Finished | Jul 01 05:12:57 PM PDT 24 |
Peak memory | 383000 kb |
Host | smart-34e80af7-f4a9-45a7-978a-cd9213c8ec92 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2681029579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2681029579 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3473228387 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 16248008445 ps |
CPU time | 394.89 seconds |
Started | Jul 01 04:59:00 PM PDT 24 |
Finished | Jul 01 05:05:40 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-105fdff3-7f59-4f1e-901b-dac7d85422a0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473228387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.3473228387 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2775789784 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 165216172 ps |
CPU time | 66.32 seconds |
Started | Jul 01 04:59:12 PM PDT 24 |
Finished | Jul 01 05:00:20 PM PDT 24 |
Peak memory | 332940 kb |
Host | smart-4f686a5e-2412-46ed-8236-bcfff0892fef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775789784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.2775789784 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.752498590 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 2380312970 ps |
CPU time | 841.19 seconds |
Started | Jul 01 04:59:06 PM PDT 24 |
Finished | Jul 01 05:13:11 PM PDT 24 |
Peak memory | 373468 kb |
Host | smart-0e760327-2a5e-4dd5-bff3-ec392c3bfc84 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752498590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 25.sram_ctrl_access_during_key_req.752498590 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.720948923 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 38818384 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:59:12 PM PDT 24 |
Finished | Jul 01 04:59:15 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-24220202-f683-406c-86f2-71290ac79865 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720948923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.720948923 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.2083679161 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 36866803698 ps |
CPU time | 63.25 seconds |
Started | Jul 01 04:59:15 PM PDT 24 |
Finished | Jul 01 05:00:20 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-e72cab91-e5c7-4cf4-b002-d0afe1d83195 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083679161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .2083679161 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.1623029178 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 22632207570 ps |
CPU time | 751.74 seconds |
Started | Jul 01 04:59:11 PM PDT 24 |
Finished | Jul 01 05:11:44 PM PDT 24 |
Peak memory | 374344 kb |
Host | smart-59499216-5974-41fe-9e2d-a97c6bfd298f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623029178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.1623029178 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.3550748957 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 2104842370 ps |
CPU time | 6.43 seconds |
Started | Jul 01 04:59:07 PM PDT 24 |
Finished | Jul 01 04:59:16 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-2782f58c-299e-4edc-88c8-3a9fd6dedda8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550748957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.3550748957 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.308000766 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 118211730 ps |
CPU time | 54.81 seconds |
Started | Jul 01 04:59:08 PM PDT 24 |
Finished | Jul 01 05:00:05 PM PDT 24 |
Peak memory | 322400 kb |
Host | smart-f78798a3-09d2-4955-82b8-eddc447705c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308000766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.sram_ctrl_max_throughput.308000766 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.6063474 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 305924135 ps |
CPU time | 5.38 seconds |
Started | Jul 01 04:59:06 PM PDT 24 |
Finished | Jul 01 04:59:15 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-4361845b-635a-4420-9089-567c64225499 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6063474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s ram_ctrl_mem_partial_access.6063474 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.948514969 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 2579494623 ps |
CPU time | 8.78 seconds |
Started | Jul 01 04:59:08 PM PDT 24 |
Finished | Jul 01 04:59:20 PM PDT 24 |
Peak memory | 211260 kb |
Host | smart-ba512c20-31df-407e-a3db-cbee447e4aee |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948514969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl _mem_walk.948514969 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.2514096536 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 85214134441 ps |
CPU time | 1419.66 seconds |
Started | Jul 01 04:59:06 PM PDT 24 |
Finished | Jul 01 05:22:49 PM PDT 24 |
Peak memory | 374552 kb |
Host | smart-26dc0b99-1314-41d1-a5d9-2174cef7d01c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514096536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.2514096536 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.1341716916 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 73341374 ps |
CPU time | 1.37 seconds |
Started | Jul 01 04:59:10 PM PDT 24 |
Finished | Jul 01 04:59:14 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-e3207850-6fc5-43c6-ad00-a9f6b9373510 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341716916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.1341716916 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.470243142 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 42952952153 ps |
CPU time | 336.78 seconds |
Started | Jul 01 04:59:08 PM PDT 24 |
Finished | Jul 01 05:04:48 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-1882d62f-2a99-4f92-8120-38f0de9886d1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470243142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.sram_ctrl_partial_access_b2b.470243142 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.2121388515 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 65337403 ps |
CPU time | 0.77 seconds |
Started | Jul 01 04:59:08 PM PDT 24 |
Finished | Jul 01 04:59:12 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-ca5ef532-be54-41e2-827b-22701911cec0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121388515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2121388515 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.54962740 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 32751853377 ps |
CPU time | 1657.61 seconds |
Started | Jul 01 04:59:06 PM PDT 24 |
Finished | Jul 01 05:26:47 PM PDT 24 |
Peak memory | 375652 kb |
Host | smart-417d0b93-824a-44c2-b44d-c3672c46b739 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54962740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.54962740 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.4270345984 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 446807507 ps |
CPU time | 49.25 seconds |
Started | Jul 01 04:59:06 PM PDT 24 |
Finished | Jul 01 04:59:59 PM PDT 24 |
Peak memory | 309272 kb |
Host | smart-642996bb-fd8a-44d4-b23e-02871ee6e676 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270345984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.4270345984 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.3749471865 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 46492956030 ps |
CPU time | 2673.06 seconds |
Started | Jul 01 04:59:09 PM PDT 24 |
Finished | Jul 01 05:43:45 PM PDT 24 |
Peak memory | 378324 kb |
Host | smart-365fea46-0daf-4eeb-887e-79aed7e68cd6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749471865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.3749471865 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2419155352 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 6121789304 ps |
CPU time | 301.37 seconds |
Started | Jul 01 04:59:06 PM PDT 24 |
Finished | Jul 01 05:04:11 PM PDT 24 |
Peak memory | 350148 kb |
Host | smart-dc57925c-5893-4dcf-9bdf-b36d48c17b27 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2419155352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2419155352 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1673352960 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 2002945261 ps |
CPU time | 194.28 seconds |
Started | Jul 01 04:59:14 PM PDT 24 |
Finished | Jul 01 05:02:30 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-75693d90-d5a8-4aeb-b897-33c1fcf1c64f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673352960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.1673352960 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2444891920 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 764055610 ps |
CPU time | 58.78 seconds |
Started | Jul 01 04:59:07 PM PDT 24 |
Finished | Jul 01 05:00:09 PM PDT 24 |
Peak memory | 307980 kb |
Host | smart-429fd51f-a3e1-479e-92a2-d6b533e4e190 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444891920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.2444891920 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3751350556 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 13427539261 ps |
CPU time | 959.57 seconds |
Started | Jul 01 04:59:12 PM PDT 24 |
Finished | Jul 01 05:15:13 PM PDT 24 |
Peak memory | 375776 kb |
Host | smart-c5677070-bd7b-4627-919a-48b8b76bda64 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751350556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.3751350556 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.2700755118 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 25823319 ps |
CPU time | 0.7 seconds |
Started | Jul 01 04:59:13 PM PDT 24 |
Finished | Jul 01 04:59:15 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-f9624590-d95f-43a7-8fb5-3dc6a4d52f66 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700755118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2700755118 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.942286760 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 796793600 ps |
CPU time | 25.17 seconds |
Started | Jul 01 04:59:14 PM PDT 24 |
Finished | Jul 01 04:59:41 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-858c55ac-76e7-4b0b-96e2-2451056bb509 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942286760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 942286760 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.3247798276 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 48868184678 ps |
CPU time | 620.02 seconds |
Started | Jul 01 04:59:21 PM PDT 24 |
Finished | Jul 01 05:09:43 PM PDT 24 |
Peak memory | 370572 kb |
Host | smart-2bccd1df-2488-42ea-8426-4e5853aaf798 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247798276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.3247798276 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.141148645 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 444030371 ps |
CPU time | 6.14 seconds |
Started | Jul 01 04:59:13 PM PDT 24 |
Finished | Jul 01 04:59:21 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-7d09790a-7242-4522-8d26-c449624d19d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141148645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esc alation.141148645 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.3621746265 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 495015524 ps |
CPU time | 92.94 seconds |
Started | Jul 01 04:59:20 PM PDT 24 |
Finished | Jul 01 05:00:55 PM PDT 24 |
Peak memory | 356484 kb |
Host | smart-bb665426-80eb-43fe-a42f-a260dfd9f3c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621746265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.3621746265 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.791249315 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 100990146 ps |
CPU time | 3.2 seconds |
Started | Jul 01 04:59:12 PM PDT 24 |
Finished | Jul 01 04:59:17 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-fe644db7-0250-483d-8644-8635a64cee66 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791249315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_mem_partial_access.791249315 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.2211741202 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 924345482 ps |
CPU time | 5.4 seconds |
Started | Jul 01 04:59:14 PM PDT 24 |
Finished | Jul 01 04:59:21 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-94164a4d-ed79-4bc3-a247-943c93efc853 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211741202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.2211741202 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.855636879 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 57107954069 ps |
CPU time | 2235.78 seconds |
Started | Jul 01 04:59:12 PM PDT 24 |
Finished | Jul 01 05:36:29 PM PDT 24 |
Peak memory | 376120 kb |
Host | smart-5cbc8337-2970-4ef8-b44d-f184fc42ff11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855636879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip le_keys.855636879 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.4024781620 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 274932734 ps |
CPU time | 5.36 seconds |
Started | Jul 01 04:59:15 PM PDT 24 |
Finished | Jul 01 04:59:22 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-12fc0c35-898a-4090-88a3-72a800236cdd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024781620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.4024781620 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2191418303 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 21644485170 ps |
CPU time | 244.85 seconds |
Started | Jul 01 04:59:14 PM PDT 24 |
Finished | Jul 01 05:03:21 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-1751e87b-b2f8-4dcf-8dd2-7eddb6c1ffb4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191418303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.2191418303 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.3660431842 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 44397887 ps |
CPU time | 0.74 seconds |
Started | Jul 01 04:59:16 PM PDT 24 |
Finished | Jul 01 04:59:18 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-481292bb-21f0-4cf2-80e1-ac4cd936163c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660431842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3660431842 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.3422406933 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 1205470965 ps |
CPU time | 171.49 seconds |
Started | Jul 01 04:59:15 PM PDT 24 |
Finished | Jul 01 05:02:08 PM PDT 24 |
Peak memory | 340252 kb |
Host | smart-ef5146e6-0ee9-46b5-b54c-66ef71047bfe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422406933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3422406933 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.3411011659 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 338457681 ps |
CPU time | 2.56 seconds |
Started | Jul 01 04:59:13 PM PDT 24 |
Finished | Jul 01 04:59:18 PM PDT 24 |
Peak memory | 206212 kb |
Host | smart-d2b93454-30b1-407d-a7e8-70ccbfc3f123 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411011659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3411011659 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.1752534953 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 94007271089 ps |
CPU time | 1055.77 seconds |
Started | Jul 01 04:59:18 PM PDT 24 |
Finished | Jul 01 05:16:55 PM PDT 24 |
Peak memory | 367728 kb |
Host | smart-bca573d0-a38c-4cc8-ae2e-3d7aef81b851 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752534953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.1752534953 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2457269593 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 4731496135 ps |
CPU time | 193.26 seconds |
Started | Jul 01 04:59:13 PM PDT 24 |
Finished | Jul 01 05:02:28 PM PDT 24 |
Peak memory | 333916 kb |
Host | smart-9774a0c5-808d-472d-bee1-4c1d8cc98b15 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2457269593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.2457269593 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.141652503 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 7310042556 ps |
CPU time | 337.18 seconds |
Started | Jul 01 04:59:12 PM PDT 24 |
Finished | Jul 01 05:04:51 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-1efc635c-362f-4444-ac3f-8f9961800e86 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141652503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_stress_pipeline.141652503 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.610899328 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 379053931 ps |
CPU time | 31.28 seconds |
Started | Jul 01 04:59:13 PM PDT 24 |
Finished | Jul 01 04:59:46 PM PDT 24 |
Peak memory | 285472 kb |
Host | smart-fc24010a-b2f4-4955-b04b-579ce8ed4428 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610899328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.610899328 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.390684671 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 30387047597 ps |
CPU time | 967.46 seconds |
Started | Jul 01 04:59:20 PM PDT 24 |
Finished | Jul 01 05:15:29 PM PDT 24 |
Peak memory | 374268 kb |
Host | smart-21c7438a-d413-4fd3-a09f-89f8d33a5452 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390684671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 27.sram_ctrl_access_during_key_req.390684671 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.210284698 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 31523923 ps |
CPU time | 0.69 seconds |
Started | Jul 01 04:59:24 PM PDT 24 |
Finished | Jul 01 04:59:26 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-e065498d-62d5-432c-94ac-10656471e74f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210284698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.210284698 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.2196636724 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 3299327132 ps |
CPU time | 69.37 seconds |
Started | Jul 01 04:59:19 PM PDT 24 |
Finished | Jul 01 05:00:30 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-a36bd3ca-2371-46b3-88ee-d82b8ccccaba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196636724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .2196636724 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.1312975678 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 11171388205 ps |
CPU time | 549.82 seconds |
Started | Jul 01 04:59:24 PM PDT 24 |
Finished | Jul 01 05:08:35 PM PDT 24 |
Peak memory | 374720 kb |
Host | smart-70852ac7-14d7-463f-b013-6fb7f3bd7b61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312975678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.1312975678 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.3595062795 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 1312474563 ps |
CPU time | 10.88 seconds |
Started | Jul 01 04:59:22 PM PDT 24 |
Finished | Jul 01 04:59:34 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-82441003-b704-4011-b23b-ca56f8272449 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595062795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.3595062795 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.272592619 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 74034319 ps |
CPU time | 16.33 seconds |
Started | Jul 01 04:59:19 PM PDT 24 |
Finished | Jul 01 04:59:36 PM PDT 24 |
Peak memory | 261080 kb |
Host | smart-c16c826c-61e3-4865-a828-0602c9bd3272 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272592619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.sram_ctrl_max_throughput.272592619 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3900691003 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 678700219 ps |
CPU time | 5.65 seconds |
Started | Jul 01 04:59:20 PM PDT 24 |
Finished | Jul 01 04:59:27 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-368303a3-57cf-4e40-ae4c-9ce21b1bd0b7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900691003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.3900691003 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.3962937816 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 1017077327 ps |
CPU time | 6.28 seconds |
Started | Jul 01 04:59:24 PM PDT 24 |
Finished | Jul 01 04:59:32 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-45ac44d7-48c7-488e-973f-e4f4e56c862e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962937816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.3962937816 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.1615856141 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 19224687891 ps |
CPU time | 655.3 seconds |
Started | Jul 01 04:59:28 PM PDT 24 |
Finished | Jul 01 05:10:26 PM PDT 24 |
Peak memory | 372428 kb |
Host | smart-d9c7f498-87ae-4e08-9582-b6a767594037 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615856141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.1615856141 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.4030684771 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 209956840 ps |
CPU time | 10.17 seconds |
Started | Jul 01 04:59:26 PM PDT 24 |
Finished | Jul 01 04:59:38 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-cc678e68-7c1e-4e32-a8c1-22a2deb37528 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030684771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.4030684771 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1698811135 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 12597065308 ps |
CPU time | 293.04 seconds |
Started | Jul 01 04:59:24 PM PDT 24 |
Finished | Jul 01 05:04:18 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-680bf4ff-bc55-434f-8d98-6598dfe3be16 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698811135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.1698811135 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.438338979 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 31619356 ps |
CPU time | 0.78 seconds |
Started | Jul 01 04:59:21 PM PDT 24 |
Finished | Jul 01 04:59:24 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-46f649a4-f0d9-4aed-a7d8-a23a458cde05 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438338979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.438338979 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.3511754887 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 47515972555 ps |
CPU time | 2208.53 seconds |
Started | Jul 01 04:59:19 PM PDT 24 |
Finished | Jul 01 05:36:08 PM PDT 24 |
Peak memory | 372556 kb |
Host | smart-c7bdde08-5000-42ef-a0cb-daef3e248fef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511754887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3511754887 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.295236198 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 866774259 ps |
CPU time | 59.5 seconds |
Started | Jul 01 04:59:20 PM PDT 24 |
Finished | Jul 01 05:00:21 PM PDT 24 |
Peak memory | 306980 kb |
Host | smart-d79824f9-e6d8-4a49-8fc7-9e33fe5bc0d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295236198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.295236198 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.3094800148 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 23288054025 ps |
CPU time | 3237.56 seconds |
Started | Jul 01 04:59:24 PM PDT 24 |
Finished | Jul 01 05:53:24 PM PDT 24 |
Peak memory | 376888 kb |
Host | smart-ddc98204-8d42-491e-8888-82bcf12f1963 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094800148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.3094800148 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.276478250 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 752418152 ps |
CPU time | 57.03 seconds |
Started | Jul 01 04:59:19 PM PDT 24 |
Finished | Jul 01 05:00:17 PM PDT 24 |
Peak memory | 229160 kb |
Host | smart-7cace035-29b4-4e08-99f4-ec6987e6d3eb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=276478250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.276478250 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1334980782 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 3653469519 ps |
CPU time | 350.66 seconds |
Started | Jul 01 04:59:24 PM PDT 24 |
Finished | Jul 01 05:05:16 PM PDT 24 |
Peak memory | 203052 kb |
Host | smart-2a86a9aa-6f05-4fc7-89a7-6b9d39e0cce5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334980782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.1334980782 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2460813590 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 315880361 ps |
CPU time | 28.27 seconds |
Started | Jul 01 04:59:20 PM PDT 24 |
Finished | Jul 01 04:59:49 PM PDT 24 |
Peak memory | 285676 kb |
Host | smart-34821f3d-ae67-44cb-9e47-1978c4bb4745 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460813590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2460813590 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3783688226 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 18383606146 ps |
CPU time | 909.06 seconds |
Started | Jul 01 04:59:20 PM PDT 24 |
Finished | Jul 01 05:14:30 PM PDT 24 |
Peak memory | 367536 kb |
Host | smart-68bb42a6-fd2d-409f-a7ab-6ef63ed41513 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783688226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.3783688226 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.2260310834 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 48832263 ps |
CPU time | 0.64 seconds |
Started | Jul 01 04:59:25 PM PDT 24 |
Finished | Jul 01 04:59:28 PM PDT 24 |
Peak memory | 202584 kb |
Host | smart-d2e7c03c-51da-4fa3-8fef-4ed6d304c2cb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260310834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.2260310834 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.2276386092 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 29406937953 ps |
CPU time | 76.7 seconds |
Started | Jul 01 04:59:19 PM PDT 24 |
Finished | Jul 01 05:00:37 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-7f683f06-b0fb-4f11-9911-cc3d6dbfabd6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276386092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .2276386092 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.2612594468 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 18966065921 ps |
CPU time | 836.17 seconds |
Started | Jul 01 04:59:22 PM PDT 24 |
Finished | Jul 01 05:13:20 PM PDT 24 |
Peak memory | 373760 kb |
Host | smart-45558ef4-9470-4f1a-a543-e67e187597b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612594468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.2612594468 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.2908375159 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 237301046 ps |
CPU time | 2.57 seconds |
Started | Jul 01 04:59:21 PM PDT 24 |
Finished | Jul 01 04:59:25 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-abc026e1-3daf-4631-9a85-9e48475b6cc1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908375159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.2908375159 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.800225973 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 42298100 ps |
CPU time | 1.97 seconds |
Started | Jul 01 04:59:21 PM PDT 24 |
Finished | Jul 01 04:59:25 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-8bc1110c-919b-4642-a4af-b05f1c78ae1f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800225973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.sram_ctrl_max_throughput.800225973 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2574380260 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 305287322 ps |
CPU time | 3.43 seconds |
Started | Jul 01 04:59:20 PM PDT 24 |
Finished | Jul 01 04:59:25 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-fe219063-c761-4cbf-bc73-cfec8970d5ef |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574380260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.2574380260 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.3796794925 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 1379130948 ps |
CPU time | 5.77 seconds |
Started | Jul 01 04:59:24 PM PDT 24 |
Finished | Jul 01 04:59:31 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-e15f07b7-7f91-4f8f-8477-3ad27544b561 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796794925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.3796794925 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.3755794035 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 27371371670 ps |
CPU time | 725.92 seconds |
Started | Jul 01 04:59:18 PM PDT 24 |
Finished | Jul 01 05:11:25 PM PDT 24 |
Peak memory | 368464 kb |
Host | smart-611b849a-8ca9-47e5-af83-6f540fb97456 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755794035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.3755794035 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.4149061791 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 854836931 ps |
CPU time | 11.29 seconds |
Started | Jul 01 04:59:24 PM PDT 24 |
Finished | Jul 01 04:59:36 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-19016106-067e-4cc1-927d-fe0679dac252 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149061791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.4149061791 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.318690175 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 27179522716 ps |
CPU time | 369.83 seconds |
Started | Jul 01 04:59:20 PM PDT 24 |
Finished | Jul 01 05:05:31 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-3504a652-6871-412a-9db4-b289e291e0ef |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318690175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.sram_ctrl_partial_access_b2b.318690175 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.2263782265 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 81089895 ps |
CPU time | 0.74 seconds |
Started | Jul 01 04:59:18 PM PDT 24 |
Finished | Jul 01 04:59:20 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-247b80d3-6c09-4750-b858-65fae0664550 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263782265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2263782265 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.3772126104 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 2774960933 ps |
CPU time | 92.22 seconds |
Started | Jul 01 04:59:28 PM PDT 24 |
Finished | Jul 01 05:01:02 PM PDT 24 |
Peak memory | 271756 kb |
Host | smart-010bf2b8-cef8-4741-acdc-679e3d74949a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772126104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3772126104 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.2286310353 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 286141249 ps |
CPU time | 23.93 seconds |
Started | Jul 01 04:59:20 PM PDT 24 |
Finished | Jul 01 04:59:45 PM PDT 24 |
Peak memory | 282144 kb |
Host | smart-66cdfc17-d8c4-49da-bf9c-6568e7ea43fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286310353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2286310353 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.495051359 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 5243951813 ps |
CPU time | 1641.33 seconds |
Started | Jul 01 04:59:23 PM PDT 24 |
Finished | Jul 01 05:26:46 PM PDT 24 |
Peak memory | 376524 kb |
Host | smart-8f2ae3b3-8c41-4c3d-88b5-f63d3c3a0f53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495051359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_stress_all.495051359 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2617344695 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 954144735 ps |
CPU time | 317.72 seconds |
Started | Jul 01 04:59:28 PM PDT 24 |
Finished | Jul 01 05:04:48 PM PDT 24 |
Peak memory | 355188 kb |
Host | smart-f1b0e248-9371-47d0-8ee4-66bf05f3c2f3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2617344695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2617344695 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1243829365 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 5591682099 ps |
CPU time | 127.29 seconds |
Started | Jul 01 04:59:22 PM PDT 24 |
Finished | Jul 01 05:01:31 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-ab65c01a-62de-4f14-a6a8-41e456df3188 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243829365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.1243829365 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.629906099 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 597129532 ps |
CPU time | 44.35 seconds |
Started | Jul 01 04:59:22 PM PDT 24 |
Finished | Jul 01 05:00:08 PM PDT 24 |
Peak memory | 308136 kb |
Host | smart-90b29053-f3c4-4d17-8f78-15cfbbae6eda |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629906099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_throughput_w_partial_write.629906099 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.576023453 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 4349011727 ps |
CPU time | 658.59 seconds |
Started | Jul 01 04:59:27 PM PDT 24 |
Finished | Jul 01 05:10:28 PM PDT 24 |
Peak memory | 350196 kb |
Host | smart-8bad898d-6184-47b1-89c3-c1f1604af943 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576023453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 29.sram_ctrl_access_during_key_req.576023453 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.1277821212 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 58989103 ps |
CPU time | 0.66 seconds |
Started | Jul 01 04:59:27 PM PDT 24 |
Finished | Jul 01 04:59:30 PM PDT 24 |
Peak memory | 202296 kb |
Host | smart-612fce58-a7ef-40a7-adab-8ae6943465a7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277821212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1277821212 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.1580592646 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 748680502 ps |
CPU time | 17.47 seconds |
Started | Jul 01 04:59:30 PM PDT 24 |
Finished | Jul 01 04:59:49 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-0830144e-e652-4546-8ab5-8acfe1a9c8bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580592646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .1580592646 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.4082269902 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 1564777396 ps |
CPU time | 626.86 seconds |
Started | Jul 01 04:59:26 PM PDT 24 |
Finished | Jul 01 05:09:55 PM PDT 24 |
Peak memory | 374612 kb |
Host | smart-a0589b62-2557-4b72-9612-04754a3b36d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082269902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.4082269902 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.3062487933 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 264215786 ps |
CPU time | 3.54 seconds |
Started | Jul 01 04:59:25 PM PDT 24 |
Finished | Jul 01 04:59:31 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-a3b72dd6-c447-4016-9aef-09d671fd5f73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062487933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.3062487933 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.2067616039 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 82400586 ps |
CPU time | 21.46 seconds |
Started | Jul 01 04:59:27 PM PDT 24 |
Finished | Jul 01 04:59:51 PM PDT 24 |
Peak memory | 273408 kb |
Host | smart-39da91a2-f24f-4177-a040-1e9c3aecad82 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067616039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.2067616039 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2694253254 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 212404620 ps |
CPU time | 5.97 seconds |
Started | Jul 01 04:59:29 PM PDT 24 |
Finished | Jul 01 04:59:37 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-08273055-512d-4702-a07d-7e84ec105d67 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694253254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.2694253254 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.1757290263 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 1792445514 ps |
CPU time | 11.35 seconds |
Started | Jul 01 04:59:25 PM PDT 24 |
Finished | Jul 01 04:59:39 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-90080bd8-55f1-4eea-9d42-37e00bc2ce47 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757290263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.1757290263 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.1465070842 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 8963225794 ps |
CPU time | 743.14 seconds |
Started | Jul 01 04:59:27 PM PDT 24 |
Finished | Jul 01 05:11:53 PM PDT 24 |
Peak memory | 368228 kb |
Host | smart-06116405-c058-4159-94ee-285c6c0b0cd4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465070842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.1465070842 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.1149040920 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 302148144 ps |
CPU time | 42.01 seconds |
Started | Jul 01 04:59:27 PM PDT 24 |
Finished | Jul 01 05:00:12 PM PDT 24 |
Peak memory | 305196 kb |
Host | smart-48408ff9-b25f-4db9-b781-e17c890a49c9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149040920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.1149040920 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1990125731 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 5320210771 ps |
CPU time | 197.82 seconds |
Started | Jul 01 04:59:30 PM PDT 24 |
Finished | Jul 01 05:02:49 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-4dd08c1d-e092-44f7-a05b-bd1d4f5933f5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990125731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.1990125731 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.3562934003 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 34764329 ps |
CPU time | 0.77 seconds |
Started | Jul 01 04:59:26 PM PDT 24 |
Finished | Jul 01 04:59:28 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-ffc6b2d8-2531-4d0f-8dac-425eb60b6d35 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562934003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3562934003 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.410492465 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 5434521221 ps |
CPU time | 954.52 seconds |
Started | Jul 01 04:59:25 PM PDT 24 |
Finished | Jul 01 05:15:22 PM PDT 24 |
Peak memory | 373648 kb |
Host | smart-248b50ba-7558-40bc-812b-77f76cd8e7ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410492465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.410492465 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.3171201321 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 324310659 ps |
CPU time | 7.01 seconds |
Started | Jul 01 04:59:25 PM PDT 24 |
Finished | Jul 01 04:59:34 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-6baffc6e-3eac-44d9-921a-d88d8cc5e55f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171201321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3171201321 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1024515378 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 477044432 ps |
CPU time | 16.63 seconds |
Started | Jul 01 04:59:26 PM PDT 24 |
Finished | Jul 01 04:59:45 PM PDT 24 |
Peak memory | 227524 kb |
Host | smart-8087e790-34c0-4116-9947-bcb213d395b8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1024515378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1024515378 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2427880994 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 16255527192 ps |
CPU time | 280.31 seconds |
Started | Jul 01 04:59:25 PM PDT 24 |
Finished | Jul 01 05:04:07 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-e29408a2-92b9-4f4a-b27b-1597a60c9885 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427880994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.2427880994 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2434709904 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 299731612 ps |
CPU time | 131.24 seconds |
Started | Jul 01 04:59:26 PM PDT 24 |
Finished | Jul 01 05:01:39 PM PDT 24 |
Peak memory | 369448 kb |
Host | smart-9d9b223e-9c6b-4a6a-a7e7-3237e6b7e326 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434709904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.2434709904 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.3974604861 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 1928631724 ps |
CPU time | 703.28 seconds |
Started | Jul 01 04:58:11 PM PDT 24 |
Finished | Jul 01 05:09:58 PM PDT 24 |
Peak memory | 373312 kb |
Host | smart-5313765d-2042-4010-9f91-1d21815300c3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974604861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.3974604861 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.1130928970 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 25740720 ps |
CPU time | 0.7 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 04:58:28 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-3cd8d681-0f2d-4ee0-82d3-102f69be9ba7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130928970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1130928970 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.3936646393 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 2532623680 ps |
CPU time | 26.08 seconds |
Started | Jul 01 04:58:13 PM PDT 24 |
Finished | Jul 01 04:58:41 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-ea1dd04d-81b9-4154-885e-39b18429945d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936646393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 3936646393 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.1212415376 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 15105965787 ps |
CPU time | 1249.37 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 05:19:16 PM PDT 24 |
Peak memory | 374196 kb |
Host | smart-dfd7bcdd-614b-49af-8c41-8334d192f2b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212415376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.1212415376 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.3245890018 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 214604709 ps |
CPU time | 1.55 seconds |
Started | Jul 01 04:58:14 PM PDT 24 |
Finished | Jul 01 04:58:17 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-28fb9877-e0cf-4c4f-afbf-adfe08b62bb2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245890018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.3245890018 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.2076050332 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 62685318 ps |
CPU time | 2.96 seconds |
Started | Jul 01 04:58:09 PM PDT 24 |
Finished | Jul 01 04:58:16 PM PDT 24 |
Peak memory | 218948 kb |
Host | smart-3343ba34-7cec-4b4d-b0e0-fadb0f35aa15 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076050332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.2076050332 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1169647688 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 647796257 ps |
CPU time | 3.48 seconds |
Started | Jul 01 04:58:25 PM PDT 24 |
Finished | Jul 01 04:58:34 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-5cb3ae9b-f0ca-4400-bc36-e32af5f11d34 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169647688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.1169647688 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.821306335 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 438144003 ps |
CPU time | 10.01 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 04:58:35 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-13636af7-28e6-42c3-8832-9ecd3ab09fd1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821306335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ mem_walk.821306335 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.3388876534 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 3823476266 ps |
CPU time | 1143.72 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 05:17:18 PM PDT 24 |
Peak memory | 374616 kb |
Host | smart-5967b739-07dc-4c89-a9c9-2f192d9f189c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388876534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.3388876534 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.3270187382 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 260005200 ps |
CPU time | 14.54 seconds |
Started | Jul 01 04:58:08 PM PDT 24 |
Finished | Jul 01 04:58:26 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-57d0fddd-6e07-48a5-b986-91ebcdbe8691 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270187382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.3270187382 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1953300162 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 62003918225 ps |
CPU time | 359.76 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 05:04:14 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-2acef7c6-bee3-4a70-98f6-fa4cb12304b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953300162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.1953300162 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.222581831 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 28604286 ps |
CPU time | 0.79 seconds |
Started | Jul 01 04:58:19 PM PDT 24 |
Finished | Jul 01 04:58:22 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-ef2f3346-6148-4a7f-ba14-10f8312f7e80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222581831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.222581831 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.1010199105 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 9896415666 ps |
CPU time | 832.3 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:12:17 PM PDT 24 |
Peak memory | 372552 kb |
Host | smart-981d2f86-f5bd-4cac-ba97-e0e1ec154c45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010199105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1010199105 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.2607107343 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 431368683 ps |
CPU time | 3.32 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 04:58:28 PM PDT 24 |
Peak memory | 222052 kb |
Host | smart-f3357513-d4a4-4aa1-abe6-40ba6c7770ea |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607107343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.2607107343 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.626805274 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 7105233199 ps |
CPU time | 17.52 seconds |
Started | Jul 01 04:58:09 PM PDT 24 |
Finished | Jul 01 04:58:30 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-28bd5c91-102e-4dd9-91f1-f8ea1aa96949 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626805274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.626805274 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.3860451194 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 50295477122 ps |
CPU time | 2101.28 seconds |
Started | Jul 01 04:58:20 PM PDT 24 |
Finished | Jul 01 05:33:24 PM PDT 24 |
Peak memory | 376600 kb |
Host | smart-f5c15194-ec71-450c-8b07-16af135f5023 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860451194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.3860451194 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3991216249 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 2410738760 ps |
CPU time | 236.89 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 05:02:28 PM PDT 24 |
Peak memory | 374788 kb |
Host | smart-aef2fa14-a217-4591-875e-7517a3bc17b2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3991216249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3991216249 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1006157535 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 4742227067 ps |
CPU time | 221.74 seconds |
Started | Jul 01 04:58:10 PM PDT 24 |
Finished | Jul 01 05:01:55 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-606c129e-17fc-474a-af15-8a1e41ef1263 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006157535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.1006157535 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2887950014 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 1110025662 ps |
CPU time | 135.8 seconds |
Started | Jul 01 04:58:08 PM PDT 24 |
Finished | Jul 01 05:00:27 PM PDT 24 |
Peak memory | 369192 kb |
Host | smart-740dd9ac-0454-4df2-b1d6-91f30575c22d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887950014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2887950014 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3949856962 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 2174848104 ps |
CPU time | 447.9 seconds |
Started | Jul 01 04:59:37 PM PDT 24 |
Finished | Jul 01 05:07:07 PM PDT 24 |
Peak memory | 372528 kb |
Host | smart-9e32f535-42f4-4e07-b5f1-71f1a82d0a90 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949856962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.3949856962 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.4106727582 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 42268157 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:59:35 PM PDT 24 |
Finished | Jul 01 04:59:38 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-8545adb6-054b-44dd-acfb-5a17cc6cb872 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106727582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.4106727582 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.4227656078 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 3268532873 ps |
CPU time | 71.67 seconds |
Started | Jul 01 04:59:27 PM PDT 24 |
Finished | Jul 01 05:00:41 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-d5a1d092-0f08-4b56-9e47-578e9bbe2b74 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227656078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .4227656078 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.2287928059 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 20689387896 ps |
CPU time | 235.66 seconds |
Started | Jul 01 04:59:34 PM PDT 24 |
Finished | Jul 01 05:03:31 PM PDT 24 |
Peak memory | 368136 kb |
Host | smart-738bebb1-0d4b-4a04-ab10-ae5c56c8860c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287928059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.2287928059 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.2647694562 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 1262770781 ps |
CPU time | 8.66 seconds |
Started | Jul 01 04:59:36 PM PDT 24 |
Finished | Jul 01 04:59:46 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-b1aacbc4-32a5-40e2-a199-d18638c7d272 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647694562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.2647694562 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.3428896955 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 130190625 ps |
CPU time | 24.53 seconds |
Started | Jul 01 04:59:26 PM PDT 24 |
Finished | Jul 01 04:59:52 PM PDT 24 |
Peak memory | 277692 kb |
Host | smart-7002641a-a0ca-479e-b4e3-60de15499cc6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428896955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.3428896955 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2515977705 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 108216374 ps |
CPU time | 3.16 seconds |
Started | Jul 01 04:59:32 PM PDT 24 |
Finished | Jul 01 04:59:36 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-e52ad58a-c0fe-400f-bf90-70b9c6436f62 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515977705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.2515977705 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.3547974971 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 2427959038 ps |
CPU time | 11.76 seconds |
Started | Jul 01 04:59:35 PM PDT 24 |
Finished | Jul 01 04:59:48 PM PDT 24 |
Peak memory | 211156 kb |
Host | smart-53031033-92bc-4248-ae21-53aa617e9d30 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547974971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.3547974971 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1924450751 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 19918077461 ps |
CPU time | 1318.65 seconds |
Started | Jul 01 04:59:26 PM PDT 24 |
Finished | Jul 01 05:21:28 PM PDT 24 |
Peak memory | 370584 kb |
Host | smart-9a52e6e1-ee9f-4d75-b883-a72454f39e6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924450751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1924450751 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.3955132042 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 64883268 ps |
CPU time | 3.04 seconds |
Started | Jul 01 04:59:28 PM PDT 24 |
Finished | Jul 01 04:59:33 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-adc151a7-5b1d-4492-b8a6-85f6ccfa88e5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955132042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.3955132042 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.47707548 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 10142496132 ps |
CPU time | 270.16 seconds |
Started | Jul 01 04:59:28 PM PDT 24 |
Finished | Jul 01 05:04:00 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-07fc1f9d-443c-448d-a385-fd33c1ef5428 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47707548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_partial_access_b2b.47707548 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.877531208 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 26911784 ps |
CPU time | 0.77 seconds |
Started | Jul 01 04:59:36 PM PDT 24 |
Finished | Jul 01 04:59:38 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-c080dd8b-eee8-45fb-bc33-e8e2d10eeb8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877531208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.877531208 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.2543094354 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 62515300023 ps |
CPU time | 882.62 seconds |
Started | Jul 01 04:59:34 PM PDT 24 |
Finished | Jul 01 05:14:18 PM PDT 24 |
Peak memory | 350220 kb |
Host | smart-cff07220-e4ad-4e9f-8009-bbf8cad09148 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543094354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2543094354 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.1166894392 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 168612079 ps |
CPU time | 9.68 seconds |
Started | Jul 01 04:59:26 PM PDT 24 |
Finished | Jul 01 04:59:38 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-b4b6261a-8f9d-4925-be7e-134fcc4ce296 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166894392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1166894392 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.4007346576 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 600741116997 ps |
CPU time | 3783.98 seconds |
Started | Jul 01 04:59:34 PM PDT 24 |
Finished | Jul 01 06:02:40 PM PDT 24 |
Peak memory | 376820 kb |
Host | smart-05040dee-bede-4a88-94e5-2a1b52916a73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007346576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.4007346576 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1735532012 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 4312899407 ps |
CPU time | 216.43 seconds |
Started | Jul 01 04:59:27 PM PDT 24 |
Finished | Jul 01 05:03:06 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-1ba0abfc-82d6-4cd7-8684-990860180990 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735532012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.1735532012 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3780894637 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 267131288 ps |
CPU time | 69.25 seconds |
Started | Jul 01 04:59:27 PM PDT 24 |
Finished | Jul 01 05:00:38 PM PDT 24 |
Peak memory | 341892 kb |
Host | smart-477a4342-8983-48cf-a298-e42b49dae909 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780894637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3780894637 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2079712871 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 2771642066 ps |
CPU time | 741.31 seconds |
Started | Jul 01 04:59:35 PM PDT 24 |
Finished | Jul 01 05:11:58 PM PDT 24 |
Peak memory | 370668 kb |
Host | smart-0d93dd6b-7de4-40e6-a26b-a70e4ec6d421 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079712871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.2079712871 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.3095886973 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 43479606 ps |
CPU time | 0.66 seconds |
Started | Jul 01 04:59:41 PM PDT 24 |
Finished | Jul 01 04:59:44 PM PDT 24 |
Peak memory | 202320 kb |
Host | smart-235964dc-4aae-428f-9b40-fed9c1a9a20b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095886973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3095886973 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.1104954746 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 1792080028 ps |
CPU time | 60.48 seconds |
Started | Jul 01 04:59:38 PM PDT 24 |
Finished | Jul 01 05:00:40 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-d47a93a4-b2bd-441a-8697-c4cb60b68595 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104954746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .1104954746 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.3587310327 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 3840140527 ps |
CPU time | 1346.37 seconds |
Started | Jul 01 04:59:32 PM PDT 24 |
Finished | Jul 01 05:21:59 PM PDT 24 |
Peak memory | 368308 kb |
Host | smart-4d111684-83f0-4dd1-9ef8-be7b2215e311 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587310327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.3587310327 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.2354602273 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 951084452 ps |
CPU time | 6.09 seconds |
Started | Jul 01 04:59:33 PM PDT 24 |
Finished | Jul 01 04:59:40 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-3d674147-24f2-43f2-879d-281b16fb4b8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354602273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.2354602273 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.2965156615 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 406857409 ps |
CPU time | 33.68 seconds |
Started | Jul 01 04:59:34 PM PDT 24 |
Finished | Jul 01 05:00:09 PM PDT 24 |
Peak memory | 279472 kb |
Host | smart-606c44ab-6737-43b5-a265-2763c1b3613c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965156615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.2965156615 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2111795077 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 338954151 ps |
CPU time | 6.02 seconds |
Started | Jul 01 04:59:43 PM PDT 24 |
Finished | Jul 01 04:59:51 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-24672d5b-d0d4-408e-ab8a-fc87ce5ef19a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111795077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.2111795077 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.173063105 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 136127011 ps |
CPU time | 8.9 seconds |
Started | Jul 01 04:59:41 PM PDT 24 |
Finished | Jul 01 04:59:52 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-a16a4cf7-917c-472a-a9ae-42f0c6170878 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173063105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl _mem_walk.173063105 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.2192582569 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 36794168163 ps |
CPU time | 1060.01 seconds |
Started | Jul 01 04:59:38 PM PDT 24 |
Finished | Jul 01 05:17:19 PM PDT 24 |
Peak memory | 374320 kb |
Host | smart-1f5e4ac5-254a-418d-b03c-ea234d34e88e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192582569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.2192582569 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.3357201424 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 1229574585 ps |
CPU time | 17.45 seconds |
Started | Jul 01 04:59:34 PM PDT 24 |
Finished | Jul 01 04:59:52 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-5220016b-e9e7-4b6e-b1e4-75e729ae42df |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357201424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.3357201424 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2440276809 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 5553127838 ps |
CPU time | 381.63 seconds |
Started | Jul 01 04:59:34 PM PDT 24 |
Finished | Jul 01 05:05:57 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-c94969cf-5ec8-4e5c-b9b0-fff453a58af9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440276809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2440276809 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.2396212179 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 105127351 ps |
CPU time | 0.74 seconds |
Started | Jul 01 04:59:45 PM PDT 24 |
Finished | Jul 01 04:59:48 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-cee58d24-3034-4e4b-9ec1-5aa1a0231f8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396212179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2396212179 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.654023195 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 821061788 ps |
CPU time | 321.92 seconds |
Started | Jul 01 04:59:42 PM PDT 24 |
Finished | Jul 01 05:05:06 PM PDT 24 |
Peak memory | 371976 kb |
Host | smart-3b825487-1ac4-46d1-b9d2-5abf7b051ca8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654023195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.654023195 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.357412498 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 4841169315 ps |
CPU time | 47.55 seconds |
Started | Jul 01 04:59:37 PM PDT 24 |
Finished | Jul 01 05:00:25 PM PDT 24 |
Peak memory | 301084 kb |
Host | smart-40a3ab88-00be-42b0-8ab4-fb24c195ee0a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357412498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.357412498 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.3214201869 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 19672526853 ps |
CPU time | 238.56 seconds |
Started | Jul 01 04:59:41 PM PDT 24 |
Finished | Jul 01 05:03:42 PM PDT 24 |
Peak memory | 215348 kb |
Host | smart-5242ca87-6470-4bdd-b026-2d1ecc28022f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214201869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.3214201869 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.565905892 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 6144474180 ps |
CPU time | 444.2 seconds |
Started | Jul 01 04:59:41 PM PDT 24 |
Finished | Jul 01 05:07:07 PM PDT 24 |
Peak memory | 376920 kb |
Host | smart-dbc757e2-2913-4bfe-8e93-6442211517c3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=565905892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.565905892 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1290774045 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 2061591510 ps |
CPU time | 208.29 seconds |
Started | Jul 01 04:59:35 PM PDT 24 |
Finished | Jul 01 05:03:05 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-9fd5e736-6252-439b-ba7d-a55eba811a81 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290774045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.1290774045 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1244167381 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 86906320 ps |
CPU time | 9.98 seconds |
Started | Jul 01 04:59:35 PM PDT 24 |
Finished | Jul 01 04:59:46 PM PDT 24 |
Peak memory | 242184 kb |
Host | smart-3a74b342-dd9b-4a4d-b96b-6d43a990b3e2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244167381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1244167381 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2444898033 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 2925369809 ps |
CPU time | 623.32 seconds |
Started | Jul 01 04:59:41 PM PDT 24 |
Finished | Jul 01 05:10:06 PM PDT 24 |
Peak memory | 368276 kb |
Host | smart-bd586198-0eb7-45ad-9889-8809a7ad7dfb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444898033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.2444898033 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.2831482948 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 10666973 ps |
CPU time | 0.63 seconds |
Started | Jul 01 04:59:42 PM PDT 24 |
Finished | Jul 01 04:59:45 PM PDT 24 |
Peak memory | 202624 kb |
Host | smart-50b7802c-cef5-4086-b533-678005e0ad74 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831482948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.2831482948 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.960984977 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 649079807 ps |
CPU time | 43.39 seconds |
Started | Jul 01 04:59:42 PM PDT 24 |
Finished | Jul 01 05:00:28 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-d281958e-a38f-4bc2-a3e1-781ea58d04ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960984977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection. 960984977 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.4069698773 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 2840165639 ps |
CPU time | 792.2 seconds |
Started | Jul 01 04:59:43 PM PDT 24 |
Finished | Jul 01 05:12:57 PM PDT 24 |
Peak memory | 365576 kb |
Host | smart-d820ccd3-2a89-4a6c-b6b4-22ff863efe83 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069698773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.4069698773 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.1950388325 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 227235693 ps |
CPU time | 2.88 seconds |
Started | Jul 01 04:59:40 PM PDT 24 |
Finished | Jul 01 04:59:45 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-ec82ca63-9179-4dab-9236-3446f52dd637 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950388325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.1950388325 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.3835827668 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 332570365 ps |
CPU time | 42.85 seconds |
Started | Jul 01 04:59:42 PM PDT 24 |
Finished | Jul 01 05:00:27 PM PDT 24 |
Peak memory | 300200 kb |
Host | smart-56ac68c0-7df9-4e90-a1d1-314ff5deb289 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835827668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.3835827668 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3069067802 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 110856614 ps |
CPU time | 3.21 seconds |
Started | Jul 01 04:59:42 PM PDT 24 |
Finished | Jul 01 04:59:48 PM PDT 24 |
Peak memory | 211292 kb |
Host | smart-3ae5808c-17af-4586-8651-2a6ff1217782 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069067802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.3069067802 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.3228781519 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 142030202 ps |
CPU time | 8.44 seconds |
Started | Jul 01 04:59:40 PM PDT 24 |
Finished | Jul 01 04:59:50 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-ca271962-0de3-4f37-a14b-1f6ec79e0d08 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228781519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3228781519 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.3093906676 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 11458042007 ps |
CPU time | 379.69 seconds |
Started | Jul 01 04:59:41 PM PDT 24 |
Finished | Jul 01 05:06:04 PM PDT 24 |
Peak memory | 339788 kb |
Host | smart-8bf58d4d-cb90-4151-972c-97c98517d327 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093906676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.3093906676 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.4074137240 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 2613091529 ps |
CPU time | 12.48 seconds |
Started | Jul 01 04:59:45 PM PDT 24 |
Finished | Jul 01 05:00:00 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-f226b80b-ade1-469b-a748-c37b0b8a2197 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074137240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.4074137240 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2534737523 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 13152959001 ps |
CPU time | 355.38 seconds |
Started | Jul 01 04:59:41 PM PDT 24 |
Finished | Jul 01 05:05:39 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-8487ed25-b7a6-4c7f-9cee-e4f3c14c6b97 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534737523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.2534737523 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.1257905101 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 29811361 ps |
CPU time | 0.81 seconds |
Started | Jul 01 04:59:41 PM PDT 24 |
Finished | Jul 01 04:59:45 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-e9ac8277-dc05-4b5c-b882-2cd1556b2bd2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257905101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1257905101 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.742403298 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 11105705213 ps |
CPU time | 381.12 seconds |
Started | Jul 01 04:59:46 PM PDT 24 |
Finished | Jul 01 05:06:09 PM PDT 24 |
Peak memory | 333784 kb |
Host | smart-073968e1-bc8a-462b-b53c-8785da611b0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742403298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.742403298 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.1483705363 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 678040595 ps |
CPU time | 3.09 seconds |
Started | Jul 01 04:59:42 PM PDT 24 |
Finished | Jul 01 04:59:47 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-101e217d-ce7f-4f7d-bd78-248e9e606e52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483705363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1483705363 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.3425935498 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 13699400055 ps |
CPU time | 365.09 seconds |
Started | Jul 01 04:59:45 PM PDT 24 |
Finished | Jul 01 05:05:53 PM PDT 24 |
Peak memory | 352460 kb |
Host | smart-3aa00036-1c55-4505-89e4-370e4a4ce1b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425935498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.3425935498 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2789902152 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 393194698 ps |
CPU time | 13.4 seconds |
Started | Jul 01 04:59:42 PM PDT 24 |
Finished | Jul 01 04:59:58 PM PDT 24 |
Peak memory | 211216 kb |
Host | smart-f5f7d0f1-310e-4724-bcbb-17c5721aa801 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2789902152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.2789902152 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.752077427 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 3069474175 ps |
CPU time | 280.02 seconds |
Started | Jul 01 04:59:45 PM PDT 24 |
Finished | Jul 01 05:04:27 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-923f41a1-0ee6-4a4f-bda2-c6efa259d33d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752077427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .sram_ctrl_stress_pipeline.752077427 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.872250037 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 146326937 ps |
CPU time | 115.79 seconds |
Started | Jul 01 04:59:39 PM PDT 24 |
Finished | Jul 01 05:01:36 PM PDT 24 |
Peak memory | 357008 kb |
Host | smart-aff1c33b-0b3d-48d9-bc7d-f67aaccd80e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872250037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_throughput_w_partial_write.872250037 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1092924252 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 361988090 ps |
CPU time | 213.8 seconds |
Started | Jul 01 04:59:53 PM PDT 24 |
Finished | Jul 01 05:03:30 PM PDT 24 |
Peak memory | 368376 kb |
Host | smart-60a86d95-b56b-4088-9f8c-b9327979b393 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092924252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.1092924252 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.1964990474 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 11788953 ps |
CPU time | 0.67 seconds |
Started | Jul 01 04:59:53 PM PDT 24 |
Finished | Jul 01 04:59:57 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-2f7e2f9d-6389-4893-b6d0-aa0928ff900d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964990474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.1964990474 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.1355948583 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 8686806351 ps |
CPU time | 47.63 seconds |
Started | Jul 01 04:59:45 PM PDT 24 |
Finished | Jul 01 05:00:35 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-76e0dab0-87bc-4df2-8175-4c681e95ce96 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355948583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .1355948583 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.711461803 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 3499522005 ps |
CPU time | 1053.95 seconds |
Started | Jul 01 04:59:57 PM PDT 24 |
Finished | Jul 01 05:17:33 PM PDT 24 |
Peak memory | 370560 kb |
Host | smart-f9383f0a-996c-4aec-aba1-60eab4241520 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711461803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executabl e.711461803 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.2402497439 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 353351781 ps |
CPU time | 1.66 seconds |
Started | Jul 01 04:59:51 PM PDT 24 |
Finished | Jul 01 04:59:56 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-ee02117e-5b07-46c4-8410-cfec60a2854a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402497439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.2402497439 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.1156699706 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 107051588 ps |
CPU time | 3.62 seconds |
Started | Jul 01 04:59:53 PM PDT 24 |
Finished | Jul 01 05:00:01 PM PDT 24 |
Peak memory | 220780 kb |
Host | smart-23562518-a760-4913-8538-d29deaae50d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156699706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.1156699706 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.368222685 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 258008503 ps |
CPU time | 5.42 seconds |
Started | Jul 01 04:59:51 PM PDT 24 |
Finished | Jul 01 04:59:59 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-62eff409-e1ef-4bfc-8ec4-95dc067c6019 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368222685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .sram_ctrl_mem_partial_access.368222685 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.3138280548 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 236712325 ps |
CPU time | 5.82 seconds |
Started | Jul 01 04:59:52 PM PDT 24 |
Finished | Jul 01 05:00:01 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-584907c8-7bf3-4a0f-989c-0e2b610881e8 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138280548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.3138280548 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.3333236963 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 7933943261 ps |
CPU time | 696.38 seconds |
Started | Jul 01 04:59:42 PM PDT 24 |
Finished | Jul 01 05:11:21 PM PDT 24 |
Peak memory | 371456 kb |
Host | smart-cd08108e-9072-4355-9330-87d1a9a4d93e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333236963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.3333236963 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.1483551141 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 663527626 ps |
CPU time | 28.72 seconds |
Started | Jul 01 04:59:41 PM PDT 24 |
Finished | Jul 01 05:00:12 PM PDT 24 |
Peak memory | 275752 kb |
Host | smart-5551ba75-b9dc-4d49-9a44-1fee4ff7b17d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483551141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.1483551141 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2004831743 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 71619616535 ps |
CPU time | 441.03 seconds |
Started | Jul 01 04:59:54 PM PDT 24 |
Finished | Jul 01 05:07:19 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-b6a21ff6-0d95-413f-ac32-4841932c2948 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004831743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2004831743 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.3278821925 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 41730592 ps |
CPU time | 0.82 seconds |
Started | Jul 01 04:59:54 PM PDT 24 |
Finished | Jul 01 04:59:59 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-0ff96751-35ed-4d01-ba10-6e8fc3f39041 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278821925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3278821925 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.3372618535 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 20360985488 ps |
CPU time | 721.01 seconds |
Started | Jul 01 04:59:54 PM PDT 24 |
Finished | Jul 01 05:11:59 PM PDT 24 |
Peak memory | 364404 kb |
Host | smart-347d5a32-322a-42c1-8a26-cc459206491d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372618535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3372618535 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.2765477189 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 9914898365 ps |
CPU time | 172.2 seconds |
Started | Jul 01 04:59:42 PM PDT 24 |
Finished | Jul 01 05:02:37 PM PDT 24 |
Peak memory | 366564 kb |
Host | smart-3e214271-7f9a-4aa2-83b1-8e8cad95a415 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765477189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2765477189 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.2196928452 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 99030485848 ps |
CPU time | 2828.16 seconds |
Started | Jul 01 04:59:53 PM PDT 24 |
Finished | Jul 01 05:47:05 PM PDT 24 |
Peak memory | 375800 kb |
Host | smart-9bb84a84-0e63-453c-ba03-fc4eb816c0bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196928452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.2196928452 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.643583110 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 1372267826 ps |
CPU time | 161.85 seconds |
Started | Jul 01 04:59:54 PM PDT 24 |
Finished | Jul 01 05:02:40 PM PDT 24 |
Peak memory | 365528 kb |
Host | smart-68dc420b-8950-467f-a782-7182b9127cf7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=643583110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.643583110 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2107278345 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 10266407409 ps |
CPU time | 362 seconds |
Started | Jul 01 04:59:45 PM PDT 24 |
Finished | Jul 01 05:05:50 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-ae8892b0-0d63-4815-b812-e6326d9a02b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107278345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.2107278345 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2902138963 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 121197932 ps |
CPU time | 67.38 seconds |
Started | Jul 01 04:59:49 PM PDT 24 |
Finished | Jul 01 05:00:59 PM PDT 24 |
Peak memory | 319400 kb |
Host | smart-9721bb35-ea06-4775-9314-9102c30c8436 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902138963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2902138963 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3840209014 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 10093735801 ps |
CPU time | 429 seconds |
Started | Jul 01 04:59:54 PM PDT 24 |
Finished | Jul 01 05:07:07 PM PDT 24 |
Peak memory | 351220 kb |
Host | smart-2fcacff6-b8cc-4f9f-80a8-c7bd773a373c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840209014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.3840209014 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.3924611009 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 10609551 ps |
CPU time | 0.68 seconds |
Started | Jul 01 05:00:03 PM PDT 24 |
Finished | Jul 01 05:00:06 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-2c082f96-9227-4fb3-a408-b14fdf6fd27b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924611009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3924611009 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.739940414 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 3321743528 ps |
CPU time | 74.52 seconds |
Started | Jul 01 04:59:53 PM PDT 24 |
Finished | Jul 01 05:01:11 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-3e3cef65-3743-46d9-bf19-01260a8324a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739940414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection. 739940414 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.2362622998 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 2961583473 ps |
CPU time | 6.81 seconds |
Started | Jul 01 04:59:54 PM PDT 24 |
Finished | Jul 01 05:00:04 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-b78df231-972b-4837-afa4-e7f2ab720867 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362622998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.2362622998 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.3978283377 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 60818815 ps |
CPU time | 6.82 seconds |
Started | Jul 01 04:59:52 PM PDT 24 |
Finished | Jul 01 05:00:01 PM PDT 24 |
Peak memory | 236584 kb |
Host | smart-45cb4761-3a16-4376-9996-0032d98e3334 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978283377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.3978283377 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2065995348 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 151632157 ps |
CPU time | 5.41 seconds |
Started | Jul 01 05:00:06 PM PDT 24 |
Finished | Jul 01 05:00:13 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-0a87ade8-d363-4761-bb35-2e9a4022156a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065995348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.2065995348 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.567265711 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 2482329673 ps |
CPU time | 11.94 seconds |
Started | Jul 01 05:00:01 PM PDT 24 |
Finished | Jul 01 05:00:15 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-22097315-d62c-428d-97d3-749829db1a85 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567265711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl _mem_walk.567265711 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.969146979 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 10662997644 ps |
CPU time | 1501.48 seconds |
Started | Jul 01 04:59:52 PM PDT 24 |
Finished | Jul 01 05:24:57 PM PDT 24 |
Peak memory | 375616 kb |
Host | smart-536d6564-afe5-43dc-9c31-8a4f6a3fad4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969146979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multip le_keys.969146979 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.1032628995 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 1692645435 ps |
CPU time | 17.51 seconds |
Started | Jul 01 04:59:54 PM PDT 24 |
Finished | Jul 01 05:00:15 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-8f438584-4047-47df-a775-7c1ed1a4ca23 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032628995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.1032628995 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.394848610 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 21551633326 ps |
CPU time | 318.94 seconds |
Started | Jul 01 04:59:53 PM PDT 24 |
Finished | Jul 01 05:05:16 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-95872b14-aae7-48ca-a395-9e777ae46e54 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394848610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.sram_ctrl_partial_access_b2b.394848610 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.3900414970 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 331708361 ps |
CPU time | 0.88 seconds |
Started | Jul 01 04:59:54 PM PDT 24 |
Finished | Jul 01 04:59:59 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-1f7ea59f-3635-4171-86f7-65a767161d9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900414970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3900414970 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.1921754381 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 7939479205 ps |
CPU time | 802.16 seconds |
Started | Jul 01 04:59:52 PM PDT 24 |
Finished | Jul 01 05:13:18 PM PDT 24 |
Peak memory | 372664 kb |
Host | smart-e6e2a58b-73c6-4203-b0ae-b021b741a1db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921754381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1921754381 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.3053097956 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 664912950 ps |
CPU time | 105.64 seconds |
Started | Jul 01 04:59:51 PM PDT 24 |
Finished | Jul 01 05:01:39 PM PDT 24 |
Peak memory | 357044 kb |
Host | smart-4154bf49-aa9a-4cd0-b1c5-678d7553d96a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053097956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3053097956 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.2654338708 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 308974271648 ps |
CPU time | 6444.75 seconds |
Started | Jul 01 05:00:01 PM PDT 24 |
Finished | Jul 01 06:47:29 PM PDT 24 |
Peak memory | 375708 kb |
Host | smart-da6c1277-affd-4a7f-b8d4-5e19da0794b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654338708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.2654338708 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.3231651914 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 4073206379 ps |
CPU time | 187.98 seconds |
Started | Jul 01 04:59:52 PM PDT 24 |
Finished | Jul 01 05:03:04 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-ffbd4d83-014b-4c23-8829-3b696c0b9089 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231651914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.3231651914 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1413212424 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 151978299 ps |
CPU time | 145.22 seconds |
Started | Jul 01 04:59:54 PM PDT 24 |
Finished | Jul 01 05:02:23 PM PDT 24 |
Peak memory | 369392 kb |
Host | smart-722251a2-39f5-4980-96c1-dd13ff5c0620 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413212424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1413212424 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.856264747 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 19161115551 ps |
CPU time | 1744.68 seconds |
Started | Jul 01 05:00:04 PM PDT 24 |
Finished | Jul 01 05:29:11 PM PDT 24 |
Peak memory | 375456 kb |
Host | smart-31ec3d45-53e7-4daa-9dd9-76e6657c190d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856264747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 35.sram_ctrl_access_during_key_req.856264747 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.941225972 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 17130620 ps |
CPU time | 0.67 seconds |
Started | Jul 01 05:00:03 PM PDT 24 |
Finished | Jul 01 05:00:06 PM PDT 24 |
Peak memory | 202280 kb |
Host | smart-8eba61ff-40e6-402a-8bb4-60efc4f4d3db |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941225972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.941225972 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.2996267129 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 5619546195 ps |
CPU time | 49.89 seconds |
Started | Jul 01 05:00:02 PM PDT 24 |
Finished | Jul 01 05:00:55 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-e087162a-7829-44dd-8a7c-1ea49573225f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996267129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .2996267129 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.3145096092 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 18751852456 ps |
CPU time | 311.62 seconds |
Started | Jul 01 05:00:04 PM PDT 24 |
Finished | Jul 01 05:05:18 PM PDT 24 |
Peak memory | 315320 kb |
Host | smart-851ede79-e241-44af-978c-ff70690d2c32 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145096092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.3145096092 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.4230988661 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 438869760 ps |
CPU time | 5.65 seconds |
Started | Jul 01 05:00:02 PM PDT 24 |
Finished | Jul 01 05:00:10 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-aa421810-796d-4572-a672-d599e88ccc11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230988661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.4230988661 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.1636587590 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 86855367 ps |
CPU time | 30.35 seconds |
Started | Jul 01 05:00:00 PM PDT 24 |
Finished | Jul 01 05:00:32 PM PDT 24 |
Peak memory | 284484 kb |
Host | smart-be7e8d99-3fd6-44e8-b528-76511c8cb29e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636587590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.1636587590 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2172499757 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 617213484 ps |
CPU time | 3.29 seconds |
Started | Jul 01 05:00:02 PM PDT 24 |
Finished | Jul 01 05:00:07 PM PDT 24 |
Peak memory | 210852 kb |
Host | smart-4a63eb2a-9baa-458f-8b86-a3bab14c91a0 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172499757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.2172499757 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.3112042443 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 1340082957 ps |
CPU time | 11.2 seconds |
Started | Jul 01 05:00:03 PM PDT 24 |
Finished | Jul 01 05:00:16 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-305e9f0f-37da-40c8-9cc6-d1c2253b2441 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112042443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.3112042443 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.462090693 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 3086663481 ps |
CPU time | 699.28 seconds |
Started | Jul 01 05:00:00 PM PDT 24 |
Finished | Jul 01 05:11:41 PM PDT 24 |
Peak memory | 375752 kb |
Host | smart-eb9b4bf9-2123-4a1e-96ec-e151867f5006 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462090693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip le_keys.462090693 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.3125740199 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 359244571 ps |
CPU time | 25.27 seconds |
Started | Jul 01 05:00:06 PM PDT 24 |
Finished | Jul 01 05:00:33 PM PDT 24 |
Peak memory | 280244 kb |
Host | smart-14905217-1a26-4f0c-bbd2-7e71b9b597ec |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125740199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3125740199 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3250460067 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 30244277234 ps |
CPU time | 420 seconds |
Started | Jul 01 04:59:59 PM PDT 24 |
Finished | Jul 01 05:07:01 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-486e1c4f-1e88-4abd-bc83-1929abacb647 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250460067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.3250460067 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.3357453851 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 49083497 ps |
CPU time | 0.78 seconds |
Started | Jul 01 04:59:59 PM PDT 24 |
Finished | Jul 01 05:00:01 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-df151e72-796a-4075-a4f8-795ef5545e8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357453851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3357453851 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.1504291695 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 28090004378 ps |
CPU time | 1439.54 seconds |
Started | Jul 01 05:00:01 PM PDT 24 |
Finished | Jul 01 05:24:03 PM PDT 24 |
Peak memory | 374704 kb |
Host | smart-11b04c8f-8d09-4a91-ab30-667999cbee67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504291695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1504291695 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.2808834521 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 138182835 ps |
CPU time | 132.35 seconds |
Started | Jul 01 05:00:00 PM PDT 24 |
Finished | Jul 01 05:02:14 PM PDT 24 |
Peak memory | 367904 kb |
Host | smart-bae11d03-09bc-4e6e-8447-ba690c3161e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808834521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2808834521 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.2437352009 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 42906293816 ps |
CPU time | 3618.9 seconds |
Started | Jul 01 05:00:00 PM PDT 24 |
Finished | Jul 01 06:00:21 PM PDT 24 |
Peak memory | 375508 kb |
Host | smart-23218cd3-2112-45dc-84a9-993ae7f9ef58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437352009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.2437352009 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.758812263 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 3079065734 ps |
CPU time | 81.84 seconds |
Started | Jul 01 05:00:01 PM PDT 24 |
Finished | Jul 01 05:01:26 PM PDT 24 |
Peak memory | 321416 kb |
Host | smart-ef9162c4-cf63-417b-88c1-ead872a9eae2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=758812263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.758812263 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1039654202 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 4146515311 ps |
CPU time | 200.09 seconds |
Started | Jul 01 05:00:03 PM PDT 24 |
Finished | Jul 01 05:03:25 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-98950f69-57eb-4d94-9563-1f9a24cddf97 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039654202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1039654202 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3332885371 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 138989906 ps |
CPU time | 104.32 seconds |
Started | Jul 01 05:00:02 PM PDT 24 |
Finished | Jul 01 05:01:49 PM PDT 24 |
Peak memory | 347164 kb |
Host | smart-9a9aa583-bb80-439b-9e76-c9978a20e628 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332885371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3332885371 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2825538507 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 11776415463 ps |
CPU time | 1294.43 seconds |
Started | Jul 01 05:00:06 PM PDT 24 |
Finished | Jul 01 05:21:42 PM PDT 24 |
Peak memory | 370544 kb |
Host | smart-16cff2ad-dcc8-44b9-b573-aab8205c5d80 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825538507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.2825538507 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.2489869899 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 17526360 ps |
CPU time | 0.68 seconds |
Started | Jul 01 05:00:08 PM PDT 24 |
Finished | Jul 01 05:00:10 PM PDT 24 |
Peak memory | 202304 kb |
Host | smart-4e5b5bec-8ab4-4381-849d-67734ca8c6bd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489869899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.2489869899 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.561859818 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 538043975 ps |
CPU time | 33.93 seconds |
Started | Jul 01 05:00:03 PM PDT 24 |
Finished | Jul 01 05:00:39 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-fc9b5f4a-ca2b-4334-88df-9ade090e235d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561859818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection. 561859818 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.3347803178 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 5139399088 ps |
CPU time | 481.45 seconds |
Started | Jul 01 05:00:03 PM PDT 24 |
Finished | Jul 01 05:08:06 PM PDT 24 |
Peak memory | 374344 kb |
Host | smart-0cc4fc1b-9449-43fb-94e2-18237913751f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347803178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.3347803178 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.2002331735 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 452255356 ps |
CPU time | 2.25 seconds |
Started | Jul 01 05:00:02 PM PDT 24 |
Finished | Jul 01 05:00:07 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-5f03c0e7-7737-4edd-aeb1-e51d23e6cfa7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002331735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.2002331735 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.180132591 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 409529692 ps |
CPU time | 1.18 seconds |
Started | Jul 01 05:00:01 PM PDT 24 |
Finished | Jul 01 05:00:05 PM PDT 24 |
Peak memory | 210608 kb |
Host | smart-7e485356-2550-40c4-83c1-1774637682b4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180132591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.sram_ctrl_max_throughput.180132591 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.952277325 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 224665407 ps |
CPU time | 3.04 seconds |
Started | Jul 01 05:00:07 PM PDT 24 |
Finished | Jul 01 05:00:12 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-c4020501-0942-4936-b170-73e363cd11de |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952277325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .sram_ctrl_mem_partial_access.952277325 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.1655855783 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 146467257 ps |
CPU time | 4.45 seconds |
Started | Jul 01 05:00:09 PM PDT 24 |
Finished | Jul 01 05:00:15 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-38dcaf6a-12f7-4afa-8aff-bc8ad5c5981a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655855783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.1655855783 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.954006744 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 67370311612 ps |
CPU time | 1523.25 seconds |
Started | Jul 01 05:00:04 PM PDT 24 |
Finished | Jul 01 05:25:29 PM PDT 24 |
Peak memory | 373036 kb |
Host | smart-19885478-0694-453e-a65a-2bd09cdc5555 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954006744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multip le_keys.954006744 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.2185328372 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 324524275 ps |
CPU time | 27.05 seconds |
Started | Jul 01 05:00:01 PM PDT 24 |
Finished | Jul 01 05:00:30 PM PDT 24 |
Peak memory | 279528 kb |
Host | smart-7f2d28ff-38ef-44f8-bc8b-0a71de67d362 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185328372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.2185328372 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1344431866 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 42023568818 ps |
CPU time | 176.21 seconds |
Started | Jul 01 05:00:04 PM PDT 24 |
Finished | Jul 01 05:03:02 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-fd4cc4fa-dee5-487e-8631-73a5c9751b75 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344431866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.1344431866 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.2696350790 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 30212018 ps |
CPU time | 0.8 seconds |
Started | Jul 01 05:00:02 PM PDT 24 |
Finished | Jul 01 05:00:05 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-7a666454-cb4d-4cf0-be45-5af03c00553b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696350790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.2696350790 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.3652587036 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 8312063192 ps |
CPU time | 72 seconds |
Started | Jul 01 05:00:03 PM PDT 24 |
Finished | Jul 01 05:01:18 PM PDT 24 |
Peak memory | 248860 kb |
Host | smart-3b309384-29bf-458e-b1e4-0af0091ee3d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652587036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3652587036 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.3622099632 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 240358568 ps |
CPU time | 15.17 seconds |
Started | Jul 01 05:00:01 PM PDT 24 |
Finished | Jul 01 05:00:19 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-7863a256-fe59-4507-bf33-4ef4f16a0441 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622099632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3622099632 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.962562989 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 42836953404 ps |
CPU time | 1837.46 seconds |
Started | Jul 01 05:00:07 PM PDT 24 |
Finished | Jul 01 05:30:47 PM PDT 24 |
Peak memory | 376664 kb |
Host | smart-10e51571-b51f-4beb-97a5-96de68a0d48f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962562989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_stress_all.962562989 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3729244307 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 3948554294 ps |
CPU time | 277.97 seconds |
Started | Jul 01 05:00:07 PM PDT 24 |
Finished | Jul 01 05:04:46 PM PDT 24 |
Peak memory | 333156 kb |
Host | smart-2f1017a0-2e08-4efd-b39f-fdee7bce9459 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3729244307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3729244307 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2861421725 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 3005390275 ps |
CPU time | 151.63 seconds |
Started | Jul 01 05:00:02 PM PDT 24 |
Finished | Jul 01 05:02:36 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-2e9a72ca-212c-486f-b74f-d3ce55b8bfde |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861421725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.2861421725 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.134909000 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 255582806 ps |
CPU time | 88.15 seconds |
Started | Jul 01 05:00:02 PM PDT 24 |
Finished | Jul 01 05:01:33 PM PDT 24 |
Peak memory | 337824 kb |
Host | smart-511b22f2-0c17-4867-968f-0748d2c3cd73 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134909000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.134909000 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.4213842378 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 2071334115 ps |
CPU time | 738.48 seconds |
Started | Jul 01 05:00:06 PM PDT 24 |
Finished | Jul 01 05:12:26 PM PDT 24 |
Peak memory | 365460 kb |
Host | smart-076c8b4c-f4e2-42ad-99b8-544685bc6d93 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213842378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.4213842378 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.1165484384 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 37114957 ps |
CPU time | 0.65 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:00:21 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-f4145027-ffb9-41ff-9a2d-a668539230f4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165484384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1165484384 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.2338608800 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 7453724665 ps |
CPU time | 84.31 seconds |
Started | Jul 01 05:00:10 PM PDT 24 |
Finished | Jul 01 05:01:35 PM PDT 24 |
Peak memory | 203000 kb |
Host | smart-9a8df0d4-7fc7-4fbf-bbd2-198c6e7cc7f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338608800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .2338608800 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.1737717213 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 3687897576 ps |
CPU time | 357.72 seconds |
Started | Jul 01 05:00:08 PM PDT 24 |
Finished | Jul 01 05:06:08 PM PDT 24 |
Peak memory | 363500 kb |
Host | smart-b3db6de9-c81f-4379-92d2-dbb1d3fb14e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737717213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.1737717213 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.159260414 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 2680334436 ps |
CPU time | 8.42 seconds |
Started | Jul 01 05:00:08 PM PDT 24 |
Finished | Jul 01 05:00:18 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-79cb8610-2350-46f0-9897-bd794d9ea939 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159260414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc alation.159260414 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.3144880555 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 549889862 ps |
CPU time | 27.08 seconds |
Started | Jul 01 05:00:08 PM PDT 24 |
Finished | Jul 01 05:00:37 PM PDT 24 |
Peak memory | 278788 kb |
Host | smart-eceae21e-b06b-4ec1-adbd-9421e7b1af83 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144880555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.3144880555 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1485753196 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 125489759 ps |
CPU time | 4.22 seconds |
Started | Jul 01 05:00:12 PM PDT 24 |
Finished | Jul 01 05:00:17 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-296dda5f-c3ca-4a2d-8197-bd349485e301 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485753196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.1485753196 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.378475721 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 145786039 ps |
CPU time | 8.18 seconds |
Started | Jul 01 05:00:07 PM PDT 24 |
Finished | Jul 01 05:00:17 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-fdc30e44-4c8b-4604-9d6b-ba8348fb24c3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378475721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _mem_walk.378475721 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.3236551067 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 16437029495 ps |
CPU time | 697.74 seconds |
Started | Jul 01 05:00:07 PM PDT 24 |
Finished | Jul 01 05:11:46 PM PDT 24 |
Peak memory | 372720 kb |
Host | smart-96a7bebe-50ce-4a27-ac77-43dce984ea2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236551067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.3236551067 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.1217031902 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 467388436 ps |
CPU time | 82.32 seconds |
Started | Jul 01 05:00:11 PM PDT 24 |
Finished | Jul 01 05:01:35 PM PDT 24 |
Peak memory | 339784 kb |
Host | smart-daf62907-ed98-49e7-b1ed-d3896f31f05f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217031902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.1217031902 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3537033644 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 45339560595 ps |
CPU time | 338.89 seconds |
Started | Jul 01 05:00:12 PM PDT 24 |
Finished | Jul 01 05:05:52 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-4400eb7b-e150-4c81-93b9-ce9d15aedde7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537033644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.3537033644 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.3599339331 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 28130939 ps |
CPU time | 0.77 seconds |
Started | Jul 01 05:00:08 PM PDT 24 |
Finished | Jul 01 05:00:10 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-3d90718e-2643-45b5-8003-91e4bf6624e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599339331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3599339331 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.959206376 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 45143404587 ps |
CPU time | 667.81 seconds |
Started | Jul 01 05:00:08 PM PDT 24 |
Finished | Jul 01 05:11:18 PM PDT 24 |
Peak memory | 371520 kb |
Host | smart-fdbbef47-585c-4d36-bd7b-3ebcb93b1ed8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959206376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.959206376 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.1676711475 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 1665472365 ps |
CPU time | 8.34 seconds |
Started | Jul 01 05:00:05 PM PDT 24 |
Finished | Jul 01 05:00:16 PM PDT 24 |
Peak memory | 233104 kb |
Host | smart-a71a99f2-7631-4af3-8ab1-cd0963d2c4b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676711475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1676711475 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.2926680895 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 112564193837 ps |
CPU time | 1934.19 seconds |
Started | Jul 01 05:00:12 PM PDT 24 |
Finished | Jul 01 05:32:27 PM PDT 24 |
Peak memory | 376836 kb |
Host | smart-8b05bc0c-9342-4322-98ba-042fafbdcd68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926680895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.2926680895 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2946562962 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 4516994845 ps |
CPU time | 64.56 seconds |
Started | Jul 01 05:00:08 PM PDT 24 |
Finished | Jul 01 05:01:14 PM PDT 24 |
Peak memory | 297976 kb |
Host | smart-3030e7fa-972d-4e20-894f-6219db8d36a9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2946562962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2946562962 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2485714073 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 1921685344 ps |
CPU time | 213.16 seconds |
Started | Jul 01 05:00:10 PM PDT 24 |
Finished | Jul 01 05:03:44 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-27a27b4e-75d3-4c3e-8ba0-d28a69163e25 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485714073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.2485714073 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.114235223 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 76228361 ps |
CPU time | 6.85 seconds |
Started | Jul 01 05:00:08 PM PDT 24 |
Finished | Jul 01 05:00:17 PM PDT 24 |
Peak memory | 236544 kb |
Host | smart-308af8c5-5af4-477a-bf53-e46925b82fbd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114235223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.114235223 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3229962600 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 2438749955 ps |
CPU time | 789.07 seconds |
Started | Jul 01 05:00:21 PM PDT 24 |
Finished | Jul 01 05:13:32 PM PDT 24 |
Peak memory | 374812 kb |
Host | smart-cf86ee30-9bb7-47a1-95cf-80afbf385601 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229962600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.3229962600 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.264977743 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 20891442 ps |
CPU time | 0.63 seconds |
Started | Jul 01 05:00:18 PM PDT 24 |
Finished | Jul 01 05:00:21 PM PDT 24 |
Peak memory | 202312 kb |
Host | smart-a5edf3d3-c4eb-4518-bbba-7d5a2df3f402 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264977743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.264977743 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.4021405523 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 6395420348 ps |
CPU time | 38.97 seconds |
Started | Jul 01 05:00:18 PM PDT 24 |
Finished | Jul 01 05:00:58 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-0525d1c8-3177-4395-ba21-c4a36b55673f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021405523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .4021405523 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.2675612099 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 12066133357 ps |
CPU time | 51.31 seconds |
Started | Jul 01 05:00:17 PM PDT 24 |
Finished | Jul 01 05:01:10 PM PDT 24 |
Peak memory | 241388 kb |
Host | smart-ae60a249-6ad5-4934-9b00-3272ee458beb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675612099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.2675612099 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.2197815717 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 999294236 ps |
CPU time | 4.65 seconds |
Started | Jul 01 05:00:18 PM PDT 24 |
Finished | Jul 01 05:00:24 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-cc479130-768b-4726-86fc-72ea42263a39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197815717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.2197815717 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.708203516 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 60260603 ps |
CPU time | 4.28 seconds |
Started | Jul 01 05:00:17 PM PDT 24 |
Finished | Jul 01 05:00:23 PM PDT 24 |
Peak memory | 225576 kb |
Host | smart-e698c71d-ac27-47db-a5df-2fe0dbbcb082 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708203516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.sram_ctrl_max_throughput.708203516 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1794969497 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 874093782 ps |
CPU time | 5.68 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:00:27 PM PDT 24 |
Peak memory | 210912 kb |
Host | smart-525f159d-2038-4ba5-afa4-6c310c437aa7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794969497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.1794969497 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.790097801 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 1870867770 ps |
CPU time | 6.72 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:00:27 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-103b09e9-da81-48ac-84ca-78b01310f327 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790097801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _mem_walk.790097801 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.177227674 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 87311241595 ps |
CPU time | 938.05 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:15:59 PM PDT 24 |
Peak memory | 361972 kb |
Host | smart-9c01c5e7-af4f-4601-b7f2-6dc33abf1145 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177227674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip le_keys.177227674 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.426205290 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 147627368 ps |
CPU time | 1.29 seconds |
Started | Jul 01 05:00:20 PM PDT 24 |
Finished | Jul 01 05:00:24 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-a4c5eaf6-2838-415c-a111-ba1a5bce64ce |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426205290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s ram_ctrl_partial_access.426205290 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4229757656 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 16211223031 ps |
CPU time | 382.26 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:06:44 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-926d527d-2943-499b-8ca2-df709f80dd9b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229757656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.4229757656 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.158861161 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 45916765 ps |
CPU time | 0.78 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:00:22 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-6646969f-fd47-4cd7-91af-ac41d050e316 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158861161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.158861161 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.3644034453 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 19389464529 ps |
CPU time | 920.55 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:15:42 PM PDT 24 |
Peak memory | 369596 kb |
Host | smart-2345113c-9040-4004-806a-c437bc80c47c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644034453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3644034453 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.997725495 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 214619474 ps |
CPU time | 12.26 seconds |
Started | Jul 01 05:00:17 PM PDT 24 |
Finished | Jul 01 05:00:31 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-31dd140b-c7e0-4549-9246-657d05206ee2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997725495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.997725495 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.2929844435 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 34181499380 ps |
CPU time | 889.64 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:15:11 PM PDT 24 |
Peak memory | 382676 kb |
Host | smart-afaaa97e-8f52-45fd-a268-ed26c421608e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929844435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.2929844435 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3027435703 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 12890296080 ps |
CPU time | 88.31 seconds |
Started | Jul 01 05:00:22 PM PDT 24 |
Finished | Jul 01 05:01:53 PM PDT 24 |
Peak memory | 312828 kb |
Host | smart-81f1566e-e196-4f3b-bbda-01b05a6c6672 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3027435703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3027435703 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.253421141 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 24823506166 ps |
CPU time | 218.58 seconds |
Started | Jul 01 05:00:18 PM PDT 24 |
Finished | Jul 01 05:03:58 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-a3dc3678-2464-445f-9b07-956da4c2e812 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253421141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_stress_pipeline.253421141 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.190645974 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 55895858 ps |
CPU time | 5.4 seconds |
Started | Jul 01 05:00:17 PM PDT 24 |
Finished | Jul 01 05:00:24 PM PDT 24 |
Peak memory | 227508 kb |
Host | smart-dc0790a2-f187-44e9-9996-c88d2def2b98 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190645974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.190645974 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.4154581721 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 31040622812 ps |
CPU time | 1704.88 seconds |
Started | Jul 01 05:00:25 PM PDT 24 |
Finished | Jul 01 05:28:52 PM PDT 24 |
Peak memory | 375808 kb |
Host | smart-7b931764-2433-40a1-b93e-55ab617d1d0b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154581721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.4154581721 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.934438284 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 15456378 ps |
CPU time | 0.68 seconds |
Started | Jul 01 05:00:25 PM PDT 24 |
Finished | Jul 01 05:00:29 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-3dfd38cc-781f-4be0-8347-05628b7c9c4d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934438284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.934438284 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.1564832066 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 481462358 ps |
CPU time | 33.64 seconds |
Started | Jul 01 05:00:20 PM PDT 24 |
Finished | Jul 01 05:00:56 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-1360fa5a-0acb-4d84-a11c-ba2f92811d46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564832066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .1564832066 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.3188578104 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 6183585562 ps |
CPU time | 491.72 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:08:48 PM PDT 24 |
Peak memory | 373276 kb |
Host | smart-aaff1d8a-18e0-43c7-9700-f880ace6d9ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188578104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.3188578104 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.326745234 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 1414387826 ps |
CPU time | 5.55 seconds |
Started | Jul 01 05:00:26 PM PDT 24 |
Finished | Jul 01 05:00:35 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-9dbd87ba-5cc8-402c-935f-a01ab6cd7f54 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326745234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_esc alation.326745234 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.1233785918 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 179343413 ps |
CPU time | 6.07 seconds |
Started | Jul 01 05:00:21 PM PDT 24 |
Finished | Jul 01 05:00:29 PM PDT 24 |
Peak memory | 235440 kb |
Host | smart-ff521aad-ee25-4a33-b56c-a00974fb0006 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233785918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.1233785918 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3716447848 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 102904923 ps |
CPU time | 3.41 seconds |
Started | Jul 01 05:00:25 PM PDT 24 |
Finished | Jul 01 05:00:31 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-4641f6cd-348e-45de-b37d-8b376fe8c073 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716447848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.3716447848 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.3740356432 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 139412366 ps |
CPU time | 4.5 seconds |
Started | Jul 01 05:00:26 PM PDT 24 |
Finished | Jul 01 05:00:34 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-fd283188-f01d-4a9d-81d6-e3af772b9b8a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740356432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.3740356432 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.3885611343 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 14654662139 ps |
CPU time | 387.63 seconds |
Started | Jul 01 05:00:18 PM PDT 24 |
Finished | Jul 01 05:06:48 PM PDT 24 |
Peak memory | 344064 kb |
Host | smart-f9121181-8fc5-4a11-b599-cd7a064189ea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885611343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.3885611343 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.559259462 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 756017417 ps |
CPU time | 123.34 seconds |
Started | Jul 01 05:00:21 PM PDT 24 |
Finished | Jul 01 05:02:26 PM PDT 24 |
Peak memory | 369164 kb |
Host | smart-598a5d6a-6d5b-4a43-8a7a-ed6d19a0e2ee |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559259462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s ram_ctrl_partial_access.559259462 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4141124678 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 24294824346 ps |
CPU time | 470.14 seconds |
Started | Jul 01 05:00:22 PM PDT 24 |
Finished | Jul 01 05:08:15 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-b07a385a-d27b-40ff-a2f4-4399eadce42d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141124678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.4141124678 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.1777043647 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 81468186 ps |
CPU time | 0.74 seconds |
Started | Jul 01 05:00:27 PM PDT 24 |
Finished | Jul 01 05:00:30 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-76512feb-a44f-47ef-9436-dad3721a7bfe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777043647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1777043647 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.3811132516 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 34711429533 ps |
CPU time | 862.21 seconds |
Started | Jul 01 05:00:24 PM PDT 24 |
Finished | Jul 01 05:14:49 PM PDT 24 |
Peak memory | 356528 kb |
Host | smart-faca5c14-2fd9-470f-821b-c2b7833454f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811132516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3811132516 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.1501602918 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 338650095 ps |
CPU time | 7.37 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:00:28 PM PDT 24 |
Peak memory | 227920 kb |
Host | smart-ae8b870d-3321-4c34-9ef7-d7a61f474aec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501602918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1501602918 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.4167399164 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 23673539639 ps |
CPU time | 7752.13 seconds |
Started | Jul 01 05:00:25 PM PDT 24 |
Finished | Jul 01 07:09:40 PM PDT 24 |
Peak memory | 378880 kb |
Host | smart-00e549fb-a66f-4f43-859d-0b0dce169981 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167399164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.4167399164 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3151012650 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 1022534296 ps |
CPU time | 21.08 seconds |
Started | Jul 01 05:00:29 PM PDT 24 |
Finished | Jul 01 05:00:52 PM PDT 24 |
Peak memory | 211260 kb |
Host | smart-4d5a33c9-b0e1-40c1-9f29-9185a0bac228 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3151012650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3151012650 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.3991836348 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 1531901039 ps |
CPU time | 148.24 seconds |
Started | Jul 01 05:00:19 PM PDT 24 |
Finished | Jul 01 05:02:50 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-26653c88-8357-428a-a280-7f5ec9e3c629 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991836348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.3991836348 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1476878866 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 2195652128 ps |
CPU time | 48.31 seconds |
Started | Jul 01 05:00:24 PM PDT 24 |
Finished | Jul 01 05:01:15 PM PDT 24 |
Peak memory | 318368 kb |
Host | smart-2e41f69a-8269-4a1c-b8bf-23096a31f8d6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476878866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1476878866 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3172918010 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 3599772426 ps |
CPU time | 956.44 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:14:22 PM PDT 24 |
Peak memory | 371708 kb |
Host | smart-db713119-b241-4c46-aae5-46cdd39c382a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172918010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.3172918010 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.1080680746 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 23787699 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:58:33 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-d5711933-332f-40c0-9f54-5534e65fa667 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080680746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.1080680746 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.3711480148 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 12689466261 ps |
CPU time | 45.6 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 04:59:10 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-e036d628-d63a-4b07-b7ef-40733eab5840 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711480148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 3711480148 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.1441552517 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 32152047419 ps |
CPU time | 755.36 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 05:11:03 PM PDT 24 |
Peak memory | 363452 kb |
Host | smart-e92a5562-8468-44b0-8bc6-4d90886537f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441552517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.1441552517 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.3845574985 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 499200449 ps |
CPU time | 5.58 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 04:58:31 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-fd0d24ae-5384-4868-a99b-9aba1cc6689f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845574985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.3845574985 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.1694701059 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 93121277 ps |
CPU time | 46.06 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 04:59:13 PM PDT 24 |
Peak memory | 300876 kb |
Host | smart-bea3c5d6-d554-4114-a5b9-64dcdfca63a1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694701059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.1694701059 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.412288265 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 46918574 ps |
CPU time | 2.69 seconds |
Started | Jul 01 04:58:20 PM PDT 24 |
Finished | Jul 01 04:58:26 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-c5866c27-4237-4a15-a967-91302a86a85e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412288265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. sram_ctrl_mem_partial_access.412288265 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.985305112 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 237236352 ps |
CPU time | 5.84 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:58:38 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-6a3dc14d-81c6-4445-8bde-79dd36f8b09e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985305112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ mem_walk.985305112 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.1831669487 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 63403430259 ps |
CPU time | 1239.27 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:19:05 PM PDT 24 |
Peak memory | 368592 kb |
Host | smart-48da8556-aef6-482c-8163-a38f335d30eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831669487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.1831669487 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.1284573383 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 1503457266 ps |
CPU time | 14.82 seconds |
Started | Jul 01 04:58:20 PM PDT 24 |
Finished | Jul 01 04:58:37 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-46985fc1-c944-414e-a6f3-040bda5ece4f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284573383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.1284573383 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2129202118 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 3665677105 ps |
CPU time | 260.82 seconds |
Started | Jul 01 04:58:19 PM PDT 24 |
Finished | Jul 01 05:02:42 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-0b3f9b8f-c5ce-4055-8727-18ea88c9ffa2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129202118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.2129202118 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.137584503 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 54935167 ps |
CPU time | 0.76 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 04:58:28 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-60ca1da6-c5de-4ce7-a2b1-d901c8946f39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137584503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.137584503 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.3072444758 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 17282393923 ps |
CPU time | 549.56 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 05:07:37 PM PDT 24 |
Peak memory | 365480 kb |
Host | smart-8da5d78e-f242-43c1-af98-eb0939e885dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072444758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3072444758 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.742231165 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 203017044 ps |
CPU time | 2.86 seconds |
Started | Jul 01 04:58:19 PM PDT 24 |
Finished | Jul 01 04:58:24 PM PDT 24 |
Peak memory | 222012 kb |
Host | smart-1d3b571d-acfb-42fc-aa74-3f07d588ce48 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742231165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_sec_cm.742231165 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.2754219605 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 325015803 ps |
CPU time | 18.37 seconds |
Started | Jul 01 04:58:19 PM PDT 24 |
Finished | Jul 01 04:58:39 PM PDT 24 |
Peak memory | 265588 kb |
Host | smart-ca93a305-5ace-4a63-9286-39bbc31e9881 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754219605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2754219605 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.2859487842 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 8233870244 ps |
CPU time | 2992.5 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:48:18 PM PDT 24 |
Peak memory | 382916 kb |
Host | smart-3accaee9-64ca-4e80-b9fc-b5574d35d8d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859487842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.2859487842 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2285072654 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 2783540512 ps |
CPU time | 335.61 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:04:01 PM PDT 24 |
Peak memory | 366644 kb |
Host | smart-a916585a-aa79-4b47-a306-9c7a1d3a72c2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2285072654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2285072654 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2872639494 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1731957030 ps |
CPU time | 136.72 seconds |
Started | Jul 01 04:58:20 PM PDT 24 |
Finished | Jul 01 05:00:38 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-25a03436-636f-49b3-bf7f-84f023e837c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872639494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.2872639494 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3833952840 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 664388212 ps |
CPU time | 111.01 seconds |
Started | Jul 01 04:58:25 PM PDT 24 |
Finished | Jul 01 05:00:22 PM PDT 24 |
Peak memory | 365644 kb |
Host | smart-cb35bf5a-ad82-43c7-b0ab-e5ec85185780 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833952840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3833952840 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.154715365 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 8546320439 ps |
CPU time | 909.62 seconds |
Started | Jul 01 05:00:26 PM PDT 24 |
Finished | Jul 01 05:15:38 PM PDT 24 |
Peak memory | 374720 kb |
Host | smart-6196bff9-3835-4199-880c-f2ae38b20697 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154715365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 40.sram_ctrl_access_during_key_req.154715365 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.146381938 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 19641177 ps |
CPU time | 0.68 seconds |
Started | Jul 01 05:00:32 PM PDT 24 |
Finished | Jul 01 05:00:35 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-7358b386-932e-45ae-b0f7-8991d1e4c7bb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146381938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.146381938 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.1983024272 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 3651682153 ps |
CPU time | 59.31 seconds |
Started | Jul 01 05:00:25 PM PDT 24 |
Finished | Jul 01 05:01:27 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-4dafef8c-70aa-44aa-b424-f523720d6bf1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983024272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .1983024272 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.1109847770 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 8935946359 ps |
CPU time | 97.53 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:02:13 PM PDT 24 |
Peak memory | 328628 kb |
Host | smart-79c40d3c-251d-487a-99e5-c7d4ee562829 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109847770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.1109847770 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.2868059233 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 955549557 ps |
CPU time | 7.25 seconds |
Started | Jul 01 05:00:25 PM PDT 24 |
Finished | Jul 01 05:00:35 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-dad2317b-1aac-4f6b-845c-da1d516241ea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868059233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.2868059233 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.4070242211 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 341028123 ps |
CPU time | 28.23 seconds |
Started | Jul 01 05:00:30 PM PDT 24 |
Finished | Jul 01 05:01:00 PM PDT 24 |
Peak memory | 288804 kb |
Host | smart-9f1bac85-d6bc-4857-97e8-b02815154a10 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070242211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.4070242211 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2351048717 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 484454258 ps |
CPU time | 3.25 seconds |
Started | Jul 01 05:00:25 PM PDT 24 |
Finished | Jul 01 05:00:31 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-ba449333-841b-4dbb-b967-7d7fbf099e4e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351048717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.2351048717 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.2675943484 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 239577759 ps |
CPU time | 5.81 seconds |
Started | Jul 01 05:00:32 PM PDT 24 |
Finished | Jul 01 05:00:40 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-4dd84234-85d7-47d0-9e00-97a2b3c92c9d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675943484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.2675943484 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.1131689678 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 2053000128 ps |
CPU time | 601.81 seconds |
Started | Jul 01 05:00:26 PM PDT 24 |
Finished | Jul 01 05:10:31 PM PDT 24 |
Peak memory | 373660 kb |
Host | smart-e8391cec-a112-42d6-930f-a96f5604cda2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131689678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.1131689678 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.615349182 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 3576164620 ps |
CPU time | 19.5 seconds |
Started | Jul 01 05:00:23 PM PDT 24 |
Finished | Jul 01 05:00:45 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-69b0554e-0304-479c-ae56-2aff30384268 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615349182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s ram_ctrl_partial_access.615349182 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1492055992 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 65704329469 ps |
CPU time | 302.39 seconds |
Started | Jul 01 05:00:24 PM PDT 24 |
Finished | Jul 01 05:05:29 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-21bc83d2-5ede-4fd2-b51c-426856b15cc6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492055992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.1492055992 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.3507665311 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 28852425 ps |
CPU time | 0.77 seconds |
Started | Jul 01 05:00:25 PM PDT 24 |
Finished | Jul 01 05:00:29 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-aa2e36b6-643e-4bf0-9075-232a409045f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507665311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3507665311 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.4116189030 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 27075429318 ps |
CPU time | 887.13 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:15:23 PM PDT 24 |
Peak memory | 372740 kb |
Host | smart-c0fb791b-6d80-41e0-9920-3f89b807ad3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116189030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.4116189030 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.2621628207 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 2499506734 ps |
CPU time | 10.55 seconds |
Started | Jul 01 05:00:27 PM PDT 24 |
Finished | Jul 01 05:00:40 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-d48376d2-3cda-4759-8e3d-2b914ff61c8f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621628207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2621628207 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.99876230 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 121507911242 ps |
CPU time | 2510.78 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:42:26 PM PDT 24 |
Peak memory | 382928 kb |
Host | smart-94b3b752-81e6-49c1-ab8f-fae201449386 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99876230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.sram_ctrl_stress_all.99876230 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1316405660 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 850441593 ps |
CPU time | 20.04 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:00:56 PM PDT 24 |
Peak memory | 252428 kb |
Host | smart-ea2df04f-3f70-4239-8342-f15441756eca |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1316405660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1316405660 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.929591251 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 2142173473 ps |
CPU time | 197.57 seconds |
Started | Jul 01 05:00:26 PM PDT 24 |
Finished | Jul 01 05:03:46 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-baabd573-dafd-4451-96cc-0181ad90c5f8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929591251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sram_ctrl_stress_pipeline.929591251 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.202357920 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 111595904 ps |
CPU time | 0.87 seconds |
Started | Jul 01 05:00:30 PM PDT 24 |
Finished | Jul 01 05:00:33 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-94f6e545-fc17-419f-809e-8d7c4a5e5135 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202357920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_throughput_w_partial_write.202357920 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1912716108 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 1412800528 ps |
CPU time | 234.24 seconds |
Started | Jul 01 05:00:34 PM PDT 24 |
Finished | Jul 01 05:04:31 PM PDT 24 |
Peak memory | 347708 kb |
Host | smart-120a5d05-e1da-4486-ba64-54683d8f66f9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912716108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.1912716108 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.267320747 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 64380489 ps |
CPU time | 0.69 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:00:36 PM PDT 24 |
Peak memory | 202624 kb |
Host | smart-446663e1-39d1-4ca1-99c2-6d0e9a624752 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267320747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.267320747 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.1380926703 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 3467248107 ps |
CPU time | 75.22 seconds |
Started | Jul 01 05:00:31 PM PDT 24 |
Finished | Jul 01 05:01:48 PM PDT 24 |
Peak memory | 203008 kb |
Host | smart-b9439a47-4187-4c06-8cb2-a4e82ea50f11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380926703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .1380926703 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.1684284483 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 24143013289 ps |
CPU time | 745.5 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:13:01 PM PDT 24 |
Peak memory | 365408 kb |
Host | smart-bb003d5e-b2bb-42be-8297-072dafa42859 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684284483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.1684284483 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.2123664201 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 722312400 ps |
CPU time | 7.95 seconds |
Started | Jul 01 05:00:32 PM PDT 24 |
Finished | Jul 01 05:00:43 PM PDT 24 |
Peak memory | 211236 kb |
Host | smart-4df2ab5a-2318-442a-a07c-8c03825e8da5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123664201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.2123664201 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.4243367894 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 106162522 ps |
CPU time | 5.3 seconds |
Started | Jul 01 05:00:34 PM PDT 24 |
Finished | Jul 01 05:00:42 PM PDT 24 |
Peak memory | 227164 kb |
Host | smart-f3e8f1cc-a7bc-44b6-9442-982864c7ffb2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243367894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.4243367894 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1664617688 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 330388509 ps |
CPU time | 3.32 seconds |
Started | Jul 01 05:00:34 PM PDT 24 |
Finished | Jul 01 05:00:40 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-23c023cd-5005-403d-aa0c-dd774d8f1a86 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664617688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.1664617688 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.4100992285 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 688910753 ps |
CPU time | 11.83 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:00:47 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-0fa884a7-3da8-4d36-9900-b4e7e6664a3a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100992285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.4100992285 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.972719144 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 14842793361 ps |
CPU time | 1384.15 seconds |
Started | Jul 01 05:00:25 PM PDT 24 |
Finished | Jul 01 05:23:32 PM PDT 24 |
Peak memory | 374668 kb |
Host | smart-76b381a9-8e45-4441-821b-067036304bbb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972719144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multip le_keys.972719144 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.435327657 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 313721267 ps |
CPU time | 13.15 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:00:49 PM PDT 24 |
Peak memory | 250972 kb |
Host | smart-2ad65cd4-8fdf-4c7d-9f8c-fae416e81459 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435327657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s ram_ctrl_partial_access.435327657 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2289723437 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 62356595344 ps |
CPU time | 442.83 seconds |
Started | Jul 01 05:00:32 PM PDT 24 |
Finished | Jul 01 05:07:56 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-1adb12d3-c60c-44a8-88a4-b7013598a152 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289723437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.2289723437 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.1791405150 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 47822936 ps |
CPU time | 0.77 seconds |
Started | Jul 01 05:00:34 PM PDT 24 |
Finished | Jul 01 05:00:37 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-f6ac6606-ea4f-446c-9f37-426fd8b1f3a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791405150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1791405150 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.565850897 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 8259283530 ps |
CPU time | 293.12 seconds |
Started | Jul 01 05:00:35 PM PDT 24 |
Finished | Jul 01 05:05:30 PM PDT 24 |
Peak memory | 366644 kb |
Host | smart-15e2e1dc-8d49-4eb9-9389-3d8cdb3c7356 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565850897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.565850897 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.2395048018 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 779480780 ps |
CPU time | 8.79 seconds |
Started | Jul 01 05:00:24 PM PDT 24 |
Finished | Jul 01 05:00:35 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-eb39c85e-0371-411a-b232-36d05a82e8b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395048018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2395048018 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.1034429461 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 137255886727 ps |
CPU time | 3833.42 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 06:04:29 PM PDT 24 |
Peak memory | 372712 kb |
Host | smart-802b21a8-70b2-424c-bc71-69ea8ec13e95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034429461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.1034429461 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2350740159 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 3356200067 ps |
CPU time | 48.6 seconds |
Started | Jul 01 05:00:34 PM PDT 24 |
Finished | Jul 01 05:01:25 PM PDT 24 |
Peak memory | 234080 kb |
Host | smart-d06a8f49-ef68-4945-a91a-82abcfb41fd5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2350740159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2350740159 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.1819689841 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 3834549524 ps |
CPU time | 354.05 seconds |
Started | Jul 01 05:00:35 PM PDT 24 |
Finished | Jul 01 05:06:31 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-bc95c179-442f-4479-8e51-3a123a7c34be |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819689841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.1819689841 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.4181070432 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 428439390 ps |
CPU time | 47.64 seconds |
Started | Jul 01 05:00:33 PM PDT 24 |
Finished | Jul 01 05:01:23 PM PDT 24 |
Peak memory | 295836 kb |
Host | smart-0bbcc75f-8152-45a3-a7ea-564959b6969f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181070432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.4181070432 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.778068315 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 4578051471 ps |
CPU time | 1748.5 seconds |
Started | Jul 01 05:00:44 PM PDT 24 |
Finished | Jul 01 05:29:54 PM PDT 24 |
Peak memory | 373608 kb |
Host | smart-df6b2215-0bb8-4567-b3d3-1c30614284d2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778068315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 42.sram_ctrl_access_during_key_req.778068315 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.1678572192 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 38910873 ps |
CPU time | 0.65 seconds |
Started | Jul 01 05:00:42 PM PDT 24 |
Finished | Jul 01 05:00:44 PM PDT 24 |
Peak memory | 202308 kb |
Host | smart-3249cd47-1e55-416c-903b-b6cac6f990ed |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678572192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.1678572192 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.4214695335 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 19186677456 ps |
CPU time | 85.81 seconds |
Started | Jul 01 05:00:45 PM PDT 24 |
Finished | Jul 01 05:02:12 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-613fff6f-c9f8-4426-a6f2-6865ec24f0ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214695335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .4214695335 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.198110146 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 2180774884 ps |
CPU time | 433.61 seconds |
Started | Jul 01 05:00:41 PM PDT 24 |
Finished | Jul 01 05:07:57 PM PDT 24 |
Peak memory | 367096 kb |
Host | smart-11384efe-3db6-4daa-9a91-9a244b36f7a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198110146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executabl e.198110146 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.311786530 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 2260457478 ps |
CPU time | 8.75 seconds |
Started | Jul 01 05:00:43 PM PDT 24 |
Finished | Jul 01 05:00:53 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-b2f099d1-99ce-4553-ace7-83acfdc060f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311786530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc alation.311786530 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.212091737 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 277657818 ps |
CPU time | 121.98 seconds |
Started | Jul 01 05:00:43 PM PDT 24 |
Finished | Jul 01 05:02:47 PM PDT 24 |
Peak memory | 371148 kb |
Host | smart-74312e6d-7fdf-497e-9b55-c73a496929d3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212091737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.sram_ctrl_max_throughput.212091737 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2158014914 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 179597183 ps |
CPU time | 5.41 seconds |
Started | Jul 01 05:00:41 PM PDT 24 |
Finished | Jul 01 05:00:47 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-1c103a61-098f-44a0-a690-5c2a0f296797 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158014914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.2158014914 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.3121423561 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 768372355 ps |
CPU time | 4.86 seconds |
Started | Jul 01 05:00:41 PM PDT 24 |
Finished | Jul 01 05:00:47 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-7e6bb515-5756-4a21-a4a9-9a23b03f2582 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121423561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.3121423561 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.323030819 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 14087645581 ps |
CPU time | 1089.7 seconds |
Started | Jul 01 05:00:42 PM PDT 24 |
Finished | Jul 01 05:18:53 PM PDT 24 |
Peak memory | 370456 kb |
Host | smart-aee69683-c814-4a1a-8830-ef7a552c98d9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323030819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip le_keys.323030819 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.4008333881 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 326220839 ps |
CPU time | 15.3 seconds |
Started | Jul 01 05:00:43 PM PDT 24 |
Finished | Jul 01 05:01:00 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-7eeea6a0-e68b-4e16-94e0-627b489403ab |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008333881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.4008333881 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1643825009 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 45134574766 ps |
CPU time | 226.21 seconds |
Started | Jul 01 05:00:42 PM PDT 24 |
Finished | Jul 01 05:04:30 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-a7d2e578-8a49-4955-bb47-d7b0e53bd18d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643825009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.1643825009 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.803141655 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 48419839 ps |
CPU time | 0.77 seconds |
Started | Jul 01 05:00:42 PM PDT 24 |
Finished | Jul 01 05:00:44 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-cb516800-dc91-41ae-8b72-bbe8eee12233 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803141655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.803141655 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.4161541639 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 16100934819 ps |
CPU time | 1513.23 seconds |
Started | Jul 01 05:00:45 PM PDT 24 |
Finished | Jul 01 05:26:00 PM PDT 24 |
Peak memory | 375808 kb |
Host | smart-1259a93d-7f5e-4161-8690-1ceaaacd4cda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161541639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.4161541639 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.2004459526 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 750520320 ps |
CPU time | 17.48 seconds |
Started | Jul 01 05:00:34 PM PDT 24 |
Finished | Jul 01 05:00:54 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-41890d91-8ddf-4335-acc8-0bc23a19f6a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004459526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2004459526 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3944631063 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 2683527003 ps |
CPU time | 208 seconds |
Started | Jul 01 05:00:42 PM PDT 24 |
Finished | Jul 01 05:04:12 PM PDT 24 |
Peak memory | 347280 kb |
Host | smart-483ea767-c685-4d79-a3ad-2f4cf9443d73 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3944631063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3944631063 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3384180236 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 8792079191 ps |
CPU time | 204.36 seconds |
Started | Jul 01 05:00:43 PM PDT 24 |
Finished | Jul 01 05:04:10 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-8320b882-4b44-419c-ad76-9ac10c96895c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384180236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.3384180236 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3939495586 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 171340291 ps |
CPU time | 2.65 seconds |
Started | Jul 01 05:00:44 PM PDT 24 |
Finished | Jul 01 05:00:48 PM PDT 24 |
Peak memory | 218520 kb |
Host | smart-91a1c393-c379-401c-9fcf-6aa7e71cd2ed |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939495586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.3939495586 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3444868566 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 3998379547 ps |
CPU time | 268.77 seconds |
Started | Jul 01 05:00:48 PM PDT 24 |
Finished | Jul 01 05:05:19 PM PDT 24 |
Peak memory | 373380 kb |
Host | smart-57985ffc-bacb-4ec1-9920-fa7f82ce76e9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444868566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.3444868566 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.3060498003 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 79188825 ps |
CPU time | 0.67 seconds |
Started | Jul 01 05:00:51 PM PDT 24 |
Finished | Jul 01 05:00:54 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-78184d25-9a58-400e-9d80-318b45080324 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060498003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.3060498003 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.1717616450 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 3511751768 ps |
CPU time | 63.82 seconds |
Started | Jul 01 05:00:51 PM PDT 24 |
Finished | Jul 01 05:01:57 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-83d61277-3c97-463e-a769-f687c35f0982 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717616450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .1717616450 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.2165876318 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 7458110659 ps |
CPU time | 352.58 seconds |
Started | Jul 01 05:00:49 PM PDT 24 |
Finished | Jul 01 05:06:44 PM PDT 24 |
Peak memory | 343052 kb |
Host | smart-2a1110be-508b-4dcd-bdf0-eb26cd3cc078 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165876318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.2165876318 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.186853127 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 650236264 ps |
CPU time | 7.97 seconds |
Started | Jul 01 05:00:52 PM PDT 24 |
Finished | Jul 01 05:01:02 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-e77b47bc-458a-411e-a51b-deb3eda766d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186853127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc alation.186853127 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.903681930 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 577205660 ps |
CPU time | 106.29 seconds |
Started | Jul 01 05:00:49 PM PDT 24 |
Finished | Jul 01 05:02:37 PM PDT 24 |
Peak memory | 363360 kb |
Host | smart-7c8f995c-73de-4616-a7c8-a51c20cb0bb3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903681930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.sram_ctrl_max_throughput.903681930 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3880217263 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 200796526 ps |
CPU time | 6.6 seconds |
Started | Jul 01 05:00:49 PM PDT 24 |
Finished | Jul 01 05:00:58 PM PDT 24 |
Peak memory | 211252 kb |
Host | smart-61315c47-8f0a-4ae9-af54-33b9c0f2aa98 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880217263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.3880217263 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.3542012008 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 4473024213 ps |
CPU time | 5.78 seconds |
Started | Jul 01 05:00:49 PM PDT 24 |
Finished | Jul 01 05:00:57 PM PDT 24 |
Peak memory | 211200 kb |
Host | smart-f6e58ae4-869c-43de-adeb-b9dca152506b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542012008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.3542012008 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.2912454737 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 4006143429 ps |
CPU time | 1710.01 seconds |
Started | Jul 01 05:00:43 PM PDT 24 |
Finished | Jul 01 05:29:15 PM PDT 24 |
Peak memory | 374952 kb |
Host | smart-f515e056-fce3-4b09-8715-7d0ecdbc8eee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912454737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2912454737 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.1457980367 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 354669297 ps |
CPU time | 16.03 seconds |
Started | Jul 01 05:00:50 PM PDT 24 |
Finished | Jul 01 05:01:08 PM PDT 24 |
Peak memory | 258196 kb |
Host | smart-bd96ad48-9a0b-45e4-810d-30861da04716 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457980367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.1457980367 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2579955270 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 20007217579 ps |
CPU time | 426.15 seconds |
Started | Jul 01 05:00:49 PM PDT 24 |
Finished | Jul 01 05:07:57 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-bb2c1714-9efa-4807-8e6e-fdd204a704d5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579955270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.2579955270 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.2092226677 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 84884812 ps |
CPU time | 0.75 seconds |
Started | Jul 01 05:00:49 PM PDT 24 |
Finished | Jul 01 05:00:52 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-3d498dbf-752f-4207-bb3a-5b4921921080 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092226677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.2092226677 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.1517367211 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 16839465610 ps |
CPU time | 762.11 seconds |
Started | Jul 01 05:00:50 PM PDT 24 |
Finished | Jul 01 05:13:34 PM PDT 24 |
Peak memory | 372708 kb |
Host | smart-50e51791-9a65-4132-b1d3-d4c9cd1c3bc8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517367211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1517367211 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.2597729379 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 622650376 ps |
CPU time | 72.29 seconds |
Started | Jul 01 05:00:42 PM PDT 24 |
Finished | Jul 01 05:01:55 PM PDT 24 |
Peak memory | 338548 kb |
Host | smart-79730e77-81d0-43b5-a3d0-85ddcf2bd543 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597729379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2597729379 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.113115769 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 16013121817 ps |
CPU time | 164.29 seconds |
Started | Jul 01 05:00:50 PM PDT 24 |
Finished | Jul 01 05:03:36 PM PDT 24 |
Peak memory | 302204 kb |
Host | smart-500aafb6-6eba-46e8-9c8e-89f18b1ff41f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113115769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_stress_all.113115769 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1031722623 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 3660041855 ps |
CPU time | 27.89 seconds |
Started | Jul 01 05:00:48 PM PDT 24 |
Finished | Jul 01 05:01:18 PM PDT 24 |
Peak memory | 212620 kb |
Host | smart-4bb8feac-5205-4fe9-b813-0717dd647055 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1031722623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1031722623 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1119810661 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 3502853944 ps |
CPU time | 331.73 seconds |
Started | Jul 01 05:00:50 PM PDT 24 |
Finished | Jul 01 05:06:24 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-021922d7-21f6-4f16-919c-1856a35c10d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119810661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.1119810661 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1071129832 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 292975587 ps |
CPU time | 128.53 seconds |
Started | Jul 01 05:00:50 PM PDT 24 |
Finished | Jul 01 05:03:00 PM PDT 24 |
Peak memory | 367632 kb |
Host | smart-1baa79ca-a28b-4485-b973-b18499158a03 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071129832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1071129832 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1184523349 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 13746045702 ps |
CPU time | 1179.6 seconds |
Started | Jul 01 05:01:00 PM PDT 24 |
Finished | Jul 01 05:20:43 PM PDT 24 |
Peak memory | 375364 kb |
Host | smart-cfbc0717-efe9-4c5c-afd5-e5ae96787c6d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184523349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.1184523349 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.2562182055 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 12697099 ps |
CPU time | 0.72 seconds |
Started | Jul 01 05:00:58 PM PDT 24 |
Finished | Jul 01 05:01:02 PM PDT 24 |
Peak memory | 202324 kb |
Host | smart-cf1105d8-0db5-4c11-8446-1ed3fbed5fcc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562182055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2562182055 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.2406826389 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 5048915180 ps |
CPU time | 69.61 seconds |
Started | Jul 01 05:00:48 PM PDT 24 |
Finished | Jul 01 05:02:00 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-1d39c22a-d600-4cc9-ada5-f5c04555db3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406826389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .2406826389 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.364603371 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 2249432067 ps |
CPU time | 364.14 seconds |
Started | Jul 01 05:00:59 PM PDT 24 |
Finished | Jul 01 05:07:07 PM PDT 24 |
Peak memory | 349172 kb |
Host | smart-4909a651-5942-4250-a4a1-b59032c196b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364603371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl e.364603371 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.2149457581 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 69203160 ps |
CPU time | 1.64 seconds |
Started | Jul 01 05:00:58 PM PDT 24 |
Finished | Jul 01 05:01:04 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-f54205a3-5dbd-41f6-aaf2-f444dea21283 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149457581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.2149457581 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.893240951 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 79991864 ps |
CPU time | 6.39 seconds |
Started | Jul 01 05:00:56 PM PDT 24 |
Finished | Jul 01 05:01:05 PM PDT 24 |
Peak memory | 235596 kb |
Host | smart-321a08f0-f90b-49f1-bfbd-e19abf5cc4df |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893240951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.sram_ctrl_max_throughput.893240951 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1499395115 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 494339186 ps |
CPU time | 3.49 seconds |
Started | Jul 01 05:00:57 PM PDT 24 |
Finished | Jul 01 05:01:04 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-461c6cab-faff-43bc-916d-7f32a2ce5e51 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499395115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.1499395115 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.1117199356 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 1931701552 ps |
CPU time | 10.17 seconds |
Started | Jul 01 05:00:58 PM PDT 24 |
Finished | Jul 01 05:01:11 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-5421c365-f180-4c9b-bafb-d2c7d81637bc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117199356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1117199356 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.884587034 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 13482784591 ps |
CPU time | 1474.75 seconds |
Started | Jul 01 05:00:50 PM PDT 24 |
Finished | Jul 01 05:25:27 PM PDT 24 |
Peak memory | 372288 kb |
Host | smart-dc115338-c907-4288-95e2-4774c806366a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884587034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multip le_keys.884587034 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.4217150389 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 258042798 ps |
CPU time | 14.37 seconds |
Started | Jul 01 05:00:58 PM PDT 24 |
Finished | Jul 01 05:01:15 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-a8bf5d29-96ba-4fb7-873c-4158db51f340 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217150389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.4217150389 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2908267491 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 17579033249 ps |
CPU time | 216.39 seconds |
Started | Jul 01 05:00:57 PM PDT 24 |
Finished | Jul 01 05:04:37 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-8910e3c0-75e9-409c-9d2a-ac31739cba93 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908267491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.2908267491 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.1032542241 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 29577687 ps |
CPU time | 0.75 seconds |
Started | Jul 01 05:00:57 PM PDT 24 |
Finished | Jul 01 05:01:01 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-707a8283-fe54-499c-adf9-f4786e740ff9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032542241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1032542241 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.3180565701 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 4081976551 ps |
CPU time | 385.44 seconds |
Started | Jul 01 05:00:58 PM PDT 24 |
Finished | Jul 01 05:07:27 PM PDT 24 |
Peak memory | 370504 kb |
Host | smart-f9ea67d8-1f5f-40d8-a1bd-a7ff0369bc0d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180565701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3180565701 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.3777657766 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 948424535 ps |
CPU time | 15.78 seconds |
Started | Jul 01 05:00:49 PM PDT 24 |
Finished | Jul 01 05:01:07 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-ab6d4cb4-b6a8-4bb9-b3a1-125dd2df3c10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777657766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3777657766 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.2324023929 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 17409707443 ps |
CPU time | 1791.97 seconds |
Started | Jul 01 05:00:58 PM PDT 24 |
Finished | Jul 01 05:30:54 PM PDT 24 |
Peak memory | 376824 kb |
Host | smart-a2586f64-3bbe-492a-8258-63556910bd2f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324023929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.2324023929 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1239122438 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 4607632123 ps |
CPU time | 234.2 seconds |
Started | Jul 01 05:00:48 PM PDT 24 |
Finished | Jul 01 05:04:44 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-453d1b5b-8cc8-4825-af71-ed063212837f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239122438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.1239122438 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1692006080 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 619597611 ps |
CPU time | 158.97 seconds |
Started | Jul 01 05:00:57 PM PDT 24 |
Finished | Jul 01 05:03:38 PM PDT 24 |
Peak memory | 369376 kb |
Host | smart-7126fdf0-71a5-4c43-93ba-828ad75d5bc7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692006080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1692006080 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1944477063 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 6631203048 ps |
CPU time | 1483.78 seconds |
Started | Jul 01 05:01:06 PM PDT 24 |
Finished | Jul 01 05:25:54 PM PDT 24 |
Peak memory | 371756 kb |
Host | smart-092b53eb-697a-40f3-b993-5e0d03f384ea |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944477063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.1944477063 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.3294242208 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 17277357 ps |
CPU time | 0.68 seconds |
Started | Jul 01 05:01:06 PM PDT 24 |
Finished | Jul 01 05:01:10 PM PDT 24 |
Peak memory | 202304 kb |
Host | smart-ebc913a7-fab0-4a91-8cab-4c9e865242d7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294242208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.3294242208 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.1447298259 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 3017690870 ps |
CPU time | 49.04 seconds |
Started | Jul 01 05:00:58 PM PDT 24 |
Finished | Jul 01 05:01:51 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-a229cf1b-3648-4cf4-9c64-bd0460d625cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447298259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .1447298259 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.669985355 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 13765875168 ps |
CPU time | 468.83 seconds |
Started | Jul 01 05:01:08 PM PDT 24 |
Finished | Jul 01 05:09:00 PM PDT 24 |
Peak memory | 374388 kb |
Host | smart-efe52de4-79ba-4af4-a19b-48b1298134ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669985355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executabl e.669985355 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.207882914 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 694762418 ps |
CPU time | 9.05 seconds |
Started | Jul 01 05:00:56 PM PDT 24 |
Finished | Jul 01 05:01:08 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-53988b38-8714-4640-a13a-9237a1343b6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207882914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esc alation.207882914 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.3752849959 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 400958755 ps |
CPU time | 64.45 seconds |
Started | Jul 01 05:00:58 PM PDT 24 |
Finished | Jul 01 05:02:05 PM PDT 24 |
Peak memory | 307084 kb |
Host | smart-409a8a85-3724-42b5-b370-6925be1910a8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752849959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.3752849959 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3158633655 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 657065974 ps |
CPU time | 3.14 seconds |
Started | Jul 01 05:01:05 PM PDT 24 |
Finished | Jul 01 05:01:12 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-a3077e22-684e-43cb-9c82-7b37e179c67e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158633655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.3158633655 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.3489505456 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 1467666732 ps |
CPU time | 5.62 seconds |
Started | Jul 01 05:01:04 PM PDT 24 |
Finished | Jul 01 05:01:13 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-59460206-01c4-4eff-a41a-d60cd78cb412 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489505456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.3489505456 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.2463045377 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 2854188823 ps |
CPU time | 951.36 seconds |
Started | Jul 01 05:00:59 PM PDT 24 |
Finished | Jul 01 05:16:54 PM PDT 24 |
Peak memory | 371640 kb |
Host | smart-41b3ad96-7f1c-49f3-a311-f28022f4af17 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463045377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.2463045377 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.2812391972 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 129571531 ps |
CPU time | 7.28 seconds |
Started | Jul 01 05:00:57 PM PDT 24 |
Finished | Jul 01 05:01:07 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-e767fe8a-99f5-4c82-a51e-27a8aa7b5cd1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812391972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.2812391972 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1966211114 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 2838299758 ps |
CPU time | 207.64 seconds |
Started | Jul 01 05:00:58 PM PDT 24 |
Finished | Jul 01 05:04:29 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-42f85709-c7b0-4dc7-ab31-81703eda063b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966211114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.1966211114 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.1636663057 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 51261356 ps |
CPU time | 0.79 seconds |
Started | Jul 01 05:01:04 PM PDT 24 |
Finished | Jul 01 05:01:08 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-c6ed24ee-bbbd-41e5-8ed7-3a730db8e21c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636663057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1636663057 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.1060991692 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 25943160748 ps |
CPU time | 856.64 seconds |
Started | Jul 01 05:01:07 PM PDT 24 |
Finished | Jul 01 05:15:27 PM PDT 24 |
Peak memory | 374496 kb |
Host | smart-0415225b-d2bd-4419-bea1-f1b84fc0cfd8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060991692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1060991692 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.1129845641 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 493845056 ps |
CPU time | 91 seconds |
Started | Jul 01 05:00:59 PM PDT 24 |
Finished | Jul 01 05:02:33 PM PDT 24 |
Peak memory | 351920 kb |
Host | smart-32ca071a-f0b8-4270-9469-1f34d3ae366e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129845641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1129845641 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.585718871 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 35713506945 ps |
CPU time | 2754.9 seconds |
Started | Jul 01 05:01:04 PM PDT 24 |
Finished | Jul 01 05:47:02 PM PDT 24 |
Peak memory | 375848 kb |
Host | smart-2960fc7b-b148-455e-a50d-48c306aade47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585718871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_stress_all.585718871 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2132054497 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 40133645294 ps |
CPU time | 415.75 seconds |
Started | Jul 01 05:00:55 PM PDT 24 |
Finished | Jul 01 05:07:53 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-37fc2cc4-d090-44c8-b923-07d3f8b673a5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132054497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2132054497 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3059597397 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 265911431 ps |
CPU time | 14.73 seconds |
Started | Jul 01 05:00:57 PM PDT 24 |
Finished | Jul 01 05:01:15 PM PDT 24 |
Peak memory | 257932 kb |
Host | smart-338ed638-be62-41af-aa7c-e65ba3931d7e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059597397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3059597397 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.987833930 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 3864741828 ps |
CPU time | 866.08 seconds |
Started | Jul 01 05:01:04 PM PDT 24 |
Finished | Jul 01 05:15:33 PM PDT 24 |
Peak memory | 366616 kb |
Host | smart-4be8c58a-4f6a-4e0b-8cc4-363ea29e237f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987833930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 46.sram_ctrl_access_during_key_req.987833930 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.3955876149 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 12219749 ps |
CPU time | 0.69 seconds |
Started | Jul 01 05:01:11 PM PDT 24 |
Finished | Jul 01 05:01:16 PM PDT 24 |
Peak memory | 202312 kb |
Host | smart-36ec9289-580d-43a4-981f-9cee01505272 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955876149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.3955876149 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.1311650186 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 11728731033 ps |
CPU time | 68.95 seconds |
Started | Jul 01 05:01:05 PM PDT 24 |
Finished | Jul 01 05:02:18 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-5de081ef-96c2-4b99-844a-62050b35e1c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311650186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .1311650186 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.2809149214 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 6722275601 ps |
CPU time | 730.58 seconds |
Started | Jul 01 05:01:04 PM PDT 24 |
Finished | Jul 01 05:13:18 PM PDT 24 |
Peak memory | 371768 kb |
Host | smart-e7207956-8b27-4599-a805-79f773168f27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809149214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.2809149214 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.347054881 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 831246327 ps |
CPU time | 7.8 seconds |
Started | Jul 01 05:01:11 PM PDT 24 |
Finished | Jul 01 05:01:22 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-cb9a9c5d-60e3-4d2e-be2d-9a8441fd0bf7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347054881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_esc alation.347054881 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.3171676788 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 71572887 ps |
CPU time | 13.39 seconds |
Started | Jul 01 05:01:05 PM PDT 24 |
Finished | Jul 01 05:01:22 PM PDT 24 |
Peak memory | 251836 kb |
Host | smart-bdb99bc4-1000-4902-a904-8845a045ebdf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171676788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.3171676788 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.52463997 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 763362555 ps |
CPU time | 6.04 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:01:24 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-5e4c32e3-042d-4c03-863a-1e1ac3b7f329 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52463997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_mem_partial_access.52463997 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.1359520653 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 295130843 ps |
CPU time | 6.22 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:01:24 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-5b6d5582-7078-45e9-b16d-96c5ee513ebb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359520653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.1359520653 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.988502446 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 11261512204 ps |
CPU time | 962.75 seconds |
Started | Jul 01 05:01:03 PM PDT 24 |
Finished | Jul 01 05:17:09 PM PDT 24 |
Peak memory | 370840 kb |
Host | smart-5c65e81a-c7d3-4730-b62f-e0452792fbab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988502446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip le_keys.988502446 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.3423359400 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 1035725895 ps |
CPU time | 100.13 seconds |
Started | Jul 01 05:01:07 PM PDT 24 |
Finished | Jul 01 05:02:50 PM PDT 24 |
Peak memory | 334272 kb |
Host | smart-6c0ab765-ea00-428b-9267-858b569b56c5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423359400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.3423359400 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2864354579 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 31313090926 ps |
CPU time | 329.71 seconds |
Started | Jul 01 05:01:04 PM PDT 24 |
Finished | Jul 01 05:06:36 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-a302fa58-cd26-4029-af48-7a36a53f8290 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864354579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.2864354579 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.1655661929 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 348484938 ps |
CPU time | 0.78 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:01:18 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-f6a8c3c2-c34b-4d41-b00f-4fdbe92264e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655661929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1655661929 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.1291060747 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 5104821968 ps |
CPU time | 51.65 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:02:10 PM PDT 24 |
Peak memory | 273768 kb |
Host | smart-55794762-45ed-4a4b-b6e0-72ceb8693733 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291060747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1291060747 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.4254067356 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 181791966 ps |
CPU time | 2.59 seconds |
Started | Jul 01 05:01:04 PM PDT 24 |
Finished | Jul 01 05:01:10 PM PDT 24 |
Peak memory | 208212 kb |
Host | smart-3cfd6f8e-bb90-4b6f-8197-a4234b4b28a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254067356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.4254067356 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.287798282 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 9676924017 ps |
CPU time | 3029.29 seconds |
Started | Jul 01 05:01:11 PM PDT 24 |
Finished | Jul 01 05:51:45 PM PDT 24 |
Peak memory | 374728 kb |
Host | smart-a743c744-ee0c-4398-8a43-339e1490678e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287798282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_stress_all.287798282 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1919392000 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 908396338 ps |
CPU time | 286.86 seconds |
Started | Jul 01 05:01:15 PM PDT 24 |
Finished | Jul 01 05:06:07 PM PDT 24 |
Peak memory | 361364 kb |
Host | smart-906f5a71-16cc-468b-a866-3b2c23b7923d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1919392000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1919392000 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.4289508860 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 3466672624 ps |
CPU time | 361.82 seconds |
Started | Jul 01 05:01:05 PM PDT 24 |
Finished | Jul 01 05:07:11 PM PDT 24 |
Peak memory | 203008 kb |
Host | smart-6d69aab1-2719-4ae5-9b9a-a26356fb4037 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289508860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.4289508860 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4239716633 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 58928843 ps |
CPU time | 4.78 seconds |
Started | Jul 01 05:01:08 PM PDT 24 |
Finished | Jul 01 05:01:16 PM PDT 24 |
Peak memory | 224992 kb |
Host | smart-7f6dfb91-20e1-4d7f-99ff-a52117cb8557 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239716633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.4239716633 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1675880786 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 3301421580 ps |
CPU time | 1154.78 seconds |
Started | Jul 01 05:01:15 PM PDT 24 |
Finished | Jul 01 05:20:34 PM PDT 24 |
Peak memory | 371432 kb |
Host | smart-83de524e-55ec-4db8-be13-dbb83404f1e7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675880786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.1675880786 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.2557517710 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 16954624 ps |
CPU time | 0.67 seconds |
Started | Jul 01 05:01:22 PM PDT 24 |
Finished | Jul 01 05:01:26 PM PDT 24 |
Peak memory | 202376 kb |
Host | smart-87299dcb-d554-4f17-ad9a-2adf6dbc20a8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557517710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.2557517710 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.2219439671 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 3234808783 ps |
CPU time | 57.65 seconds |
Started | Jul 01 05:01:12 PM PDT 24 |
Finished | Jul 01 05:02:14 PM PDT 24 |
Peak memory | 203008 kb |
Host | smart-9f715c1e-a89d-432a-b375-f584289d69e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219439671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .2219439671 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.2586954723 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 883951188 ps |
CPU time | 247.39 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:05:25 PM PDT 24 |
Peak memory | 373816 kb |
Host | smart-50a6e0ec-d7c8-49e8-b6ed-728231da0b90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586954723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.2586954723 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.1581431203 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 369227137 ps |
CPU time | 5.77 seconds |
Started | Jul 01 05:01:12 PM PDT 24 |
Finished | Jul 01 05:01:22 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-d378a608-c24d-4e9f-8bb0-841bd4ebe996 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581431203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.1581431203 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.2771222426 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 789173722 ps |
CPU time | 73.96 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:02:32 PM PDT 24 |
Peak memory | 337560 kb |
Host | smart-661c044c-9772-4626-8e65-69eff4f984ca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771222426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.2771222426 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2750312644 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 188631788 ps |
CPU time | 2.98 seconds |
Started | Jul 01 05:01:14 PM PDT 24 |
Finished | Jul 01 05:01:22 PM PDT 24 |
Peak memory | 211232 kb |
Host | smart-c9c90970-ebcb-4a7a-a030-0132e472f939 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750312644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.2750312644 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.62520700 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 2610393645 ps |
CPU time | 11.87 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:01:30 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-1731c72c-1593-4a76-8064-1a33b6238179 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62520700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ mem_walk.62520700 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.183803018 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 11028802262 ps |
CPU time | 911.01 seconds |
Started | Jul 01 05:01:14 PM PDT 24 |
Finished | Jul 01 05:16:30 PM PDT 24 |
Peak memory | 370592 kb |
Host | smart-61b74934-e854-40e1-a87c-705dc76f17d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183803018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip le_keys.183803018 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.2301462345 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 971644312 ps |
CPU time | 11.51 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:01:29 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-16568730-ca2b-4866-92c7-ddcd53326db1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301462345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2301462345 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.2490559085 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 29471269 ps |
CPU time | 0.77 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:01:18 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-e381b818-b6a4-4611-93ed-7ce942268906 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490559085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2490559085 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.814322779 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 4649750589 ps |
CPU time | 637.15 seconds |
Started | Jul 01 05:01:20 PM PDT 24 |
Finished | Jul 01 05:12:00 PM PDT 24 |
Peak memory | 354780 kb |
Host | smart-68c9d159-769f-4842-92ec-dbe7ab68f538 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814322779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.814322779 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.1582685716 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 540141897 ps |
CPU time | 18.21 seconds |
Started | Jul 01 05:01:14 PM PDT 24 |
Finished | Jul 01 05:01:37 PM PDT 24 |
Peak memory | 266224 kb |
Host | smart-c446fe01-c813-4557-bc9e-a20a66e0d779 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582685716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1582685716 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.311252143 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 7309778535 ps |
CPU time | 657.8 seconds |
Started | Jul 01 05:01:13 PM PDT 24 |
Finished | Jul 01 05:12:15 PM PDT 24 |
Peak memory | 368820 kb |
Host | smart-9775fe64-8ce8-47f0-b32c-a816b4a63a82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311252143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_stress_all.311252143 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.967162316 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 5696981847 ps |
CPU time | 530.94 seconds |
Started | Jul 01 05:01:14 PM PDT 24 |
Finished | Jul 01 05:10:10 PM PDT 24 |
Peak memory | 377140 kb |
Host | smart-a02fe5e8-90ee-466d-aa0b-6899b2e7664f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=967162316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.967162316 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.4164394893 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 4805684773 ps |
CPU time | 233.03 seconds |
Started | Jul 01 05:01:12 PM PDT 24 |
Finished | Jul 01 05:05:10 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-9a36fa48-d921-474e-8150-e316d8b5f9ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164394893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.4164394893 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1872148550 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 344148534 ps |
CPU time | 26 seconds |
Started | Jul 01 05:01:15 PM PDT 24 |
Finished | Jul 01 05:01:46 PM PDT 24 |
Peak memory | 281584 kb |
Host | smart-6e4b1a4e-ace9-4992-a5fa-dbbdbfbfb5d3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872148550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1872148550 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4158009089 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 3041517985 ps |
CPU time | 957.16 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:17:20 PM PDT 24 |
Peak memory | 372572 kb |
Host | smart-7ea31738-0c7a-421c-9466-ed8449610c97 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158009089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.4158009089 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.4241885716 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 11880228 ps |
CPU time | 0.72 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:01:24 PM PDT 24 |
Peak memory | 202380 kb |
Host | smart-75202e58-d341-4fd7-a32f-54876b59228c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241885716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.4241885716 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.1532362459 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 855715783 ps |
CPU time | 54.68 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:02:18 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-76dba151-8841-42aa-828f-0dbe16139024 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532362459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .1532362459 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.2089872387 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 13053723691 ps |
CPU time | 118.61 seconds |
Started | Jul 01 05:01:20 PM PDT 24 |
Finished | Jul 01 05:03:22 PM PDT 24 |
Peak memory | 315060 kb |
Host | smart-6adc87fc-f05b-4bdf-a559-44463f909cbe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089872387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2089872387 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.670762602 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 1252381279 ps |
CPU time | 8.48 seconds |
Started | Jul 01 05:01:20 PM PDT 24 |
Finished | Jul 01 05:01:31 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-efb3c6d1-e3d8-47db-8a14-fc909ea904ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670762602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_esc alation.670762602 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.537335277 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 208077783 ps |
CPU time | 5.95 seconds |
Started | Jul 01 05:01:24 PM PDT 24 |
Finished | Jul 01 05:01:32 PM PDT 24 |
Peak memory | 235272 kb |
Host | smart-005a60ef-18ef-47c3-a65b-6a654615af19 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537335277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.sram_ctrl_max_throughput.537335277 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2401909578 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 156709594 ps |
CPU time | 5.22 seconds |
Started | Jul 01 05:01:23 PM PDT 24 |
Finished | Jul 01 05:01:31 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-0a578fe5-89fc-436c-ade8-3e567c5abe42 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401909578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.2401909578 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.2427752384 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 938768105 ps |
CPU time | 6.35 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:01:30 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-daa55366-3129-4bf4-9392-ffdf4808da6d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427752384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.2427752384 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.1121042582 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 13829173917 ps |
CPU time | 682.98 seconds |
Started | Jul 01 05:01:22 PM PDT 24 |
Finished | Jul 01 05:12:48 PM PDT 24 |
Peak memory | 373232 kb |
Host | smart-33fc4d00-ad8c-4e56-a844-911a8ecaa0dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121042582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.1121042582 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.3828544360 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 467487093 ps |
CPU time | 55.57 seconds |
Started | Jul 01 05:01:22 PM PDT 24 |
Finished | Jul 01 05:02:20 PM PDT 24 |
Peak memory | 306308 kb |
Host | smart-30ceb5b1-0e98-44fd-9198-bb9c7ec77ce3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828544360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.3828544360 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1979154238 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 6806472615 ps |
CPU time | 498.11 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:09:42 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-3a327a3e-e2e8-4090-8d1b-3558eff55e53 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979154238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.1979154238 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.104486645 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 30877509 ps |
CPU time | 0.79 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:01:25 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-abf5b9ab-c365-4b4f-bc76-48152ab85248 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104486645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.104486645 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.1856484443 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 19332020664 ps |
CPU time | 1215.01 seconds |
Started | Jul 01 05:01:22 PM PDT 24 |
Finished | Jul 01 05:21:40 PM PDT 24 |
Peak memory | 368600 kb |
Host | smart-5a78b825-2445-49c7-a490-fac8dcb46672 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856484443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1856484443 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.2635705422 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 678141817 ps |
CPU time | 12.36 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:01:36 PM PDT 24 |
Peak memory | 203004 kb |
Host | smart-2ee1db08-bfc8-4ac8-b8ce-35b5c025d260 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635705422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2635705422 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.1830670430 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 152778537211 ps |
CPU time | 3131.96 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:53:36 PM PDT 24 |
Peak memory | 373584 kb |
Host | smart-60dd6a04-65dc-4fb7-b26a-6e1c90380962 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830670430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.1830670430 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1954602930 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 13086946299 ps |
CPU time | 269.7 seconds |
Started | Jul 01 05:01:21 PM PDT 24 |
Finished | Jul 01 05:05:54 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-2dc33710-1bfd-4553-a621-9ef90ac50a4e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954602930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1954602930 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.924767663 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 1870383182 ps |
CPU time | 26.77 seconds |
Started | Jul 01 05:01:23 PM PDT 24 |
Finished | Jul 01 05:01:52 PM PDT 24 |
Peak memory | 290780 kb |
Host | smart-1035a035-9e7a-4e6a-9a0e-8e3c3222dcae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924767663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.924767663 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3889957468 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 3996638896 ps |
CPU time | 1240.91 seconds |
Started | Jul 01 05:01:29 PM PDT 24 |
Finished | Jul 01 05:22:13 PM PDT 24 |
Peak memory | 373740 kb |
Host | smart-658067ac-8312-42ea-9e63-90723a24abe9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889957468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.3889957468 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.2946923035 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 33318257 ps |
CPU time | 0.67 seconds |
Started | Jul 01 05:01:35 PM PDT 24 |
Finished | Jul 01 05:01:37 PM PDT 24 |
Peak memory | 202584 kb |
Host | smart-3f059ada-0d53-44c2-918a-c366805f673c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946923035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2946923035 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.2649410125 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 20983891128 ps |
CPU time | 77.74 seconds |
Started | Jul 01 05:01:29 PM PDT 24 |
Finished | Jul 01 05:02:50 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-05e68c9a-cf60-490f-af49-e6bcd90a7840 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649410125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .2649410125 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.1135117667 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 14981203308 ps |
CPU time | 380.75 seconds |
Started | Jul 01 05:01:32 PM PDT 24 |
Finished | Jul 01 05:07:55 PM PDT 24 |
Peak memory | 371024 kb |
Host | smart-8a113d11-8777-4b86-a7f2-96eaada654ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135117667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.1135117667 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.4064231278 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 374255904 ps |
CPU time | 5.06 seconds |
Started | Jul 01 05:01:28 PM PDT 24 |
Finished | Jul 01 05:01:36 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-47715c04-8298-4a88-bbdf-b01e84f818c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064231278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.4064231278 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.3338129626 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 239262705 ps |
CPU time | 108.23 seconds |
Started | Jul 01 05:01:28 PM PDT 24 |
Finished | Jul 01 05:03:19 PM PDT 24 |
Peak memory | 348452 kb |
Host | smart-6a081b9d-aef0-4489-815c-3a07f7030bbb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338129626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.3338129626 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.501808365 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 417481474 ps |
CPU time | 5.79 seconds |
Started | Jul 01 05:01:29 PM PDT 24 |
Finished | Jul 01 05:01:37 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-9ae9e269-31ef-4bf8-9eb7-74367f0e28cf |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501808365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_mem_partial_access.501808365 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.1719967624 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 1080044237 ps |
CPU time | 6.22 seconds |
Started | Jul 01 05:01:31 PM PDT 24 |
Finished | Jul 01 05:01:40 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-0231c6f4-cb9f-40e0-befd-7870ab90351e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719967624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.1719967624 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.1758791502 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 16635732558 ps |
CPU time | 1166.31 seconds |
Started | Jul 01 05:01:28 PM PDT 24 |
Finished | Jul 01 05:20:57 PM PDT 24 |
Peak memory | 375744 kb |
Host | smart-583b712d-30af-41cc-b340-88ebb2d0ad44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758791502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.1758791502 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.3172490269 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 125550418 ps |
CPU time | 5.78 seconds |
Started | Jul 01 05:01:30 PM PDT 24 |
Finished | Jul 01 05:01:39 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-bfd3912a-1593-44f0-aab7-1326a2b38434 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172490269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.3172490269 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1797361562 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 16896850397 ps |
CPU time | 304.25 seconds |
Started | Jul 01 05:01:32 PM PDT 24 |
Finished | Jul 01 05:06:39 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-67493ddd-53d6-48a3-8995-ba8200f32392 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797361562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.1797361562 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.3930601390 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 81810510 ps |
CPU time | 0.8 seconds |
Started | Jul 01 05:01:31 PM PDT 24 |
Finished | Jul 01 05:01:34 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-252a777d-3a39-4e22-b633-5f9babe4007a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930601390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3930601390 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.1205454842 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 3367209824 ps |
CPU time | 404.57 seconds |
Started | Jul 01 05:01:31 PM PDT 24 |
Finished | Jul 01 05:08:19 PM PDT 24 |
Peak memory | 365460 kb |
Host | smart-07946d43-c141-4b72-afb1-425243c42b96 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205454842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1205454842 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.2518520080 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 109341485 ps |
CPU time | 3.96 seconds |
Started | Jul 01 05:01:29 PM PDT 24 |
Finished | Jul 01 05:01:36 PM PDT 24 |
Peak memory | 216988 kb |
Host | smart-737c0d7b-b9c2-4f1c-b920-d73dcb50c60f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518520080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2518520080 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.4208281836 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 12401574714 ps |
CPU time | 1036.31 seconds |
Started | Jul 01 05:01:38 PM PDT 24 |
Finished | Jul 01 05:18:55 PM PDT 24 |
Peak memory | 373952 kb |
Host | smart-dffc7dcc-a54b-4030-83c9-a8beb2e99ed3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208281836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.4208281836 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1109533038 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 451156109 ps |
CPU time | 14.61 seconds |
Started | Jul 01 05:01:36 PM PDT 24 |
Finished | Jul 01 05:01:52 PM PDT 24 |
Peak memory | 212148 kb |
Host | smart-ed94c6e2-ff70-4c08-a3ee-59f790606e38 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1109533038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1109533038 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2066840543 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 3647280639 ps |
CPU time | 185.83 seconds |
Started | Jul 01 05:01:31 PM PDT 24 |
Finished | Jul 01 05:04:40 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-094525a1-e67b-4a46-bee3-de3afb377859 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066840543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.2066840543 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2302606553 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 116504426 ps |
CPU time | 69.23 seconds |
Started | Jul 01 05:01:29 PM PDT 24 |
Finished | Jul 01 05:02:41 PM PDT 24 |
Peak memory | 307236 kb |
Host | smart-42f3a5cd-0559-4f54-8029-5dff8eac6e69 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302606553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2302606553 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3816291682 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 3617422189 ps |
CPU time | 1612.81 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:25:19 PM PDT 24 |
Peak memory | 374756 kb |
Host | smart-f0a3941b-576f-4622-aaf2-e6956a2d435b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816291682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.3816291682 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.2262768452 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 22808513 ps |
CPU time | 0.68 seconds |
Started | Jul 01 04:58:18 PM PDT 24 |
Finished | Jul 01 04:58:19 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-1599bceb-ca2a-4cbc-8d99-5d09dad948c4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262768452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.2262768452 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.1134329146 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 22671542156 ps |
CPU time | 78.1 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 04:59:44 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-7c0d264e-d145-4f52-9031-a2782a89cf8e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134329146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 1134329146 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.3120206047 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 12265036183 ps |
CPU time | 1179.01 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 05:18:07 PM PDT 24 |
Peak memory | 374724 kb |
Host | smart-ec78429f-f1af-4535-aefb-45ec7cc51e90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120206047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.3120206047 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.3932068127 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 1729795489 ps |
CPU time | 11.18 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 04:58:37 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-846c5b10-7325-4f44-a156-92c04b7825d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932068127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.3932068127 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.2963693595 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 137635170 ps |
CPU time | 151.45 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 05:01:00 PM PDT 24 |
Peak memory | 367964 kb |
Host | smart-e6c229ba-fd1c-44c7-b98b-74b72573e361 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963693595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.2963693595 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1107242033 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 421562984 ps |
CPU time | 3.41 seconds |
Started | Jul 01 04:58:18 PM PDT 24 |
Finished | Jul 01 04:58:23 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-84157976-7325-4687-8320-6ab1841e0ca3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107242033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.1107242033 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.548492356 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 3249033500 ps |
CPU time | 10.77 seconds |
Started | Jul 01 04:58:18 PM PDT 24 |
Finished | Jul 01 04:58:31 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-3e40700c-5ec8-4254-a80a-95597c523c35 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548492356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ mem_walk.548492356 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.3660812492 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 14370301500 ps |
CPU time | 1180.15 seconds |
Started | Jul 01 04:58:19 PM PDT 24 |
Finished | Jul 01 05:18:02 PM PDT 24 |
Peak memory | 371632 kb |
Host | smart-8f5a26a6-1d2b-4235-ad55-bc44012360bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660812492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.3660812492 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.3815121414 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 90573904 ps |
CPU time | 0.85 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:58:33 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-94bf9c2f-fa63-4f4f-ae78-89df2604280e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815121414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.3815121414 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1643463572 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 4913434820 ps |
CPU time | 354.18 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:04:20 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-87c1da4b-7e5a-4518-87d4-ab0865031f08 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643463572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.1643463572 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.2674878937 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 150842769 ps |
CPU time | 0.76 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 04:58:27 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-39ad0798-aee9-4f5b-b52d-15a5245eb884 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674878937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2674878937 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.4002904982 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 19941448592 ps |
CPU time | 1407.29 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 05:21:53 PM PDT 24 |
Peak memory | 374876 kb |
Host | smart-b5083401-22fe-48c5-a5e4-214b390f6676 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002904982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.4002904982 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.4172182918 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 633252597 ps |
CPU time | 97.25 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 05:00:10 PM PDT 24 |
Peak memory | 356036 kb |
Host | smart-713b6320-4935-4f5b-b628-b74645c17040 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172182918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.4172182918 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.2012587443 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 5892768512 ps |
CPU time | 931.16 seconds |
Started | Jul 01 04:58:19 PM PDT 24 |
Finished | Jul 01 05:13:52 PM PDT 24 |
Peak memory | 374956 kb |
Host | smart-53bfa3e9-14cf-4e67-996a-e6b8e2afc633 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012587443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.2012587443 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2687383064 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 1308685242 ps |
CPU time | 61.46 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 04:59:28 PM PDT 24 |
Peak memory | 292884 kb |
Host | smart-8907a618-69eb-4e34-8ab4-b5cd3226d36e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2687383064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2687383064 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.329911864 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 3153280308 ps |
CPU time | 302.76 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 05:03:35 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-e9be1426-1da2-4b54-b6ff-60b63d8d8be9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329911864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. sram_ctrl_stress_pipeline.329911864 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2291595013 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 281608000 ps |
CPU time | 8.38 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 04:58:35 PM PDT 24 |
Peak memory | 237220 kb |
Host | smart-f9ab900d-4cc1-43fa-90cf-4d697605b934 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291595013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2291595013 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2899671807 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 4807861175 ps |
CPU time | 406.42 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:05:12 PM PDT 24 |
Peak memory | 341860 kb |
Host | smart-42bdf1f8-724f-46c0-a34e-bcc58d2faf9a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899671807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.2899671807 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.3914843365 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 30003665 ps |
CPU time | 0.64 seconds |
Started | Jul 01 04:58:20 PM PDT 24 |
Finished | Jul 01 04:58:22 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-427f8626-55f6-428a-9491-1f69dad02038 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914843365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3914843365 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.701150782 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 3765353877 ps |
CPU time | 63.77 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:59:36 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-b60dd240-a92c-4e65-a8b7-0dd502a76da3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701150782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.701150782 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.1987932065 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 52469701725 ps |
CPU time | 980.31 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:14:46 PM PDT 24 |
Peak memory | 337912 kb |
Host | smart-84f7bd53-3378-48a6-83a2-f3666d6c5003 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987932065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.1987932065 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.494326247 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 3481961820 ps |
CPU time | 5.52 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 04:58:33 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-9dcbd174-a4d8-4178-9823-f5d1a8254d31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494326247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esca lation.494326247 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.2377727816 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 476739243 ps |
CPU time | 120.28 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 05:00:33 PM PDT 24 |
Peak memory | 370308 kb |
Host | smart-543b9c33-5cd9-4da4-9966-f24e8abefddb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377727816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.2377727816 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3581891075 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 308532582 ps |
CPU time | 3.12 seconds |
Started | Jul 01 04:58:25 PM PDT 24 |
Finished | Jul 01 04:58:34 PM PDT 24 |
Peak memory | 211152 kb |
Host | smart-050f810b-8b18-4e3d-98c8-feb073cfd883 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581891075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.3581891075 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.1371431886 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 1070129322 ps |
CPU time | 9.86 seconds |
Started | Jul 01 04:58:19 PM PDT 24 |
Finished | Jul 01 04:58:31 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-04a95f5e-d0ca-4862-9891-4b0fdf6012fb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371431886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.1371431886 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.3831828754 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 108180199264 ps |
CPU time | 1470.46 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 05:22:58 PM PDT 24 |
Peak memory | 371652 kb |
Host | smart-a2256a67-4a2b-4b91-945d-774cdb50586b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831828754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.3831828754 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.3918116263 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 459825286 ps |
CPU time | 10.06 seconds |
Started | Jul 01 04:58:20 PM PDT 24 |
Finished | Jul 01 04:58:33 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-db2d04b0-6e0f-4b19-bdc1-f50d7efbf59e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918116263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.3918116263 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.31292938 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 4305138093 ps |
CPU time | 307.65 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 05:03:36 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-116432a4-0da0-4500-a312-ce6410f015f7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_partial_access_b2b.31292938 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.1566557885 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 42005373 ps |
CPU time | 0.84 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 04:58:25 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-755ab1d0-b96f-4949-a271-0c6a756ffae8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566557885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1566557885 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2046559701 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 1552208929 ps |
CPU time | 414.98 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 05:05:27 PM PDT 24 |
Peak memory | 361212 kb |
Host | smart-522cb130-4706-48a5-b6d7-0de8a7b5355b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046559701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2046559701 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.3129726061 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 2160290754 ps |
CPU time | 64.57 seconds |
Started | Jul 01 04:58:24 PM PDT 24 |
Finished | Jul 01 04:59:34 PM PDT 24 |
Peak memory | 341752 kb |
Host | smart-968dd128-a357-405c-9a6e-b31cacabd462 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129726061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3129726061 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.1326247069 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 68326345013 ps |
CPU time | 5578.51 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 06:31:31 PM PDT 24 |
Peak memory | 380680 kb |
Host | smart-ca425e77-66fd-4f21-a973-abe82a6cb702 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326247069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.1326247069 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2902314277 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 986499805 ps |
CPU time | 86.92 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 04:59:52 PM PDT 24 |
Peak memory | 339600 kb |
Host | smart-f858ed79-f23a-4842-ad47-a071d66d2630 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2902314277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2902314277 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.66203189 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 5332991860 ps |
CPU time | 261.59 seconds |
Started | Jul 01 04:58:19 PM PDT 24 |
Finished | Jul 01 05:02:42 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-55a6a066-edc2-4af9-a8ea-adc06bfdf6d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66203189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_stress_pipeline.66203189 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2087890621 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 438323209 ps |
CPU time | 146.04 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:00:50 PM PDT 24 |
Peak memory | 371340 kb |
Host | smart-8cf4b0f0-3f0b-44c5-bdf5-ad14350882d7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087890621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.2087890621 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3786036807 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 7162275289 ps |
CPU time | 1119.28 seconds |
Started | Jul 01 04:58:21 PM PDT 24 |
Finished | Jul 01 05:17:05 PM PDT 24 |
Peak memory | 372792 kb |
Host | smart-71f87763-37de-4cb3-84d8-41e7bef6ea6b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786036807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.3786036807 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.2298443235 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 15218213 ps |
CPU time | 0.65 seconds |
Started | Jul 01 04:58:28 PM PDT 24 |
Finished | Jul 01 04:58:35 PM PDT 24 |
Peak memory | 202308 kb |
Host | smart-a396c346-ad57-4ca8-b0dd-5030852e6470 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298443235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2298443235 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.2011823502 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 14356371715 ps |
CPU time | 68.44 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 04:59:41 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-0decf3e4-c03a-451e-96b8-2e8f933d668b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011823502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 2011823502 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.2222510315 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 3888100403 ps |
CPU time | 956.39 seconds |
Started | Jul 01 04:58:20 PM PDT 24 |
Finished | Jul 01 05:14:20 PM PDT 24 |
Peak memory | 371716 kb |
Host | smart-71708709-137e-4221-b968-166b2e55e8b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222510315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.2222510315 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.3306324990 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 330768487 ps |
CPU time | 3.12 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 04:58:29 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-eca644cc-1fc8-46c2-bbe4-521e4d89775b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306324990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.3306324990 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.2661724089 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 463592205 ps |
CPU time | 82.61 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:59:55 PM PDT 24 |
Peak memory | 343904 kb |
Host | smart-8d0647ff-bc04-4553-ac07-6d4577593529 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661724089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.2661724089 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1381279941 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 173946043 ps |
CPU time | 5.16 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:58:37 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-7d1cdadd-e09b-4a01-ba33-3b2160dc59a3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381279941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.1381279941 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.2067347591 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 849327775 ps |
CPU time | 11.21 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:58:43 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-e4bd5998-b6c5-41c5-8c81-d62ab367ce54 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067347591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2067347591 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.2367998332 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 8355950229 ps |
CPU time | 58.65 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 04:59:31 PM PDT 24 |
Peak memory | 284124 kb |
Host | smart-24aa860a-7b1e-4009-8e07-8e49e4116378 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367998332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.2367998332 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.2041953169 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 172822060 ps |
CPU time | 37.86 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 04:59:11 PM PDT 24 |
Peak memory | 302936 kb |
Host | smart-5d4d5546-004c-46f1-91ea-290485758e63 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041953169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.2041953169 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4277369306 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 54768951961 ps |
CPU time | 377.16 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 05:04:50 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-17a2e82f-377f-4e5b-8400-b071cedd1d7f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277369306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.4277369306 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.3624130770 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 102352306 ps |
CPU time | 0.76 seconds |
Started | Jul 01 04:58:20 PM PDT 24 |
Finished | Jul 01 04:58:22 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-b34b572d-3b27-4635-a8f5-13c5df332677 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624130770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3624130770 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.1553064052 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 9658547058 ps |
CPU time | 314.56 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 05:03:47 PM PDT 24 |
Peak memory | 359020 kb |
Host | smart-190015c6-a0b6-40d9-b002-03a7cc23832d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553064052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1553064052 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.3267328761 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 499172760 ps |
CPU time | 9.87 seconds |
Started | Jul 01 04:58:24 PM PDT 24 |
Finished | Jul 01 04:58:39 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-e9c4bf13-552f-4a42-97b5-7832e56c8242 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267328761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3267328761 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.3578443206 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 47750715480 ps |
CPU time | 4071.29 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 06:06:19 PM PDT 24 |
Peak memory | 377712 kb |
Host | smart-a40e930f-40da-4c4b-a316-bdf12d2008aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578443206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.3578443206 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1527070498 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 431535832 ps |
CPU time | 120.73 seconds |
Started | Jul 01 04:58:31 PM PDT 24 |
Finished | Jul 01 05:00:37 PM PDT 24 |
Peak memory | 368276 kb |
Host | smart-fbdbd42f-eddc-4425-ae28-02670b4041f5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1527070498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1527070498 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.4146404905 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 7134333401 ps |
CPU time | 347.01 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 05:04:20 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-05a3f230-ea91-4a41-94d0-939000ad5ad3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146404905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.4146404905 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.735865458 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 268347322 ps |
CPU time | 51.48 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:59:24 PM PDT 24 |
Peak memory | 312024 kb |
Host | smart-d8b1203f-d7a1-4f6f-9019-4dd7051ac770 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735865458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_throughput_w_partial_write.735865458 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.4109278794 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 5627810459 ps |
CPU time | 1560.22 seconds |
Started | Jul 01 04:58:24 PM PDT 24 |
Finished | Jul 01 05:24:31 PM PDT 24 |
Peak memory | 372980 kb |
Host | smart-afdd4a5d-79de-4393-ae54-661be50d9256 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109278794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.4109278794 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.3364984952 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 26211190 ps |
CPU time | 0.64 seconds |
Started | Jul 01 04:58:24 PM PDT 24 |
Finished | Jul 01 04:58:30 PM PDT 24 |
Peak memory | 202556 kb |
Host | smart-1823ec7e-eea8-4777-a22f-08d17866eaf0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364984952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.3364984952 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.3270538105 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 9808476586 ps |
CPU time | 59.62 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 04:59:28 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-fdc378db-5888-4826-8d9c-7189570ebd7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270538105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 3270538105 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.2146135201 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 33984004943 ps |
CPU time | 877.43 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 05:13:11 PM PDT 24 |
Peak memory | 367900 kb |
Host | smart-a819051d-af6f-410e-b3a6-d33f1d0f6489 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146135201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.2146135201 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.3496282332 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 458468999 ps |
CPU time | 41.94 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 04:59:15 PM PDT 24 |
Peak memory | 320408 kb |
Host | smart-91cb3d25-7134-4657-97f4-358ace502156 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496282332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.3496282332 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1238922098 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 440631715 ps |
CPU time | 5.8 seconds |
Started | Jul 01 04:58:28 PM PDT 24 |
Finished | Jul 01 04:58:40 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-d953d113-f024-4b80-b596-f36289a22126 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238922098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.1238922098 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.1981277640 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 72354920 ps |
CPU time | 4.44 seconds |
Started | Jul 01 04:58:29 PM PDT 24 |
Finished | Jul 01 04:58:39 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-187b7349-f48e-4bd6-8ed7-733e9ddcad1c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981277640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.1981277640 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.3322100983 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 21985827907 ps |
CPU time | 785.76 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 05:11:38 PM PDT 24 |
Peak memory | 370436 kb |
Host | smart-2b92908e-a17f-47bd-8387-3bc2a675ae4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322100983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.3322100983 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.1382018685 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 1752409895 ps |
CPU time | 90.01 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 04:59:57 PM PDT 24 |
Peak memory | 328284 kb |
Host | smart-ac59b28e-51c7-41a4-8028-1ee2f250428d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382018685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.1382018685 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.375196522 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 245967536173 ps |
CPU time | 585.2 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 05:08:18 PM PDT 24 |
Peak memory | 203048 kb |
Host | smart-7c8e135b-52ab-40c4-a9ff-5ead8d60144f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375196522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.sram_ctrl_partial_access_b2b.375196522 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.2959419261 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 28165884 ps |
CPU time | 0.79 seconds |
Started | Jul 01 04:58:46 PM PDT 24 |
Finished | Jul 01 04:58:51 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-960a45fc-c20e-4fa3-8987-7a4db9f5cb60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959419261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2959419261 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.3821964904 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 27434443824 ps |
CPU time | 708.78 seconds |
Started | Jul 01 04:58:28 PM PDT 24 |
Finished | Jul 01 05:10:23 PM PDT 24 |
Peak memory | 362188 kb |
Host | smart-c6c9f479-2bc8-4e52-8704-27779bec115a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821964904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3821964904 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.985524135 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 377770086 ps |
CPU time | 30.14 seconds |
Started | Jul 01 04:58:24 PM PDT 24 |
Finished | Jul 01 04:58:59 PM PDT 24 |
Peak memory | 283624 kb |
Host | smart-5eb82928-8bc7-4621-89ea-909afdc1df24 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985524135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.985524135 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.3339412483 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 177802425984 ps |
CPU time | 1530.11 seconds |
Started | Jul 01 04:58:24 PM PDT 24 |
Finished | Jul 01 05:23:59 PM PDT 24 |
Peak memory | 375848 kb |
Host | smart-da836bea-d18e-40b6-8205-2148f1f3cd80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339412483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.3339412483 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3944002929 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 3758813533 ps |
CPU time | 136.41 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 05:00:49 PM PDT 24 |
Peak memory | 302104 kb |
Host | smart-b15c9f5c-a2df-4b7d-aac2-eef70e53a5a7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3944002929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3944002929 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1687493184 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 18001859565 ps |
CPU time | 267.64 seconds |
Started | Jul 01 04:58:22 PM PDT 24 |
Finished | Jul 01 05:02:54 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-bf40c9e1-40bc-4cbf-80a7-969df409b133 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687493184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.1687493184 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1363245000 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 131435404 ps |
CPU time | 103.12 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 05:00:15 PM PDT 24 |
Peak memory | 344968 kb |
Host | smart-124e4e1d-80ca-4447-84f3-5e9dc89e47c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363245000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1363245000 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2557704949 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 12167072458 ps |
CPU time | 1034.86 seconds |
Started | Jul 01 04:58:28 PM PDT 24 |
Finished | Jul 01 05:15:49 PM PDT 24 |
Peak memory | 376000 kb |
Host | smart-7b64b17d-0dc9-45f9-9435-4523e7f0b49f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557704949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.2557704949 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.1293629988 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 18527393 ps |
CPU time | 0.66 seconds |
Started | Jul 01 04:58:29 PM PDT 24 |
Finished | Jul 01 04:58:35 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-78670727-9e75-4dfb-827f-89b694f17147 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293629988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1293629988 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.3698429882 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 1401812904 ps |
CPU time | 43.56 seconds |
Started | Jul 01 04:58:25 PM PDT 24 |
Finished | Jul 01 04:59:15 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-2df0dee0-08be-419f-888a-6b5328494998 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698429882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 3698429882 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.1664638734 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 66267418859 ps |
CPU time | 798.91 seconds |
Started | Jul 01 04:58:31 PM PDT 24 |
Finished | Jul 01 05:11:56 PM PDT 24 |
Peak memory | 360992 kb |
Host | smart-145c8689-c518-4589-a0f8-eaf0c24291c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664638734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.1664638734 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.656624456 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 1647725654 ps |
CPU time | 5.25 seconds |
Started | Jul 01 04:58:29 PM PDT 24 |
Finished | Jul 01 04:58:40 PM PDT 24 |
Peak memory | 214508 kb |
Host | smart-e0337672-56a0-49a3-a888-e72b0926ea99 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656624456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca lation.656624456 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.3347615716 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 518940815 ps |
CPU time | 54.05 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 04:59:23 PM PDT 24 |
Peak memory | 324492 kb |
Host | smart-53009bd7-a7ac-424c-9fa2-5266afc94150 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347615716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.3347615716 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1126241075 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 311507128 ps |
CPU time | 3.17 seconds |
Started | Jul 01 04:58:33 PM PDT 24 |
Finished | Jul 01 04:58:41 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-2678968e-26b1-455f-b448-2072ce1e0cdc |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126241075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.1126241075 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.3413162522 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 656955925 ps |
CPU time | 10.1 seconds |
Started | Jul 01 04:58:32 PM PDT 24 |
Finished | Jul 01 04:58:47 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-d693452a-f3e6-466f-ad01-89b29545119c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413162522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3413162522 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.202730424 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 11033282347 ps |
CPU time | 442.41 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 05:05:51 PM PDT 24 |
Peak memory | 348168 kb |
Host | smart-61ac5fd8-7937-4489-ac33-500bba41abae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202730424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multipl e_keys.202730424 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.3446880548 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 501183937 ps |
CPU time | 6.37 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 04:58:38 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-e4cd50d8-f3d2-47b8-bffc-1deab834aa73 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446880548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3446880548 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.731560390 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 2287071628 ps |
CPU time | 160.41 seconds |
Started | Jul 01 04:58:23 PM PDT 24 |
Finished | Jul 01 05:01:14 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-39a94762-db8f-4818-bc3c-2059382af603 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731560390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 9.sram_ctrl_partial_access_b2b.731560390 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.1477649294 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 72786811 ps |
CPU time | 0.75 seconds |
Started | Jul 01 04:58:25 PM PDT 24 |
Finished | Jul 01 04:58:32 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-6d8075ed-d256-4d9a-9c4b-182c61e738f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477649294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.1477649294 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.3931415669 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 44659653295 ps |
CPU time | 377.01 seconds |
Started | Jul 01 04:58:31 PM PDT 24 |
Finished | Jul 01 05:04:53 PM PDT 24 |
Peak memory | 360160 kb |
Host | smart-cb604e0d-9319-473a-bec2-e894291005fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931415669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3931415669 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.3528997950 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 1218365597 ps |
CPU time | 14.26 seconds |
Started | Jul 01 04:58:27 PM PDT 24 |
Finished | Jul 01 04:58:47 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-b43b0f31-7def-4a3d-9224-dd52727d81ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528997950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3528997950 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.4032414917 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 12374882103 ps |
CPU time | 656.78 seconds |
Started | Jul 01 04:58:28 PM PDT 24 |
Finished | Jul 01 05:09:31 PM PDT 24 |
Peak memory | 358168 kb |
Host | smart-b7d8502e-bcbc-421b-a4e1-9ccdb56dd9eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032414917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.4032414917 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1088672948 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 3557241991 ps |
CPU time | 106.18 seconds |
Started | Jul 01 04:58:34 PM PDT 24 |
Finished | Jul 01 05:00:25 PM PDT 24 |
Peak memory | 317976 kb |
Host | smart-7232d881-3620-4ef1-8e60-5e8bd5513786 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1088672948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1088672948 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3942170783 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 2439151028 ps |
CPU time | 164.72 seconds |
Started | Jul 01 04:58:26 PM PDT 24 |
Finished | Jul 01 05:01:16 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-79d0af72-f4a4-4d42-94a9-2f1903ae73eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942170783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.3942170783 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4170268207 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 94609644 ps |
CPU time | 4.03 seconds |
Started | Jul 01 04:58:34 PM PDT 24 |
Finished | Jul 01 04:58:43 PM PDT 24 |
Peak memory | 223184 kb |
Host | smart-b068f0c4-9cfb-466f-a6da-310be4c458cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170268207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.4170268207 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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