Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 16 0 16 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_exec_cp 3 0 3 100.00 100 1 1 0
en_sram_ifetch_cp 3 0 3 100.00 100 1 1 0
lc_hw_debug_en_cp 3 0 3 100.00 100 1 1 0


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
executable_cross 16 0 16 100.00 100 1 1 0


Summary for Variable csr_exec_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csr_exec_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
instr_invalid_dis 152026964 1 T1 476634 T2 119066 T3 6142
instr_valid_dis 118308584 1 T1 476634 T2 98730 T3 6142
instr_en 24409168 1 T2 20336 T26 143094 T44 49948



Summary for Variable en_sram_ifetch_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for en_sram_ifetch_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_ifetch_invalid_disable 11521481 1 T20 55624 T26 78798 T44 63560
sram_ifetch_valid_disable 116167430 1 T1 476634 T2 118730 T3 6142
sram_ifetch_enable 24338053 1 T2 336 T20 130982 T25 25020



Summary for Variable lc_hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for lc_hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off 152026964 1 T1 476634 T2 119066 T3 6142
hw_debug_en_valid_off 116633455 1 T1 476634 T2 98730 T3 6142
hw_debug_en_on 23063609 1 T2 20000 T20 169822 T26 19080



Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 16 0 16 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for executable_cross

Bins
lc_hw_debug_en_cpen_sram_ifetch_cpcsr_exec_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_invalid_dis 116167430 1 T1 476634 T2 118730 T3 6142
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_valid_dis 103527543 1 T1 476634 T2 98730 T3 6142
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_en 9348310 1 T2 20000 T26 64120 T44 47436
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_invalid_dis 4448659 1 T20 55624 T26 39718 T44 51658
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_valid_dis 1944690 1 T44 51658 T153 42222 T148 5604
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_en 1897478 1 T26 39718 T21 212 T22 14182
hw_debug_en_on sram_ifetch_invalid_disable instr_invalid_dis 4645136 1 T26 19080 T22 54162 T48 18556
hw_debug_en_on sram_ifetch_invalid_disable instr_valid_dis 2201456 1 T22 54162 T48 18556 T142 8730
hw_debug_en_on sram_ifetch_invalid_disable instr_en 1851108 1 T142 10364 T145 29496 T143 49666
hw_debug_en_on sram_ifetch_valid_disable instr_invalid_dis 7883538 1 T2 20000 T20 93014 T44 37802
hw_debug_en_on sram_ifetch_valid_disable instr_valid_dis 3224448 1 T44 15664 T22 183872 T145 41880
hw_debug_en_on sram_ifetch_valid_disable instr_en 3429958 1 T2 20000 T44 22138 T21 23828


User Defined Cross Bins for executable_cross

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
csr_exec_en 10056984 1 T2 336 T26 19256 T44 2512
lc_exec_en 10534935 1 T20 76808 T44 4232 T21 11360
valid_exec_dis 112950495 1 T1 476634 T2 98730 T3 6142
invalid_exec_dis 35859534 1 T2 336 T20 186606 T25 25020

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