Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45399886	1			T1	216792		T2	36113		T3	3071
triple_byte_access	2594428	1			T1	4285		T2	331		T5	15696
halfword_access	3890713	1			T1	6511		T2	481		T5	23421
byte_access	5195430	1			T1	8591		T2	668		T5	30882
zero_access	1309167	1			T1	2138		T2	151		T5	7727

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29142693

1

T1

118845

T2

17993

T3

1024

auto[1]

29246931

1

T1

119472

T2

19751

T3

2047

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22652110	1			T1	108201		T2	17179		T3	1024
auto[0]	triple_byte_access	1294837	1			T1	2150		T2	174		T5	7824
auto[0]	halfword_access	1941036	1			T1	3180		T2	259		T5	11810
auto[0]	byte_access	2596164	1			T1	4252		T2	313		T5	15450
auto[0]	zero_access	658546	1			T1	1062		T2	68		T5	3843
auto[1]	word_access	22747776	1			T1	108591		T2	18934		T3	2047
auto[1]	triple_byte_access	1299591	1			T1	2135		T2	157		T5	7872
auto[1]	halfword_access	1949677	1			T1	3331		T2	222		T5	11611
auto[1]	byte_access	2599266	1			T1	4339		T2	355		T5	15432
auto[1]	zero_access	650621	1			T1	1076		T2	83		T5	3884