Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	149269060	1			T1	410186		T3	9254		T4	3952
instr_valid_dis	115049179	1			T1	279158		T3	9254		T4	3952
instr_en	21642046	1			T1	105490		T21	65986		T22	262132

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11144414	1			T1	99170		T75	60230		T64	125198
sram_ifetch_valid_disable	115489624	1			T1	126450		T3	9254		T4	3952
sram_ifetch_enable	22635022	1			T1	184566		T20	3418		T22	131190

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	149269060	1			T1	410186		T3	9254		T4	3952
hw_debug_en_valid_off	117068425	1			T1	218450		T3	9254		T4	3952
hw_debug_en_on	22012754	1			T1	89528		T20	3418		T25	4526

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115489624	1			T1	126450		T3	9254		T4	3952
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102196015	1			T1	52878		T3	9254		T4	3952
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8605208	1			T1	63516		T21	65986		T22	130942
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4365652	1			T1	77018		T64	73118		T45	60956
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1617756	1			T1	64022		T45	60956		T133	18116
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1903998	1			T46	29164		T141	7154		T133	11058
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4807982	1			T1	16886		T75	18240		T64	34516
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1603736	1			T1	16886		T75	12070		T135	15164
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1731176	1			T75	6170		T142	18526		T133	29702
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8235738	1			T1	54312		T25	4526		T21	16322
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2880644	1			T1	38380		T25	4526		T75	29020
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3805114	1			T1	15932		T21	16322		T22	56492

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8572298	1			T1	41974		T22	131190		T75	51736
lc_exec_en	8969034	1			T1	18330		T20	3418		T22	48530
valid_exec_dis	111604265	1			T1	204674		T3	9254		T4	3952
invalid_exec_dis	33779436	1			T1	283736		T20	3418		T22	131190