Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45107438	1			T1	74358		T3	3762		T4	121
triple_byte_access	2555185	1			T1	1469		T3	181		T4	253
halfword_access	3829566	1			T1	2205		T3	266		T4	434
byte_access	5106070	1			T1	2958		T3	331		T4	761
zero_access	1286723	1			T1	723		T3	87		T4	407

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28888950

1

T1

40802

T3

2310

T4

866

auto[1]

28996032

1

T1

40911

T3

2317

T4

1110

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22503177	1			T1	37143		T3	1870		T4	5
auto[0]	triple_byte_access	1274565	1			T1	725		T3	99		T4	43
auto[0]	halfword_access	1909904	1			T1	1092		T3	149		T4	133
auto[0]	byte_access	2553893	1			T1	1488		T3	153		T4	375
auto[0]	zero_access	647411	1			T1	354		T3	39		T4	310
auto[1]	word_access	22604261	1			T1	37215		T3	1892		T4	116
auto[1]	triple_byte_access	1280620	1			T1	744		T3	82		T4	210
auto[1]	halfword_access	1919662	1			T1	1113		T3	117		T4	301
auto[1]	byte_access	2552177	1			T1	1470		T3	178		T4	386
auto[1]	zero_access	639312	1			T1	369		T3	48		T4	97