Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 16 0 16 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_exec_cp 3 0 3 100.00 100 1 1 0
en_sram_ifetch_cp 3 0 3 100.00 100 1 1 0
lc_hw_debug_en_cp 3 0 3 100.00 100 1 1 0


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
executable_cross 16 0 16 100.00 100 1 1 0


Summary for Variable csr_exec_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csr_exec_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
instr_invalid_dis 146185238 1 T1 20680 T3 595842 T4 1990
instr_valid_dis 113661433 1 T1 20680 T3 278270 T4 1990
instr_en 22028240 1 T5 50502 T22 7154 T59 329734



Summary for Variable en_sram_ifetch_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for en_sram_ifetch_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_ifetch_invalid_disable 10428789 1 T3 19270 T5 33664 T7 153806
sram_ifetch_valid_disable 114305415 1 T1 20680 T3 458274 T4 1990
sram_ifetch_enable 21451034 1 T3 118298 T5 976 T7 266982



Summary for Variable lc_hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for lc_hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off 146185238 1 T1 20680 T3 595842 T4 1990
hw_debug_en_valid_off 114840377 1 T1 20680 T3 397002 T4 1990
hw_debug_en_on 21176577 1 T3 159172 T5 25464 T7 169480



Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 16 0 16 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for executable_cross

Bins
lc_hw_debug_en_cpen_sram_ifetch_cpcsr_exec_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_invalid_dis 114305415 1 T1 20680 T3 458274 T4 1990
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_valid_dis 101305044 1 T1 20680 T3 278270 T4 1990
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_en 9158618 1 T5 15862 T59 229952 T134 17886
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_invalid_dis 4529074 1 T3 11930 T7 61286 T22 355462
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_valid_dis 1466190 1 T7 61286 T22 28884 T55 20378
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_en 1656178 1 T59 2008 T20 12116 T45 22822
hw_debug_en_on sram_ifetch_invalid_disable instr_invalid_dis 3807645 1 T3 7340 T5 8716 T7 92520
hw_debug_en_on sram_ifetch_invalid_disable instr_valid_dis 1471121 1 T7 92520 T55 92188 T59 93660
hw_debug_en_on sram_ifetch_invalid_disable instr_en 1492018 1 T5 8716 T59 2984 T130 26044
hw_debug_en_on sram_ifetch_valid_disable instr_invalid_dis 8675842 1 T3 81550 T5 15772 T22 81228
hw_debug_en_on sram_ifetch_valid_disable instr_valid_dis 3338336 1 T22 81228 T59 323444 T28 37478
hw_debug_en_on sram_ifetch_valid_disable instr_en 4071754 1 T5 15772 T59 177072 T134 5726


User Defined Cross Bins for executable_cross

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
csr_exec_en 9051392 1 T5 976 T22 7154 T59 65812
lc_exec_en 8693090 1 T3 70282 T5 976 T7 76960
valid_exec_dis 110671651 1 T1 20680 T3 358152 T4 1990
invalid_exec_dis 31879823 1 T3 137568 T5 34640 T7 420788

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