Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
escalated_cp 2 0 2 100.00 100 1 1 2
key_seed_valid_cp 2 0 2 100.00 100 1 1 2


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_seed_valid_cross 4 0 4 100.00 100 1 1 0


Summary for Variable escalated_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for escalated_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8483 1 T1 8 T3 53 T4 1
auto[1] 970 1 T3 17 T6 7 T7 24



Summary for Variable key_seed_valid_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_seed_valid_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4653 1 T1 6 T3 30 T8 4
auto[1] 4800 1 T1 2 T3 40 T4 1



Summary for Cross key_seed_valid_cross

Samples crossed: key_seed_valid_cp escalated_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key_seed_valid_cross

Bins
key_seed_valid_cpescalated_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 4189 1 T1 6 T3 25 T8 4
auto[0] auto[1] 464 1 T3 5 T6 2 T7 13
auto[1] auto[0] 4294 1 T1 2 T3 28 T4 1
auto[1] auto[1] 506 1 T3 12 T6 5 T7 11

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