Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44177354	1			T1	2501		T3	186744		T4	42
triple_byte_access	2476103	1			T1	30		T3	2723		T4	126
halfword_access	3717009	1			T1	40		T3	3990		T4	243
byte_access	4964617	1			T1	53		T3	5334		T4	396
zero_access	1250281	1			T1	16		T3	1279		T4	188

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28236611

1

T1

758

T3

100232

T4

392

auto[1]

28348753

1

T1

1882

T3

99838

T4

603

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22035955	1			T1	680		T3	93528		T4	2
auto[0]	triple_byte_access	1234608	1			T1	19		T3	1373		T4	20
auto[0]	halfword_access	1855825	1			T1	23		T3	1988		T4	65
auto[0]	byte_access	2481539	1			T1	26		T3	2696		T4	171
auto[0]	zero_access	628684	1			T1	10		T3	647		T4	134
auto[1]	word_access	22141399	1			T1	1821		T3	93216		T4	40
auto[1]	triple_byte_access	1241495	1			T1	11		T3	1350		T4	106
auto[1]	halfword_access	1861184	1			T1	17		T3	2002		T4	178
auto[1]	byte_access	2483078	1			T1	27		T3	2638		T4	225
auto[1]	zero_access	621597	1			T1	6		T3	632		T4	54