Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	143674994	1			T1	130776		T2	385712		T4	12284
instr_valid_dis	113704329	1			T1	116190		T2	297222		T4	12284
instr_en	21064101	1			T2	88490		T11	40408		T35	43374

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11185837	1			T1	14352		T2	57916		T11	79982
sram_ifetch_valid_disable	110514702	1			T1	103270		T2	248558		T4	12284
sram_ifetch_enable	21974455	1			T1	13154		T2	79238		T11	165682

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	143674994	1			T1	130776		T2	385712		T4	12284
hw_debug_en_valid_off	111204954	1			T1	59084		T2	263912		T4	12284
hw_debug_en_on	21451870	1			T1	56166		T2	59372		T11	96570

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110514702	1			T1	103270		T2	248558		T4	12284
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	98832087	1			T1	88684		T2	188126		T4	12284
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8312344	1			T2	60432		T11	15230		T7	156380
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4197389	1			T2	22778		T7	212822		T53	58560
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1966202	1			T2	22778		T7	116248		T21	18184
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1458292	1			T7	27502		T53	58560		T21	14374
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4324900	1			T2	7080		T11	62980		T35	43374
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1841772	1			T2	7080		T11	43456		T7	40592
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1775702	1			T35	43374		T53	23006		T21	11872
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8637053	1			T1	56166		T2	36062		T11	33590
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3823968	1			T1	41580		T2	7502		T11	18360
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3346418	1			T2	28560		T11	15230		T7	43058

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8750487	1			T11	17946		T7	143442		T53	1402
lc_exec_en	8489917	1			T2	16230		T35	48424		T7	215812
valid_exec_dis	107328841	1			T1	59084		T2	272420		T4	12284
invalid_exec_dis	33160292	1			T1	27506		T2	137154		T11	245664