Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42270846	1			T1	23751		T2	105025		T4	6142
triple_byte_access	2575236	1			T1	490		T2	2096		T6	5086
halfword_access	3865776	1			T1	728		T2	3157		T6	7743
byte_access	5159007	1			T1	991		T2	4187		T6	10036
zero_access	1297709	1			T1	258		T2	1026		T6	2576

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27528808

1

T1

13103

T2

57772

T4

2048

auto[1]

27639766

1

T1

13115

T2

57719

T4

4094

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21086585	1			T1	11883		T2	52555		T4	2048
auto[0]	triple_byte_access	1284724	1			T1	243		T2	1022		T6	2568
auto[0]	halfword_access	1928737	1			T1	370		T2	1574		T6	3820
auto[0]	byte_access	2577017	1			T1	477		T2	2092		T6	4962
auto[0]	zero_access	651745	1			T1	130		T2	529		T6	1281
auto[1]	word_access	21184261	1			T1	11868		T2	52470		T4	4094
auto[1]	triple_byte_access	1290512	1			T1	247		T2	1074		T6	2518
auto[1]	halfword_access	1937039	1			T1	358		T2	1583		T6	3923
auto[1]	byte_access	2581990	1			T1	514		T2	2095		T6	5074
auto[1]	zero_access	645964	1			T1	128		T2	497		T6	1295