| T789 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2398466537 |
|
|
Jul 06 04:53:12 PM PDT 24 |
Jul 06 04:53:14 PM PDT 24 |
131264670 ps |
| T790 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1686432726 |
|
|
Jul 06 04:56:20 PM PDT 24 |
Jul 06 04:56:25 PM PDT 24 |
383520038 ps |
| T791 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.6264358 |
|
|
Jul 06 04:56:44 PM PDT 24 |
Jul 06 04:57:29 PM PDT 24 |
365550461 ps |
| T792 |
/workspace/coverage/default/6.sram_ctrl_stress_all.2233242579 |
|
|
Jul 06 04:53:02 PM PDT 24 |
Jul 06 05:26:13 PM PDT 24 |
32131919846 ps |
| T793 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2900804125 |
|
|
Jul 06 04:53:10 PM PDT 24 |
Jul 06 05:10:38 PM PDT 24 |
1694457090 ps |
| T794 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.2634703398 |
|
|
Jul 06 04:52:59 PM PDT 24 |
Jul 06 04:53:06 PM PDT 24 |
6161908506 ps |
| T795 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2786503218 |
|
|
Jul 06 04:54:09 PM PDT 24 |
Jul 06 05:07:44 PM PDT 24 |
6014031420 ps |
| T796 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.1867717456 |
|
|
Jul 06 04:52:57 PM PDT 24 |
Jul 06 04:59:27 PM PDT 24 |
8457195956 ps |
| T797 |
/workspace/coverage/default/6.sram_ctrl_smoke.3289901333 |
|
|
Jul 06 04:52:58 PM PDT 24 |
Jul 06 04:53:03 PM PDT 24 |
84246690 ps |
| T798 |
/workspace/coverage/default/43.sram_ctrl_regwen.121617941 |
|
|
Jul 06 04:55:58 PM PDT 24 |
Jul 06 05:00:12 PM PDT 24 |
1280345156 ps |
| T799 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3953037003 |
|
|
Jul 06 04:54:49 PM PDT 24 |
Jul 06 04:55:04 PM PDT 24 |
368598866 ps |
| T800 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.3660819339 |
|
|
Jul 06 04:54:23 PM PDT 24 |
Jul 06 04:54:28 PM PDT 24 |
558048496 ps |
| T801 |
/workspace/coverage/default/40.sram_ctrl_stress_all.2361545651 |
|
|
Jul 06 04:55:37 PM PDT 24 |
Jul 06 05:51:02 PM PDT 24 |
9239567097 ps |
| T802 |
/workspace/coverage/default/19.sram_ctrl_smoke.1665338381 |
|
|
Jul 06 04:53:40 PM PDT 24 |
Jul 06 04:53:49 PM PDT 24 |
1566786358 ps |
| T803 |
/workspace/coverage/default/14.sram_ctrl_executable.2643538254 |
|
|
Jul 06 04:53:32 PM PDT 24 |
Jul 06 04:56:29 PM PDT 24 |
4194630880 ps |
| T804 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1870295310 |
|
|
Jul 06 04:56:34 PM PDT 24 |
Jul 06 04:56:40 PM PDT 24 |
375505867 ps |
| T805 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2027133626 |
|
|
Jul 06 04:55:46 PM PDT 24 |
Jul 06 04:55:48 PM PDT 24 |
46379439 ps |
| T806 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1109626716 |
|
|
Jul 06 04:55:46 PM PDT 24 |
Jul 06 04:56:02 PM PDT 24 |
441483684 ps |
| T807 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3366040659 |
|
|
Jul 06 04:56:20 PM PDT 24 |
Jul 06 04:59:33 PM PDT 24 |
7775328825 ps |
| T808 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.184850881 |
|
|
Jul 06 04:55:47 PM PDT 24 |
Jul 06 05:01:31 PM PDT 24 |
13191040977 ps |
| T809 |
/workspace/coverage/default/15.sram_ctrl_bijection.2254929536 |
|
|
Jul 06 04:53:43 PM PDT 24 |
Jul 06 04:54:21 PM PDT 24 |
8149742993 ps |
| T810 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1048258388 |
|
|
Jul 06 04:53:16 PM PDT 24 |
Jul 06 05:07:50 PM PDT 24 |
3197086520 ps |
| T811 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.450276277 |
|
|
Jul 06 04:53:06 PM PDT 24 |
Jul 06 04:53:40 PM PDT 24 |
93499774 ps |
| T812 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3277679680 |
|
|
Jul 06 04:52:48 PM PDT 24 |
Jul 06 04:56:58 PM PDT 24 |
3526807908 ps |
| T813 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2246690987 |
|
|
Jul 06 04:53:17 PM PDT 24 |
Jul 06 04:53:24 PM PDT 24 |
1861025298 ps |
| T814 |
/workspace/coverage/default/49.sram_ctrl_partial_access.89655901 |
|
|
Jul 06 04:56:44 PM PDT 24 |
Jul 06 04:56:48 PM PDT 24 |
365524017 ps |
| T815 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.1638581597 |
|
|
Jul 06 04:53:04 PM PDT 24 |
Jul 06 04:54:52 PM PDT 24 |
127499657 ps |
| T816 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4148166220 |
|
|
Jul 06 04:53:19 PM PDT 24 |
Jul 06 05:04:00 PM PDT 24 |
4693253785 ps |
| T817 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.1044142286 |
|
|
Jul 06 04:55:30 PM PDT 24 |
Jul 06 05:01:18 PM PDT 24 |
15225277181 ps |
| T818 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.361906781 |
|
|
Jul 06 04:54:13 PM PDT 24 |
Jul 06 04:54:14 PM PDT 24 |
47106162 ps |
| T819 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1712903909 |
|
|
Jul 06 04:54:26 PM PDT 24 |
Jul 06 04:54:29 PM PDT 24 |
241037660 ps |
| T820 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.837880620 |
|
|
Jul 06 04:55:50 PM PDT 24 |
Jul 06 04:55:55 PM PDT 24 |
1593831083 ps |
| T821 |
/workspace/coverage/default/11.sram_ctrl_smoke.2075162970 |
|
|
Jul 06 04:53:27 PM PDT 24 |
Jul 06 04:55:09 PM PDT 24 |
1950756625 ps |
| T822 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2124137753 |
|
|
Jul 06 04:53:15 PM PDT 24 |
Jul 06 05:00:04 PM PDT 24 |
11597954628 ps |
| T823 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.3448619600 |
|
|
Jul 06 04:53:36 PM PDT 24 |
Jul 06 04:53:40 PM PDT 24 |
1670455388 ps |
| T824 |
/workspace/coverage/default/40.sram_ctrl_bijection.2286723705 |
|
|
Jul 06 04:55:30 PM PDT 24 |
Jul 06 04:56:07 PM PDT 24 |
2302971739 ps |
| T825 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3854282077 |
|
|
Jul 06 04:55:06 PM PDT 24 |
Jul 06 04:55:15 PM PDT 24 |
66933609 ps |
| T826 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.481888993 |
|
|
Jul 06 04:54:26 PM PDT 24 |
Jul 06 04:56:08 PM PDT 24 |
3561060274 ps |
| T827 |
/workspace/coverage/default/23.sram_ctrl_bijection.56949537 |
|
|
Jul 06 04:53:53 PM PDT 24 |
Jul 06 04:54:43 PM PDT 24 |
2493827943 ps |
| T828 |
/workspace/coverage/default/26.sram_ctrl_stress_all.3746364026 |
|
|
Jul 06 04:54:09 PM PDT 24 |
Jul 06 05:11:57 PM PDT 24 |
29985832092 ps |
| T829 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2365692699 |
|
|
Jul 06 04:55:52 PM PDT 24 |
Jul 06 05:00:44 PM PDT 24 |
1201038054 ps |
| T830 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2770798895 |
|
|
Jul 06 04:53:58 PM PDT 24 |
Jul 06 05:39:40 PM PDT 24 |
51337071067 ps |
| T831 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1317558399 |
|
|
Jul 06 04:53:14 PM PDT 24 |
Jul 06 04:53:17 PM PDT 24 |
117550352 ps |
| T832 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3222476275 |
|
|
Jul 06 04:53:53 PM PDT 24 |
Jul 06 04:53:58 PM PDT 24 |
662533633 ps |
| T833 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3582839993 |
|
|
Jul 06 04:54:28 PM PDT 24 |
Jul 06 04:54:31 PM PDT 24 |
85987602 ps |
| T834 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.108758404 |
|
|
Jul 06 04:53:38 PM PDT 24 |
Jul 06 04:53:44 PM PDT 24 |
98418765 ps |
| T835 |
/workspace/coverage/default/42.sram_ctrl_smoke.2700244407 |
|
|
Jul 06 04:55:48 PM PDT 24 |
Jul 06 04:56:04 PM PDT 24 |
252464840 ps |
| T836 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.105231971 |
|
|
Jul 06 04:53:29 PM PDT 24 |
Jul 06 05:07:56 PM PDT 24 |
12814615978 ps |
| T109 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3337437794 |
|
|
Jul 06 04:53:17 PM PDT 24 |
Jul 06 04:53:53 PM PDT 24 |
2432596682 ps |
| T837 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.31058481 |
|
|
Jul 06 04:53:30 PM PDT 24 |
Jul 06 05:06:06 PM PDT 24 |
11452643946 ps |
| T838 |
/workspace/coverage/default/21.sram_ctrl_stress_all.3641589683 |
|
|
Jul 06 04:53:54 PM PDT 24 |
Jul 06 05:48:03 PM PDT 24 |
48808764291 ps |
| T839 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.845861463 |
|
|
Jul 06 04:54:20 PM PDT 24 |
Jul 06 04:56:17 PM PDT 24 |
1955020679 ps |
| T840 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2245104763 |
|
|
Jul 06 04:53:07 PM PDT 24 |
Jul 06 04:53:10 PM PDT 24 |
698359660 ps |
| T841 |
/workspace/coverage/default/25.sram_ctrl_partial_access.1528496481 |
|
|
Jul 06 04:53:58 PM PDT 24 |
Jul 06 04:54:56 PM PDT 24 |
527010725 ps |
| T842 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.23230806 |
|
|
Jul 06 04:55:05 PM PDT 24 |
Jul 06 04:55:11 PM PDT 24 |
1224298354 ps |
| T843 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1960189755 |
|
|
Jul 06 04:55:10 PM PDT 24 |
Jul 06 05:12:22 PM PDT 24 |
6873029326 ps |
| T844 |
/workspace/coverage/default/2.sram_ctrl_regwen.2523658355 |
|
|
Jul 06 04:52:53 PM PDT 24 |
Jul 06 05:09:10 PM PDT 24 |
8484996097 ps |
| T845 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.1239087986 |
|
|
Jul 06 04:53:03 PM PDT 24 |
Jul 06 04:53:15 PM PDT 24 |
2725522685 ps |
| T846 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1592570778 |
|
|
Jul 06 04:53:02 PM PDT 24 |
Jul 06 05:24:21 PM PDT 24 |
126116982323 ps |
| T847 |
/workspace/coverage/default/31.sram_ctrl_bijection.3540144343 |
|
|
Jul 06 04:54:30 PM PDT 24 |
Jul 06 04:55:03 PM PDT 24 |
6130430405 ps |
| T848 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2973013240 |
|
|
Jul 06 04:56:22 PM PDT 24 |
Jul 06 04:56:23 PM PDT 24 |
90876565 ps |
| T849 |
/workspace/coverage/default/25.sram_ctrl_alert_test.1409570443 |
|
|
Jul 06 04:54:06 PM PDT 24 |
Jul 06 04:54:07 PM PDT 24 |
84783015 ps |
| T850 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2755898987 |
|
|
Jul 06 04:55:21 PM PDT 24 |
Jul 06 05:05:26 PM PDT 24 |
11157883169 ps |
| T851 |
/workspace/coverage/default/9.sram_ctrl_executable.3488892522 |
|
|
Jul 06 04:53:10 PM PDT 24 |
Jul 06 04:57:09 PM PDT 24 |
7439148127 ps |
| T852 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3996022110 |
|
|
Jul 06 04:53:42 PM PDT 24 |
Jul 06 04:54:57 PM PDT 24 |
142208440 ps |
| T853 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3347557714 |
|
|
Jul 06 04:56:33 PM PDT 24 |
Jul 06 05:01:04 PM PDT 24 |
12163375295 ps |
| T854 |
/workspace/coverage/default/8.sram_ctrl_regwen.38457677 |
|
|
Jul 06 04:53:07 PM PDT 24 |
Jul 06 04:58:30 PM PDT 24 |
1880460695 ps |
| T855 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1101002723 |
|
|
Jul 06 04:53:06 PM PDT 24 |
Jul 06 04:53:07 PM PDT 24 |
15144506 ps |
| T856 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3022956312 |
|
|
Jul 06 04:55:07 PM PDT 24 |
Jul 06 04:59:33 PM PDT 24 |
20885480081 ps |
| T857 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1876995374 |
|
|
Jul 06 04:55:16 PM PDT 24 |
Jul 06 05:00:19 PM PDT 24 |
3747377287 ps |
| T858 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3120022006 |
|
|
Jul 06 04:55:53 PM PDT 24 |
Jul 06 04:55:56 PM PDT 24 |
1322613519 ps |
| T859 |
/workspace/coverage/default/34.sram_ctrl_executable.1707196034 |
|
|
Jul 06 04:54:49 PM PDT 24 |
Jul 06 05:02:23 PM PDT 24 |
46464790029 ps |
| T860 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2893036895 |
|
|
Jul 06 04:55:46 PM PDT 24 |
Jul 06 04:55:49 PM PDT 24 |
127733048 ps |
| T861 |
/workspace/coverage/default/26.sram_ctrl_alert_test.4070198378 |
|
|
Jul 06 04:54:11 PM PDT 24 |
Jul 06 04:54:12 PM PDT 24 |
11854754 ps |
| T862 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1547724564 |
|
|
Jul 06 04:56:45 PM PDT 24 |
Jul 06 04:56:51 PM PDT 24 |
91911644 ps |
| T863 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1998121281 |
|
|
Jul 06 04:56:22 PM PDT 24 |
Jul 06 04:56:56 PM PDT 24 |
388124583 ps |
| T864 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.4018005297 |
|
|
Jul 06 04:55:15 PM PDT 24 |
Jul 06 04:55:16 PM PDT 24 |
87510420 ps |
| T865 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.423625326 |
|
|
Jul 06 04:54:34 PM PDT 24 |
Jul 06 04:59:14 PM PDT 24 |
11539325785 ps |
| T866 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.577137229 |
|
|
Jul 06 04:53:17 PM PDT 24 |
Jul 06 04:56:11 PM PDT 24 |
3510641811 ps |
| T867 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2804258580 |
|
|
Jul 06 04:52:56 PM PDT 24 |
Jul 06 05:01:14 PM PDT 24 |
37195813899 ps |
| T868 |
/workspace/coverage/default/5.sram_ctrl_partial_access.2334557569 |
|
|
Jul 06 04:53:06 PM PDT 24 |
Jul 06 04:53:10 PM PDT 24 |
558985133 ps |
| T869 |
/workspace/coverage/default/43.sram_ctrl_executable.1179018887 |
|
|
Jul 06 04:55:58 PM PDT 24 |
Jul 06 05:09:59 PM PDT 24 |
14693241700 ps |
| T870 |
/workspace/coverage/default/38.sram_ctrl_smoke.4036852116 |
|
|
Jul 06 04:55:08 PM PDT 24 |
Jul 06 04:55:15 PM PDT 24 |
761247403 ps |
| T871 |
/workspace/coverage/default/47.sram_ctrl_executable.2874592834 |
|
|
Jul 06 04:56:32 PM PDT 24 |
Jul 06 05:15:27 PM PDT 24 |
13475670591 ps |
| T872 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2815249245 |
|
|
Jul 06 04:54:06 PM PDT 24 |
Jul 06 04:54:11 PM PDT 24 |
1445906215 ps |
| T873 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2961645430 |
|
|
Jul 06 04:56:47 PM PDT 24 |
Jul 06 05:03:37 PM PDT 24 |
1099702419 ps |
| T874 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1684162777 |
|
|
Jul 06 04:53:23 PM PDT 24 |
Jul 06 04:58:25 PM PDT 24 |
988808782 ps |
| T875 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2831081442 |
|
|
Jul 06 04:53:26 PM PDT 24 |
Jul 06 04:59:05 PM PDT 24 |
4208410189 ps |
| T876 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1840390179 |
|
|
Jul 06 04:53:20 PM PDT 24 |
Jul 06 05:33:54 PM PDT 24 |
32749451304 ps |
| T877 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3120971495 |
|
|
Jul 06 04:54:48 PM PDT 24 |
Jul 06 04:55:29 PM PDT 24 |
1937442758 ps |
| T878 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2306913185 |
|
|
Jul 06 04:55:10 PM PDT 24 |
Jul 06 04:57:26 PM PDT 24 |
418276080 ps |
| T879 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2920360619 |
|
|
Jul 06 04:53:59 PM PDT 24 |
Jul 06 05:01:08 PM PDT 24 |
50140746100 ps |
| T880 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.2265163991 |
|
|
Jul 06 04:55:53 PM PDT 24 |
Jul 06 04:55:55 PM PDT 24 |
151604754 ps |
| T881 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.3066719347 |
|
|
Jul 06 04:55:00 PM PDT 24 |
Jul 06 05:22:14 PM PDT 24 |
43954966903 ps |
| T882 |
/workspace/coverage/default/11.sram_ctrl_stress_all.3982416619 |
|
|
Jul 06 04:53:11 PM PDT 24 |
Jul 06 06:14:41 PM PDT 24 |
16064206019 ps |
| T883 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.360527501 |
|
|
Jul 06 04:53:22 PM PDT 24 |
Jul 06 04:53:23 PM PDT 24 |
161215958 ps |
| T884 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.498378981 |
|
|
Jul 06 04:53:42 PM PDT 24 |
Jul 06 05:04:14 PM PDT 24 |
14949689875 ps |
| T885 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3442841599 |
|
|
Jul 06 04:54:59 PM PDT 24 |
Jul 06 04:55:33 PM PDT 24 |
104739152 ps |
| T886 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1919415052 |
|
|
Jul 06 04:53:42 PM PDT 24 |
Jul 06 05:04:37 PM PDT 24 |
1960828370 ps |
| T887 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.599749592 |
|
|
Jul 06 04:53:19 PM PDT 24 |
Jul 06 04:53:22 PM PDT 24 |
138427087 ps |
| T888 |
/workspace/coverage/default/8.sram_ctrl_smoke.3488235817 |
|
|
Jul 06 04:53:11 PM PDT 24 |
Jul 06 04:54:30 PM PDT 24 |
3055890711 ps |
| T889 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4261930427 |
|
|
Jul 06 04:53:05 PM PDT 24 |
Jul 06 05:00:52 PM PDT 24 |
1406484708 ps |
| T890 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1721899360 |
|
|
Jul 06 04:54:16 PM PDT 24 |
Jul 06 04:56:11 PM PDT 24 |
3556561096 ps |
| T891 |
/workspace/coverage/default/15.sram_ctrl_regwen.3104569031 |
|
|
Jul 06 04:53:41 PM PDT 24 |
Jul 06 05:00:48 PM PDT 24 |
1132972801 ps |
| T892 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.3385474762 |
|
|
Jul 06 04:54:26 PM PDT 24 |
Jul 06 04:59:40 PM PDT 24 |
3266074925 ps |
| T893 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2812700514 |
|
|
Jul 06 04:56:10 PM PDT 24 |
Jul 06 05:02:01 PM PDT 24 |
2558571920 ps |
| T894 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.223928952 |
|
|
Jul 06 04:52:59 PM PDT 24 |
Jul 06 04:53:02 PM PDT 24 |
503764773 ps |
| T895 |
/workspace/coverage/default/24.sram_ctrl_regwen.3285275811 |
|
|
Jul 06 04:53:58 PM PDT 24 |
Jul 06 05:04:58 PM PDT 24 |
61962840326 ps |
| T896 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1159809221 |
|
|
Jul 06 04:55:05 PM PDT 24 |
Jul 06 05:02:27 PM PDT 24 |
12444341727 ps |
| T897 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2371557672 |
|
|
Jul 06 04:53:46 PM PDT 24 |
Jul 06 04:53:47 PM PDT 24 |
28016330 ps |
| T898 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3842492044 |
|
|
Jul 06 04:53:42 PM PDT 24 |
Jul 06 04:53:54 PM PDT 24 |
1998856919 ps |
| T899 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3468949523 |
|
|
Jul 06 04:53:09 PM PDT 24 |
Jul 06 04:53:18 PM PDT 24 |
5525690110 ps |
| T900 |
/workspace/coverage/default/47.sram_ctrl_alert_test.388003257 |
|
|
Jul 06 04:56:33 PM PDT 24 |
Jul 06 04:56:33 PM PDT 24 |
15605041 ps |
| T901 |
/workspace/coverage/default/36.sram_ctrl_partial_access.3439430210 |
|
|
Jul 06 04:55:00 PM PDT 24 |
Jul 06 04:57:20 PM PDT 24 |
2597242097 ps |
| T902 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.255742961 |
|
|
Jul 06 04:53:24 PM PDT 24 |
Jul 06 04:58:49 PM PDT 24 |
3365225515 ps |
| T903 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2242575727 |
|
|
Jul 06 04:56:08 PM PDT 24 |
Jul 06 05:00:17 PM PDT 24 |
9723095528 ps |
| T904 |
/workspace/coverage/default/44.sram_ctrl_regwen.1443979386 |
|
|
Jul 06 04:56:05 PM PDT 24 |
Jul 06 05:15:50 PM PDT 24 |
10772951764 ps |
| T905 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3188220996 |
|
|
Jul 06 04:53:16 PM PDT 24 |
Jul 06 04:55:44 PM PDT 24 |
29779247246 ps |
| T906 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2683625321 |
|
|
Jul 06 04:56:39 PM PDT 24 |
Jul 06 04:56:40 PM PDT 24 |
55198188 ps |
| T907 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.438505587 |
|
|
Jul 06 04:53:14 PM PDT 24 |
Jul 06 04:57:20 PM PDT 24 |
2563769584 ps |
| T908 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.328471195 |
|
|
Jul 06 04:53:59 PM PDT 24 |
Jul 06 05:00:59 PM PDT 24 |
17890120469 ps |
| T909 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1197608491 |
|
|
Jul 06 04:53:58 PM PDT 24 |
Jul 06 04:59:11 PM PDT 24 |
8437436088 ps |
| T910 |
/workspace/coverage/default/24.sram_ctrl_executable.62965244 |
|
|
Jul 06 04:54:00 PM PDT 24 |
Jul 06 05:05:06 PM PDT 24 |
18392495273 ps |
| T911 |
/workspace/coverage/default/9.sram_ctrl_stress_all.2684394859 |
|
|
Jul 06 04:53:18 PM PDT 24 |
Jul 06 05:16:15 PM PDT 24 |
84921696435 ps |
| T912 |
/workspace/coverage/default/11.sram_ctrl_alert_test.286565495 |
|
|
Jul 06 04:53:19 PM PDT 24 |
Jul 06 04:53:21 PM PDT 24 |
30960345 ps |
| T913 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.4042658115 |
|
|
Jul 06 04:55:06 PM PDT 24 |
Jul 06 04:55:11 PM PDT 24 |
304472661 ps |
| T914 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3447516179 |
|
|
Jul 06 04:56:10 PM PDT 24 |
Jul 06 06:16:16 PM PDT 24 |
115666779833 ps |
| T915 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.4287842712 |
|
|
Jul 06 04:55:22 PM PDT 24 |
Jul 06 04:55:32 PM PDT 24 |
874222022 ps |
| T916 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.141144942 |
|
|
Jul 06 04:53:15 PM PDT 24 |
Jul 06 04:53:16 PM PDT 24 |
31009983 ps |
| T917 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.736014962 |
|
|
Jul 06 04:54:03 PM PDT 24 |
Jul 06 05:00:30 PM PDT 24 |
3065324958 ps |
| T918 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2740891388 |
|
|
Jul 06 04:53:11 PM PDT 24 |
Jul 06 04:53:12 PM PDT 24 |
47784828 ps |
| T919 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3041941843 |
|
|
Jul 06 04:55:41 PM PDT 24 |
Jul 06 05:07:41 PM PDT 24 |
4287207653 ps |
| T920 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2978039917 |
|
|
Jul 06 04:53:34 PM PDT 24 |
Jul 06 04:53:36 PM PDT 24 |
189781441 ps |
| T921 |
/workspace/coverage/default/34.sram_ctrl_smoke.3654658943 |
|
|
Jul 06 04:54:49 PM PDT 24 |
Jul 06 04:54:53 PM PDT 24 |
358706398 ps |
| T922 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3245849403 |
|
|
Jul 06 04:53:35 PM PDT 24 |
Jul 06 04:53:37 PM PDT 24 |
40054869 ps |
| T923 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2301287106 |
|
|
Jul 06 04:53:04 PM PDT 24 |
Jul 06 04:53:08 PM PDT 24 |
61549735 ps |
| T924 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2408273993 |
|
|
Jul 06 04:53:09 PM PDT 24 |
Jul 06 04:53:25 PM PDT 24 |
520020145 ps |
| T925 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1017361794 |
|
|
Jul 06 04:53:14 PM PDT 24 |
Jul 06 04:56:59 PM PDT 24 |
11442687944 ps |
| T926 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2328551474 |
|
|
Jul 06 04:53:12 PM PDT 24 |
Jul 06 05:09:57 PM PDT 24 |
10739693937 ps |
| T927 |
/workspace/coverage/default/15.sram_ctrl_partial_access.1590276808 |
|
|
Jul 06 04:53:31 PM PDT 24 |
Jul 06 04:53:53 PM PDT 24 |
15525567225 ps |
| T928 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2996011650 |
|
|
Jul 06 04:53:03 PM PDT 24 |
Jul 06 04:53:09 PM PDT 24 |
97803941 ps |
| T58 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1183395554 |
|
|
Jul 06 04:52:14 PM PDT 24 |
Jul 06 04:52:16 PM PDT 24 |
29824949 ps |
| T929 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3280969803 |
|
|
Jul 06 04:52:13 PM PDT 24 |
Jul 06 04:52:15 PM PDT 24 |
53144136 ps |
| T930 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4115854568 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:19 PM PDT 24 |
37122423 ps |
| T59 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1463877856 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:08 PM PDT 24 |
33712983 ps |
| T55 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.409488315 |
|
|
Jul 06 04:52:14 PM PDT 24 |
Jul 06 04:52:16 PM PDT 24 |
145092272 ps |
| T56 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2668306879 |
|
|
Jul 06 04:52:03 PM PDT 24 |
Jul 06 04:52:06 PM PDT 24 |
364518159 ps |
| T931 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2238721598 |
|
|
Jul 06 04:52:11 PM PDT 24 |
Jul 06 04:52:14 PM PDT 24 |
31570907 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3275899262 |
|
|
Jul 06 04:52:14 PM PDT 24 |
Jul 06 04:52:16 PM PDT 24 |
215581926 ps |
| T932 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1492958575 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:09 PM PDT 24 |
42501104 ps |
| T933 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2975589039 |
|
|
Jul 06 04:52:18 PM PDT 24 |
Jul 06 04:52:20 PM PDT 24 |
29817792 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1774905147 |
|
|
Jul 06 04:51:55 PM PDT 24 |
Jul 06 04:51:56 PM PDT 24 |
35552815 ps |
| T75 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3878003982 |
|
|
Jul 06 04:52:02 PM PDT 24 |
Jul 06 04:52:03 PM PDT 24 |
12649009 ps |
| T934 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3950665878 |
|
|
Jul 06 04:52:18 PM PDT 24 |
Jul 06 04:52:20 PM PDT 24 |
38070072 ps |
| T935 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2310060773 |
|
|
Jul 06 04:52:02 PM PDT 24 |
Jul 06 04:52:06 PM PDT 24 |
235514195 ps |
| T936 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.407354789 |
|
|
Jul 06 04:52:13 PM PDT 24 |
Jul 06 04:52:17 PM PDT 24 |
102180979 ps |
| T76 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2070415463 |
|
|
Jul 06 04:52:12 PM PDT 24 |
Jul 06 04:52:16 PM PDT 24 |
6144540038 ps |
| T77 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1251915661 |
|
|
Jul 06 04:52:23 PM PDT 24 |
Jul 06 04:52:24 PM PDT 24 |
16044833 ps |
| T103 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2972864555 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:19 PM PDT 24 |
24042472 ps |
| T93 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2677323863 |
|
|
Jul 06 04:52:05 PM PDT 24 |
Jul 06 04:52:06 PM PDT 24 |
21185127 ps |
| T78 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3902255795 |
|
|
Jul 06 04:52:02 PM PDT 24 |
Jul 06 04:52:03 PM PDT 24 |
14437694 ps |
| T57 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1380433823 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:08 PM PDT 24 |
705381056 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.872923247 |
|
|
Jul 06 04:52:16 PM PDT 24 |
Jul 06 04:52:18 PM PDT 24 |
79695557 ps |
| T79 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3349717380 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:07 PM PDT 24 |
63842823 ps |
| T94 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3072103049 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:22 PM PDT 24 |
4310340101 ps |
| T937 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1298184356 |
|
|
Jul 06 04:52:00 PM PDT 24 |
Jul 06 04:52:01 PM PDT 24 |
47916379 ps |
| T938 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2911422280 |
|
|
Jul 06 04:52:00 PM PDT 24 |
Jul 06 04:52:01 PM PDT 24 |
22607921 ps |
| T80 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2023462379 |
|
|
Jul 06 04:52:19 PM PDT 24 |
Jul 06 04:52:21 PM PDT 24 |
221707436 ps |
| T81 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2614086014 |
|
|
Jul 06 04:52:12 PM PDT 24 |
Jul 06 04:52:15 PM PDT 24 |
210153923 ps |
| T939 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1201339746 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:20 PM PDT 24 |
65721374 ps |
| T95 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.276442086 |
|
|
Jul 06 04:52:00 PM PDT 24 |
Jul 06 04:52:01 PM PDT 24 |
20205445 ps |
| T940 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.707777990 |
|
|
Jul 06 04:52:00 PM PDT 24 |
Jul 06 04:52:03 PM PDT 24 |
486594361 ps |
| T112 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3083311781 |
|
|
Jul 06 04:52:16 PM PDT 24 |
Jul 06 04:52:19 PM PDT 24 |
344700000 ps |
| T941 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.802359817 |
|
|
Jul 06 04:52:14 PM PDT 24 |
Jul 06 04:52:16 PM PDT 24 |
24922394 ps |
| T113 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1155251683 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:19 PM PDT 24 |
83143677 ps |
| T942 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.964240306 |
|
|
Jul 06 04:52:21 PM PDT 24 |
Jul 06 04:52:26 PM PDT 24 |
131271843 ps |
| T119 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3903496771 |
|
|
Jul 06 04:52:18 PM PDT 24 |
Jul 06 04:52:20 PM PDT 24 |
96686679 ps |
| T943 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3832523496 |
|
|
Jul 06 04:52:11 PM PDT 24 |
Jul 06 04:52:12 PM PDT 24 |
33297226 ps |
| T82 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3659228098 |
|
|
Jul 06 04:52:21 PM PDT 24 |
Jul 06 04:52:22 PM PDT 24 |
14854782 ps |
| T944 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2598557725 |
|
|
Jul 06 04:52:27 PM PDT 24 |
Jul 06 04:52:28 PM PDT 24 |
15367191 ps |
| T945 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3333675455 |
|
|
Jul 06 04:52:11 PM PDT 24 |
Jul 06 04:52:13 PM PDT 24 |
18401961 ps |
| T946 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.843824652 |
|
|
Jul 06 04:52:13 PM PDT 24 |
Jul 06 04:52:16 PM PDT 24 |
129301273 ps |
| T83 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2803263983 |
|
|
Jul 06 04:52:07 PM PDT 24 |
Jul 06 04:52:11 PM PDT 24 |
1748888883 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4110253708 |
|
|
Jul 06 04:51:55 PM PDT 24 |
Jul 06 04:51:56 PM PDT 24 |
40230380 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2015388190 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:21 PM PDT 24 |
98627288 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.70893981 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:09 PM PDT 24 |
133881649 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2069960998 |
|
|
Jul 06 04:52:02 PM PDT 24 |
Jul 06 04:52:03 PM PDT 24 |
44941724 ps |
| T84 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1973986161 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:20 PM PDT 24 |
799316631 ps |
| T89 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.149580429 |
|
|
Jul 06 04:52:19 PM PDT 24 |
Jul 06 04:52:21 PM PDT 24 |
228457377 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2783736250 |
|
|
Jul 06 04:51:56 PM PDT 24 |
Jul 06 04:51:58 PM PDT 24 |
48002315 ps |
| T952 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2595846193 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:19 PM PDT 24 |
45047693 ps |
| T953 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1229222120 |
|
|
Jul 06 04:52:08 PM PDT 24 |
Jul 06 04:52:09 PM PDT 24 |
53413148 ps |
| T954 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1241038742 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:19 PM PDT 24 |
17655005 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2201082996 |
|
|
Jul 06 04:51:59 PM PDT 24 |
Jul 06 04:52:00 PM PDT 24 |
35546471 ps |
| T956 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.674981162 |
|
|
Jul 06 04:52:18 PM PDT 24 |
Jul 06 04:52:21 PM PDT 24 |
34648844 ps |
| T117 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3033782540 |
|
|
Jul 06 04:52:13 PM PDT 24 |
Jul 06 04:52:16 PM PDT 24 |
236599176 ps |
| T957 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2819613618 |
|
|
Jul 06 04:52:16 PM PDT 24 |
Jul 06 04:52:18 PM PDT 24 |
27899303 ps |
| T958 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1595332813 |
|
|
Jul 06 04:52:07 PM PDT 24 |
Jul 06 04:52:09 PM PDT 24 |
35493094 ps |
| T118 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3456468742 |
|
|
Jul 06 04:52:16 PM PDT 24 |
Jul 06 04:52:19 PM PDT 24 |
215262081 ps |
| T114 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1047989282 |
|
|
Jul 06 04:52:14 PM PDT 24 |
Jul 06 04:52:17 PM PDT 24 |
229724663 ps |
| T959 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1142061404 |
|
|
Jul 06 04:52:00 PM PDT 24 |
Jul 06 04:52:03 PM PDT 24 |
210497715 ps |
| T960 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2131888221 |
|
|
Jul 06 04:52:12 PM PDT 24 |
Jul 06 04:52:17 PM PDT 24 |
134882576 ps |
| T961 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3655518218 |
|
|
Jul 06 04:52:20 PM PDT 24 |
Jul 06 04:52:21 PM PDT 24 |
11318736 ps |
| T962 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2737688335 |
|
|
Jul 06 04:52:15 PM PDT 24 |
Jul 06 04:52:17 PM PDT 24 |
32298214 ps |
| T120 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.681659459 |
|
|
Jul 06 04:51:55 PM PDT 24 |
Jul 06 04:51:57 PM PDT 24 |
514099959 ps |
| T963 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4252038313 |
|
|
Jul 06 04:52:16 PM PDT 24 |
Jul 06 04:52:18 PM PDT 24 |
34482914 ps |
| T964 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2101987349 |
|
|
Jul 06 04:52:12 PM PDT 24 |
Jul 06 04:52:13 PM PDT 24 |
53708494 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2707019225 |
|
|
Jul 06 04:51:59 PM PDT 24 |
Jul 06 04:52:01 PM PDT 24 |
81993901 ps |
| T966 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1890259603 |
|
|
Jul 06 04:52:03 PM PDT 24 |
Jul 06 04:52:06 PM PDT 24 |
888405305 ps |
| T90 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2482124059 |
|
|
Jul 06 04:51:57 PM PDT 24 |
Jul 06 04:52:01 PM PDT 24 |
400083054 ps |
| T967 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1956316617 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:18 PM PDT 24 |
38558208 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1498184941 |
|
|
Jul 06 04:51:56 PM PDT 24 |
Jul 06 04:52:01 PM PDT 24 |
128949435 ps |
| T969 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1245204077 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:07 PM PDT 24 |
44308883 ps |
| T970 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2172664905 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:07 PM PDT 24 |
28601461 ps |
| T971 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3769674861 |
|
|
Jul 06 04:52:07 PM PDT 24 |
Jul 06 04:52:10 PM PDT 24 |
28780526 ps |
| T122 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1291436684 |
|
|
Jul 06 04:52:24 PM PDT 24 |
Jul 06 04:52:26 PM PDT 24 |
153303680 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1162302822 |
|
|
Jul 06 04:52:14 PM PDT 24 |
Jul 06 04:52:16 PM PDT 24 |
28024991 ps |
| T973 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3766045358 |
|
|
Jul 06 04:52:10 PM PDT 24 |
Jul 06 04:52:13 PM PDT 24 |
76387968 ps |
| T974 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.373836407 |
|
|
Jul 06 04:52:07 PM PDT 24 |
Jul 06 04:52:10 PM PDT 24 |
406866754 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3960754470 |
|
|
Jul 06 04:52:00 PM PDT 24 |
Jul 06 04:52:01 PM PDT 24 |
29514570 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2245365845 |
|
|
Jul 06 04:51:55 PM PDT 24 |
Jul 06 04:51:58 PM PDT 24 |
167732431 ps |
| T121 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3836374016 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:20 PM PDT 24 |
139390632 ps |
| T977 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2647229339 |
|
|
Jul 06 04:52:27 PM PDT 24 |
Jul 06 04:52:32 PM PDT 24 |
49495812 ps |
| T978 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3019786691 |
|
|
Jul 06 04:52:00 PM PDT 24 |
Jul 06 04:52:01 PM PDT 24 |
30159227 ps |
| T979 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3530889793 |
|
|
Jul 06 04:52:15 PM PDT 24 |
Jul 06 04:52:17 PM PDT 24 |
52475108 ps |
| T980 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.923962480 |
|
|
Jul 06 04:51:59 PM PDT 24 |
Jul 06 04:52:00 PM PDT 24 |
39299082 ps |
| T981 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2644340153 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:18 PM PDT 24 |
41833938 ps |
| T982 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1838311725 |
|
|
Jul 06 04:52:18 PM PDT 24 |
Jul 06 04:52:19 PM PDT 24 |
14497114 ps |
| T115 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2974749597 |
|
|
Jul 06 04:52:13 PM PDT 24 |
Jul 06 04:52:15 PM PDT 24 |
127833408 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.385829439 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:22 PM PDT 24 |
107726641 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2742709545 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:10 PM PDT 24 |
286281592 ps |
| T985 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3550693074 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:08 PM PDT 24 |
55415787 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3200886561 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:08 PM PDT 24 |
76835897 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3510336449 |
|
|
Jul 06 04:52:13 PM PDT 24 |
Jul 06 04:52:15 PM PDT 24 |
20726447 ps |
| T988 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4142793577 |
|
|
Jul 06 04:52:20 PM PDT 24 |
Jul 06 04:52:22 PM PDT 24 |
320040946 ps |
| T989 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.544106998 |
|
|
Jul 06 04:52:17 PM PDT 24 |
Jul 06 04:52:20 PM PDT 24 |
227893383 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3396656294 |
|
|
Jul 06 04:52:19 PM PDT 24 |
Jul 06 04:52:20 PM PDT 24 |
17989689 ps |
| T91 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4055350801 |
|
|
Jul 06 04:52:15 PM PDT 24 |
Jul 06 04:52:17 PM PDT 24 |
12974356 ps |
| T991 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1072101205 |
|
|
Jul 06 04:52:05 PM PDT 24 |
Jul 06 04:52:08 PM PDT 24 |
358213947 ps |
| T992 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.810865667 |
|
|
Jul 06 04:52:07 PM PDT 24 |
Jul 06 04:52:09 PM PDT 24 |
13612454 ps |
| T993 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.865587077 |
|
|
Jul 06 04:52:20 PM PDT 24 |
Jul 06 04:52:21 PM PDT 24 |
57053344 ps |
| T994 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.160552581 |
|
|
Jul 06 04:52:06 PM PDT 24 |
Jul 06 04:52:08 PM PDT 24 |
15428192 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.250718334 |
|
|
Jul 06 04:51:56 PM PDT 24 |
Jul 06 04:51:58 PM PDT 24 |
259940098 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1195627626 |
|
|
Jul 06 04:52:15 PM PDT 24 |
Jul 06 04:52:17 PM PDT 24 |
95466621 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3792150286 |
|
|
Jul 06 04:52:12 PM PDT 24 |
Jul 06 04:52:15 PM PDT 24 |
794642299 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3665772748 |
|
|
Jul 06 04:52:01 PM PDT 24 |
Jul 06 04:52:04 PM PDT 24 |
20977374 ps |
| T999 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3971367981 |
|
|
Jul 06 04:52:13 PM PDT 24 |
Jul 06 04:52:15 PM PDT 24 |
27536433 ps |
| T1000 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.596135185 |
|
|
Jul 06 04:52:11 PM PDT 24 |
Jul 06 04:52:13 PM PDT 24 |
33032007 ps |
| T1001 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2885554263 |
|
|
Jul 06 04:52:21 PM PDT 24 |
Jul 06 04:52:22 PM PDT 24 |
16470266 ps |
| T1002 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.727226445 |
|
|
Jul 06 04:52:14 PM PDT 24 |
Jul 06 04:52:18 PM PDT 24 |
1840096694 ps |