Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147367480	1			T1	11544		T2	6142		T3	337714
instr_valid_dis	117126949	1			T1	11544		T2	6142		T3	337714
instr_en	21754692	1			T21	613716		T147	11450		T46	153708

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10768442	1			T12	11508		T21	62964		T28	20000
sram_ifetch_valid_disable	114755991	1			T1	11544		T2	6142		T3	337714
sram_ifetch_enable	21843047	1			T12	109398		T21	399306		T28	164106

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147367480	1			T1	11544		T2	6142		T3	337714
hw_debug_en_valid_off	115025733	1			T1	11544		T2	6142		T3	337714
hw_debug_en_on	21041141	1			T12	211014		T21	123382		T28	68020

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114755991	1			T1	11544		T2	6142		T3	337714
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102788813	1			T1	11544		T2	6142		T3	337714
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8406762	1			T21	151446		T147	11450		T46	38516
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4053562	1			T21	62964		T28	20000		T47	30970
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1854362	1			T28	20000		T74	36962		T129	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1540560	1			T21	62964		T47	30970		T139	51316
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4501206	1			T12	11508		T46	15082		T47	2652
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1846454	1			T12	11508		T139	9662		T129	14356
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1838156	1			T46	15082		T47	2652		T142	30912
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8239576	1			T12	143318		T21	72490		T28	48334
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3842788	1			T12	143318		T28	48334		T74	24346
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3054916	1			T21	72490		T46	38516		T47	108554

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9275934	1			T21	399306		T46	100110		T47	75880
lc_exec_en	8300359	1			T12	56188		T21	50892		T28	19686
valid_exec_dis	111034965	1			T1	11544		T2	6142		T3	337714
invalid_exec_dis	32611489	1			T12	120906		T21	462270		T28	184106