Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44512197	1			T1	1042		T2	3071		T3	30716
triple_byte_access	2489857	1			T1	928		T3	27545		T12	2038
halfword_access	3731798	1			T1	1415		T3	41308		T12	2714
byte_access	4982905	1			T1	1886		T3	55531		T12	3721
zero_access	1256654	1			T1	501		T3	13757		T12	897

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28440974

1

T1

2941

T2

1024

T3

84814

auto[1]

28532437

1

T1

2831

T2

2047

T3

84043

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22210020	1			T1	535		T2	1024		T3	15476
auto[0]	triple_byte_access	1241505	1			T1	470		T3	13735		T12	1032
auto[0]	halfword_access	1862359	1			T1	730		T3	20692		T12	1347
auto[0]	byte_access	2494067	1			T1	956		T3	27901		T12	1836
auto[0]	zero_access	633023	1			T1	250		T3	7010		T12	447
auto[1]	word_access	22302177	1			T1	507		T2	2047		T3	15240
auto[1]	triple_byte_access	1248352	1			T1	458		T3	13810		T12	1006
auto[1]	halfword_access	1869439	1			T1	685		T3	20616		T12	1367
auto[1]	byte_access	2488838	1			T1	930		T3	27630		T12	1885
auto[1]	zero_access	623631	1			T1	251		T3	6747		T12	450