Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14522730	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

60146303

1

T1

157389

T2

2511

T3

93876

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37228543	1			T1	86194		T2	1389		T3	51464
values[0x0]	17267506	1			T1	41822		T2	649		T3	24959
values[0x1]	20172984	1			T1	45220		T2	730		T3	26895

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7235466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67433567

1

T1

165311

T2

2637

T3

98657

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	298966	1			T1	675		T2	10		T3	378
valid_sources[0x01]	272246	1			T1	682		T2	7		T3	380
valid_sources[0x02]	258346	1			T1	657		T2	8		T3	486
valid_sources[0x03]	318128	1			T1	661		T2	7		T3	399
valid_sources[0x04]	257629	1			T1	724		T2	18		T3	350
valid_sources[0x05]	277191	1			T1	687		T2	6		T3	396
valid_sources[0x06]	343249	1			T1	689		T2	18		T3	392
valid_sources[0x07]	280170	1			T1	709		T2	7		T3	371
valid_sources[0x08]	322916	1			T1	653		T2	8		T3	431
valid_sources[0x09]	340173	1			T1	652		T2	9		T3	404
valid_sources[0x0a]	310073	1			T1	678		T2	7		T3	392
valid_sources[0x0b]	262000	1			T1	724		T2	10		T3	449
valid_sources[0x0c]	286362	1			T1	685		T2	10		T3	442
valid_sources[0x0d]	287456	1			T1	654		T2	7		T3	364
valid_sources[0x0e]	264807	1			T1	648		T2	3		T3	308
valid_sources[0x0f]	271589	1			T1	684		T2	9		T3	336
valid_sources[0x10]	337277	1			T1	684		T2	5		T3	361
valid_sources[0x11]	290692	1			T1	674		T2	10		T3	474
valid_sources[0x12]	310460	1			T1	690		T2	14		T3	468
valid_sources[0x13]	266435	1			T1	668		T2	11		T3	340
valid_sources[0x14]	278797	1			T1	655		T2	8		T3	400
valid_sources[0x15]	261223	1			T1	743		T2	14		T3	414
valid_sources[0x16]	318298	1			T1	665		T2	8		T3	340
valid_sources[0x17]	297909	1			T1	705		T2	10		T3	378
valid_sources[0x18]	267202	1			T1	701		T2	11		T3	417
valid_sources[0x19]	333280	1			T1	699		T2	5		T3	497
valid_sources[0x1a]	292691	1			T1	707		T2	13		T3	369
valid_sources[0x1b]	256597	1			T1	723		T2	12		T3	491
valid_sources[0x1c]	288617	1			T1	686		T2	12		T3	407
valid_sources[0x1d]	389460	1			T1	731		T2	10		T3	332
valid_sources[0x1e]	285894	1			T1	668		T2	14		T3	460
valid_sources[0x1f]	271207	1			T1	673		T2	13		T3	492
valid_sources[0x20]	251720	1			T1	664		T2	16		T3	511
valid_sources[0x21]	293580	1			T1	678		T2	11		T3	298
valid_sources[0x22]	294080	1			T1	708		T2	16		T3	474
valid_sources[0x23]	340404	1			T1	672		T2	21		T3	428
valid_sources[0x24]	283138	1			T1	715		T2	10		T3	441
valid_sources[0x25]	278694	1			T1	701		T2	10		T3	371
valid_sources[0x26]	283427	1			T1	679		T2	12		T3	416
valid_sources[0x27]	279775	1			T1	640		T2	6		T3	424
valid_sources[0x28]	282656	1			T1	687		T2	19		T3	394
valid_sources[0x29]	350667	1			T1	679		T2	7		T3	421
valid_sources[0x2a]	386961	1			T1	610		T2	9		T3	398
valid_sources[0x2b]	297281	1			T1	654		T2	12		T3	419
valid_sources[0x2c]	264806	1			T1	651		T2	19		T3	400
valid_sources[0x2d]	263326	1			T1	683		T2	19		T3	358
valid_sources[0x2e]	314199	1			T1	686		T2	5		T3	517
valid_sources[0x2f]	271219	1			T1	652		T2	5		T3	506
valid_sources[0x30]	259632	1			T1	702		T2	6		T3	413
valid_sources[0x31]	263357	1			T1	680		T2	12		T3	443
valid_sources[0x32]	287069	1			T1	661		T2	13		T3	418
valid_sources[0x33]	346015	1			T1	701		T2	11		T3	313
valid_sources[0x34]	284815	1			T1	674		T2	8		T3	433
valid_sources[0x35]	306105	1			T1	637		T2	10		T3	313
valid_sources[0x36]	306416	1			T1	672		T2	8		T3	370
valid_sources[0x37]	302212	1			T1	728		T2	8		T3	426
valid_sources[0x38]	276770	1			T1	650		T2	7		T3	385
valid_sources[0x39]	285025	1			T1	632		T2	14		T3	537
valid_sources[0x3a]	277327	1			T1	641		T2	9		T3	421
valid_sources[0x3b]	260294	1			T1	693		T2	12		T3	373
valid_sources[0x3c]	369453	1			T1	589		T2	6		T3	425
valid_sources[0x3d]	295708	1			T1	608		T2	5		T3	391
valid_sources[0x3e]	282332	1			T1	629		T2	11		T3	460
valid_sources[0x3f]	269378	1			T1	670		T2	7		T3	389
valid_sources[0x40]	317672	1			T1	656		T2	21		T3	299
valid_sources[0x41]	307881	1			T1	690		T2	7		T3	546
valid_sources[0x42]	328502	1			T1	633		T2	10		T3	406
valid_sources[0x43]	285459	1			T1	661		T2	5		T3	499
valid_sources[0x44]	317636	1			T1	706		T2	9		T3	500
valid_sources[0x45]	266927	1			T1	719		T2	14		T3	464
valid_sources[0x46]	249648	1			T1	699		T2	17		T3	342
valid_sources[0x47]	330220	1			T1	663		T2	11		T3	386
valid_sources[0x48]	304017	1			T1	697		T2	19		T3	470
valid_sources[0x49]	319761	1			T1	669		T2	2		T3	359
valid_sources[0x4a]	269574	1			T1	704		T2	17		T3	397
valid_sources[0x4b]	301083	1			T1	717		T2	12		T3	320
valid_sources[0x4c]	317921	1			T1	699		T2	14		T3	404
valid_sources[0x4d]	282441	1			T1	665		T2	11		T3	453
valid_sources[0x4e]	264426	1			T1	690		T2	12		T3	496
valid_sources[0x4f]	323167	1			T1	667		T2	10		T3	349
valid_sources[0x50]	324256	1			T1	688		T2	7		T3	340
valid_sources[0x51]	283467	1			T1	703		T2	12		T3	338
valid_sources[0x52]	298042	1			T1	652		T2	12		T3	418
valid_sources[0x53]	277167	1			T1	676		T2	9		T3	386
valid_sources[0x54]	269729	1			T1	682		T2	11		T3	338
valid_sources[0x55]	257925	1			T1	659		T2	12		T3	576
valid_sources[0x56]	279980	1			T1	606		T2	8		T3	405
valid_sources[0x57]	253051	1			T1	665		T2	13		T3	461
valid_sources[0x58]	279918	1			T1	690		T2	8		T3	434
valid_sources[0x59]	254374	1			T1	654		T2	18		T3	433
valid_sources[0x5a]	305264	1			T1	664		T2	13		T3	444
valid_sources[0x5b]	301035	1			T1	684		T2	10		T3	415
valid_sources[0x5c]	266924	1			T1	664		T2	8		T3	379
valid_sources[0x5d]	284402	1			T1	684		T2	10		T3	383
valid_sources[0x5e]	296431	1			T1	644		T2	16		T3	483
valid_sources[0x5f]	344887	1			T1	703		T2	11		T3	335
valid_sources[0x60]	258571	1			T1	624		T2	8		T3	432
valid_sources[0x61]	273102	1			T1	722		T2	9		T3	441
valid_sources[0x62]	297500	1			T1	638		T2	8		T3	381
valid_sources[0x63]	300489	1			T1	725		T2	9		T3	370
valid_sources[0x64]	263835	1			T1	670		T2	10		T3	436
valid_sources[0x65]	337511	1			T1	657		T2	12		T3	389
valid_sources[0x66]	275652	1			T1	642		T2	12		T3	385
valid_sources[0x67]	276974	1			T1	684		T2	13		T3	387
valid_sources[0x68]	292770	1			T1	686		T2	17		T3	492
valid_sources[0x69]	289306	1			T1	648		T2	8		T3	360
valid_sources[0x6a]	308654	1			T1	676		T2	17		T3	334
valid_sources[0x6b]	296097	1			T1	667		T2	12		T3	371
valid_sources[0x6c]	309928	1			T1	643		T2	6		T3	383
valid_sources[0x6d]	273394	1			T1	685		T2	16		T3	392
valid_sources[0x6e]	282598	1			T1	700		T2	11		T3	356
valid_sources[0x6f]	292749	1			T1	682		T2	9		T3	436
valid_sources[0x70]	263671	1			T1	667		T2	9		T3	384
valid_sources[0x71]	295792	1			T1	674		T2	11		T3	357
valid_sources[0x72]	323180	1			T1	654		T2	11		T3	375
valid_sources[0x73]	306569	1			T1	681		T2	8		T3	399
valid_sources[0x74]	290665	1			T1	678		T2	13		T3	490
valid_sources[0x75]	263301	1			T1	668		T2	14		T3	373
valid_sources[0x76]	360698	1			T1	649		T2	10		T3	466
valid_sources[0x77]	289062	1			T1	656		T2	7		T3	390
valid_sources[0x78]	283913	1			T1	693		T2	8		T3	380
valid_sources[0x79]	366923	1			T1	688		T2	12		T3	318
valid_sources[0x7a]	299798	1			T1	771		T2	4		T3	396
valid_sources[0x7b]	324055	1			T1	642		T2	14		T3	364
valid_sources[0x7c]	285408	1			T1	701		T2	8		T3	354
valid_sources[0x7d]	285996	1			T1	645		T2	18		T3	434
valid_sources[0x7e]	260934	1			T1	696		T2	7		T3	366
valid_sources[0x7f]	270699	1			T1	668		T2	6		T3	387
valid_sources[0x80]	280916	1			T1	656		T2	13		T3	429

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29971442

1

T1

78396

T2

1258

T3

46721

values[0x0]

all_enables

biggest_size

15089032

1

T1

39421

T2

613

T3

23583

values[0x1]

all_enables

biggest_size

15085829

1

T1

39572

T2

640

T3

23572

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34789	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

111239

1

T2

17

T3

28

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43339	1			T2	26		T3	16		T5	52
values[0x0]	49201	1			T1	3		T2	10		T3	31
values[0x1]	53488	1			T1	1		T2	13		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26677	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

119351

1

T1

1

T2

21

T3

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	389	1			T17	2		T148	5		T21	20
valid_sources[0x01]	526	1			T9	3		T17	4		T129	2
valid_sources[0x02]	452	1			T5	1		T9	1		T112	1
valid_sources[0x03]	490	1			T5	1		T17	2		T129	1
valid_sources[0x04]	476	1			T5	2		T18	2		T129	2
valid_sources[0x05]	542	1			T5	1		T9	2		T21	9
valid_sources[0x06]	462	1			T5	2		T9	1		T17	1
valid_sources[0x07]	804	1			T9	1		T18	2		T150	1
valid_sources[0x08]	647	1			T16	1		T17	1		T129	2
valid_sources[0x09]	557	1			T5	5		T42	1		T17	1
valid_sources[0x0a]	381	1			T9	2		T11	2		T151	2
valid_sources[0x0b]	871	1			T9	4		T21	10		T84	3
valid_sources[0x0c]	382	1			T2	1		T57	1		T17	3
valid_sources[0x0d]	674	1			T8	1		T19	1		T66	1
valid_sources[0x0e]	536	1			T150	2		T38	1		T101	1
valid_sources[0x0f]	492	1			T10	1		T16	1		T100	1
valid_sources[0x10]	468	1			T5	2		T8	1		T9	2
valid_sources[0x11]	878	1			T9	1		T10	1		T38	1
valid_sources[0x12]	559	1			T5	1		T9	2		T17	1
valid_sources[0x13]	711	1			T17	2		T129	1		T21	10
valid_sources[0x14]	684	1			T9	1		T10	1		T18	2
valid_sources[0x15]	600	1			T1	1		T9	1		T129	1
valid_sources[0x16]	544	1			T2	1		T9	2		T17	1
valid_sources[0x17]	361	1			T19	4		T17	1		T39	1
valid_sources[0x18]	384	1			T17	2		T21	11		T128	1
valid_sources[0x19]	596	1			T5	9		T9	1		T18	2
valid_sources[0x1a]	857	1			T1	1		T9	2		T17	2
valid_sources[0x1b]	426	1			T9	2		T56	1		T100	1
valid_sources[0x1c]	358	1			T19	2		T21	10		T152	2
valid_sources[0x1d]	1061	1			T17	1		T129	1		T21	6
valid_sources[0x1e]	461	1			T10	1		T17	1		T21	33
valid_sources[0x1f]	478	1			T10	1		T21	14		T153	2
valid_sources[0x20]	657	1			T9	2		T150	1		T129	1
valid_sources[0x21]	525	1			T5	2		T10	1		T57	1
valid_sources[0x22]	511	1			T8	1		T16	1		T146	3
valid_sources[0x23]	454	1			T9	2		T100	1		T21	12
valid_sources[0x24]	817	1			T21	18		T78	3		T22	67
valid_sources[0x25]	521	1			T129	1		T100	2		T21	13
valid_sources[0x26]	751	1			T2	1		T18	1		T17	2
valid_sources[0x27]	791	1			T9	1		T18	2		T148	2
valid_sources[0x28]	594	1			T9	1		T16	1		T17	1
valid_sources[0x29]	451	1			T5	1		T17	1		T100	1
valid_sources[0x2a]	501	1			T2	1		T10	1		T18	1
valid_sources[0x2b]	401	1			T18	1		T154	16		T21	11
valid_sources[0x2c]	635	1			T17	1		T21	22		T84	2
valid_sources[0x2d]	453	1			T5	3		T9	2		T57	1
valid_sources[0x2e]	1096	1			T9	1		T40	1		T151	10
valid_sources[0x2f]	753	1			T5	2		T9	1		T18	1
valid_sources[0x30]	666	1			T155	1		T21	13		T22	3
valid_sources[0x31]	522	1			T5	3		T16	1		T129	1
valid_sources[0x32]	364	1			T9	2		T156	1		T72	2
valid_sources[0x33]	337	1			T2	1		T5	1		T9	1
valid_sources[0x34]	439	1			T157	1		T21	8		T158	20
valid_sources[0x35]	700	1			T9	2		T18	1		T17	1
valid_sources[0x36]	464	1			T19	2		T17	2		T129	2
valid_sources[0x37]	536	1			T9	2		T17	1		T21	12
valid_sources[0x38]	1057	1			T19	1		T129	1		T40	1
valid_sources[0x39]	541	1			T149	8		T21	7		T128	2
valid_sources[0x3a]	1121	1			T5	3		T9	1		T18	1
valid_sources[0x3b]	548	1			T2	1		T9	1		T17	2
valid_sources[0x3c]	507	1			T9	2		T43	1		T19	1
valid_sources[0x3d]	896	1			T2	2		T41	36		T66	1
valid_sources[0x3e]	663	1			T9	3		T21	8		T152	1
valid_sources[0x3f]	362	1			T8	1		T19	2		T21	7
valid_sources[0x40]	879	1			T5	1		T10	1		T19	3
valid_sources[0x41]	572	1			T17	1		T39	1		T148	5
valid_sources[0x42]	415	1			T9	1		T42	1		T159	17
valid_sources[0x43]	517	1			T19	1		T17	3		T66	1
valid_sources[0x44]	904	1			T5	2		T100	1		T21	13
valid_sources[0x45]	557	1			T38	1		T21	17		T80	1
valid_sources[0x46]	427	1			T7	3		T5	2		T9	2
valid_sources[0x47]	362	1			T40	1		T21	18		T22	1
valid_sources[0x48]	563	1			T16	1		T17	1		T40	1
valid_sources[0x49]	685	1			T40	1		T148	15		T21	16
valid_sources[0x4a]	492	1			T9	1		T16	1		T129	1
valid_sources[0x4b]	381	1			T9	1		T21	10		T84	1
valid_sources[0x4c]	384	1			T7	1		T39	1		T21	13
valid_sources[0x4d]	610	1			T5	1		T21	21		T22	4
valid_sources[0x4e]	563	1			T17	1		T21	24		T152	2
valid_sources[0x4f]	545	1			T9	1		T18	1		T66	1
valid_sources[0x50]	619	1			T40	1		T21	19		T160	3
valid_sources[0x51]	371	1			T2	2		T129	2		T21	11
valid_sources[0x52]	701	1			T9	2		T17	1		T156	1
valid_sources[0x53]	641	1			T17	4		T21	11		T128	1
valid_sources[0x54]	735	1			T16	1		T17	2		T129	1
valid_sources[0x55]	549	1			T5	1		T21	14		T161	4
valid_sources[0x56]	520	1			T9	1		T129	1		T21	10
valid_sources[0x57]	515	1			T72	1		T21	15		T84	3
valid_sources[0x58]	398	1			T17	2		T64	3		T21	14
valid_sources[0x59]	899	1			T18	1		T129	1		T148	8
valid_sources[0x5a]	407	1			T5	3		T9	1		T26	1
valid_sources[0x5b]	721	1			T9	1		T16	1		T17	2
valid_sources[0x5c]	584	1			T5	1		T129	2		T39	1
valid_sources[0x5d]	366	1			T10	1		T18	1		T11	7
valid_sources[0x5e]	484	1			T5	4		T18	2		T129	3
valid_sources[0x5f]	1057	1			T5	1		T9	1		T10	1
valid_sources[0x60]	556	1			T2	1		T18	2		T16	1
valid_sources[0x61]	436	1			T9	1		T17	1		T72	1
valid_sources[0x62]	670	1			T9	1		T57	1		T18	1
valid_sources[0x63]	376	1			T2	4		T56	1		T21	11
valid_sources[0x64]	907	1			T7	3		T10	1		T150	1
valid_sources[0x65]	327	1			T5	1		T9	1		T21	19
valid_sources[0x66]	383	1			T7	1		T8	2		T9	3
valid_sources[0x67]	491	1			T5	15		T16	1		T17	2
valid_sources[0x68]	659	1			T5	1		T9	1		T44	8
valid_sources[0x69]	498	1			T17	1		T40	1		T21	4
valid_sources[0x6a]	838	1			T113	3		T162	2		T21	16
valid_sources[0x6b]	609	1			T10	1		T57	1		T21	13
valid_sources[0x6c]	844	1			T5	1		T21	10		T22	1
valid_sources[0x6d]	442	1			T2	1		T7	2		T5	4
valid_sources[0x6e]	539	1			T42	1		T16	1		T40	1
valid_sources[0x6f]	405	1			T16	2		T148	31		T21	12
valid_sources[0x70]	690	1			T17	1		T21	24		T153	1
valid_sources[0x71]	655	1			T9	1		T129	3		T148	2
valid_sources[0x72]	416	1			T5	2		T9	1		T129	1
valid_sources[0x73]	474	1			T9	2		T57	1		T17	1
valid_sources[0x74]	450	1			T57	1		T17	1		T114	1
valid_sources[0x75]	580	1			T17	4		T21	18		T22	3
valid_sources[0x76]	448	1			T5	2		T9	1		T18	1
valid_sources[0x77]	639	1			T112	1		T21	14		T84	10
valid_sources[0x78]	512	1			T10	1		T56	1		T18	1
valid_sources[0x79]	361	1			T9	2		T20	2		T16	1
valid_sources[0x7a]	699	1			T5	1		T18	1		T19	5
valid_sources[0x7b]	511	1			T100	1		T101	1		T163	2
valid_sources[0x7c]	394	1			T3	31		T21	5		T153	3
valid_sources[0x7d]	847	1			T5	1		T21	27		T84	5
valid_sources[0x7e]	530	1			T2	2		T9	1		T21	9
valid_sources[0x7f]	521	1			T5	2		T9	2		T17	1
valid_sources[0x80]	743	1			T9	1		T57	1		T129	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30962

1

T2

12

T3

8

T5

27

values[0x0]

all_enables

biggest_size

40878

1

T2

3

T3

15

T7

3

values[0x1]

all_enables

biggest_size

39399

1

T2

2

T3

5

T5

6