Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14154997

1

T1

15847

T2

26

T3

7534

full_word

54993502

1

T1

157389

T2

205

T3

75292

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69148199	1			T1	173236		T2	231		T3	82826
auto[TlIntgErrCmd]	98	1			T69	6		T70	1		T71	7
auto[TlIntgErrData]	100	1			T69	9		T70	6		T71	4
auto[TlIntgErrBoth]	102	1			T69	5		T70	3		T71	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31683241

1

T1

86194

T2

110

T3

30972

auto[1]

37465258

1

T1

87042

T2

121

T3

51854

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6779658	1			T1	7798		T2	9		T3	2835
auto[TlIntgErrNone]	partial	auto[1]	7375071	1			T1	8049		T2	17		T3	4699
auto[TlIntgErrNone]	full_word	auto[0]	24903458	1			T1	78396		T2	101		T3	28137
auto[TlIntgErrNone]	full_word	auto[1]	30090012	1			T1	78993		T2	104		T3	47155
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T69	1		T70	1		T71	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T69	4		T71	5		T133	8
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T133	1		T130	1		T140	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T69	1		T141	2		T142	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T69	1		T70	2		T71	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T69	5		T70	2		T71	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T69	2		T70	1		T71	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T69	1		T70	1		T135	2
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T69	1		T70	1		T71	5
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T69	4		T70	2		T71	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T133	1		T134	1		T140	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T71	1		T130	1		T143	1