Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	58.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success	0.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.readback.en	33.33	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	6	0	0.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	6	0	0.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.readback.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
33.33	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.readback.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	4	2	33.33

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.readback.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	4	2	33.33	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	6	0	0.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
false	0	1	1
true	0	1	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	4	2	33.33

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

152

1

T4

1

T99

1

T81

1

true

166

1

T7

1

T8

1

T11

1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	107	1			T3	2		T5	1		T9	1
others[1]	97	1			T6	2		T9	1		T145	1
others[2]	96	1			T3	1		T6	1		T9	1
others[3]	186	1			T3	1		T6	1		T9	4
false	1022	1			T3	9		T5	4		T6	8
true	922	1			T3	3		T5	2		T6	9

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	102	1			T3	2		T6	2		T9	2
others[1]	777	1			T3	6		T5	1		T6	5
others[2]	5810	1			T1	1		T2	27		T3	6
others[3]	192	1			T5	2		T6	3		T9	2
false	49	1			T9	1		T145	1		T17	2
true	33	1			T9	1		T16	1		T146	1